BS616LV1011EIP70 [BSI]

Very Low Power/Voltage CMOS SRAM 64K X 16 bit; 非常低的功率/电压CMOS SRAM 64K ×16位


型号：	BS616LV1011EIP70
厂家：	BRILLIANCE SEMICONDUCTOR
描述：	Very Low Power/Voltage CMOS SRAM 64K X 16 bit 非常低的功率/电压CMOS SRAM 64K ×16位静态存储器
文件：	总9页 (文件大小：262K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Very Low Power/Voltage CMOS SRAM

64K X 16 bit

BSI

BS616LV1011

FEATURES

• Fully static operation

• Wide Vcc operation voltage : 2.4 ~ 5.5V

• Very low power consumption :

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

Vcc = 3.0V C-grade : 22mA (@55ns) operating current

I- grade : 23mA (@55ns) operating current

C-grade : 17mA (@70ns) operating current

I- grade : 18mA (@70ns) operating current

0.4uA (Typ.) CMOS standby current

Vcc = 5.0V C-grade : 48mA (55ns) operating current

I- grade : 50mA (55ns) operating current

C-grade : 36mA (70ns) operating current

I- grade : 38mA (70ns) operating current

1.3uA (Typ.) CMOS standby current

• I/O Configuration x8/x16 selectable by LB and UB pin

DESCRIPTION

The BS616LV1011 is a high performance , very low power CMOS Static

Random Access Memory organized as 65,536 words by 16 bits and

operates from a wide range of 2.4V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current

of 0.4uA at 3V/25^oC and maximum access time of 55ns at 3V/85^oC.

Easy memory expansion is provided by an active LOW chip enable

(CE) and active LOW output enable(OE) and three-state output drivers.

The BS616LV1011 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

• High speed access time :

-55

-70

55ns

70ns

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

The BS616LV1011 is available in the JEDEC standard 44-pin TSOP

Type II and 48-pin BGA package.

PRODUCT FAMILY

POWER DISSIPATION

SPEED

(ns)

STANDBY

Operating

(ICC, Max)

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

PKG TYPE

(ICCSB1, Max)

Vcc=5.0V

70ns

Vcc=3.0V

70ns

55ns:2.8~5.5V

70ns:2.5~5.5V

Vcc=5.0V

Vcc=3.0V

1.3uA

BS616LV1011EC

TSOP2-44

+0 ^OC to +70 ^O

-40 ^OC to +85 ^O

2.4V ~ 5.5V

55/70

4uA

8uA

36mA

17mA

18mA

BS616LV1011AC

BS616LV1011EI

BS616LV1011AI

BGA-48-0608

TSOP2-44

2.5uA

38mA

BGA-48-0608

PIN CONFIGURATIONS

BLOCK DIAGRAM

DQ0

DQ1

DQ2

DQ3

VCC

GND

DQ4

DQ5

DQ6

DQ7

A13

DQ15

Address

A15

DQ14

DQ13

DQ12

GND

VCC

DQ11

DQ10

DQ9

DQ8

512

A14

A12

BS616LV1011EC

BS616LV1011EI

Input

Row

Decoder

Memory Array

512 x 2048

Buffer

A15

A14

A13

A12

A10

A11

2048

Data

Input

Column I/O

DQ0

Buffer

Write Driver

Sense Amp

128

Data

Output

IO0

IO2

Buffer

Column Decoder

DQ15

IO8

IO9

IO10

IO11

IO12

IO13

IO1

IO3

IO4

IO5

A11

Control

Address Input Buffer

VSS

VCC

IO14

IO15

A14

A12

VCC

VSS

IO6

IO7

A11 A9 A3 A2 A1

A0 A10

A15

A13

A10

Vcc

Gnd

Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.

Revision 1.0

R0201-BS616LV1011

Apr.

2004

BSI

BS616LV1011

PIN DESCRIPTIONS

Name

Function

A0-A15 Address Input

These 16 address inputs select one of the 65,536 x 16-bit words in the RAM.

CE Chip Enable Input

WE Write Enable Input

CE is active LOW. Chip enables must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

Lower byte and upper byte data input/output control pins.

LB and UB Data Byte Control Input

DQ0 - DQ15 Data Input/Output

Ports

These 16 bi-directional ports are used to read data from or write data into the RAM.

Vcc

Power Supply

Ground

Gnd

TRUTH TABLE

MODE

DQ0~DQ7

DQ8~DQ15

Vcc CURRENT

Not selected

(Power Down)

High Z

_CCSB, I_CCSB1

Output Disabled

High Z

Dout

High Z

Dout

Din

High Z

Dout

High Z

Din

I_CC

Read

Write

Din

Revision 1.0

Apr. 2004

R0201-BS616LV1011

BSI

BS616LV1011

OPERATING RANGE

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

AMBIENT

TEMPERATURE

0 ^OC to +70 ^O

SYMBOL

PARAMETER

RATING

UNITS

RANGE

Vcc

Terminal Voltage with

Respect to GND

-0.5 to

Vcc+0.5

-0.5 to

TERM

Commercial

Industrial

2.4V ~ 5.5V

Power Supply Voltage

Temperature Under Bias

Storage Temperature

Power Dissipation

Vcc+0.5

-40 ^OC to +85 ^O

-40 to +85

-60 to +150

1.0

^OC

BIAS

STG

CAPACITANCE ⁽¹⁾(TA = 25^oC, f = 1.0 MHz)

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

DC Output Current

OUT

Input

CIN

VIN=0V

Capacitance

Input/Output

Capacitance

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

CDQ

VI/O=0V

1. This parameter is guaranteed and not 100% tested.

DC ELECTRICAL CHARACTERISTICS ( TA = -40^oC to + 85^oC )

PARAMETER

MIN. TYP. ⁽¹⁾MAX.

UNITS

PARAMETER

TEST CONDITIONS

NAME

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

Guaranteed Input Low

Voltage⁽²⁾

V^IL

-0.5

0.8

Guaranteed Input High

2.0

2.2

VIH

I^IL

Vcc+0.3

Voltage⁽³⁾

Input Leakage Current

Output Leakage Current

Vcc = Max, V^IN= 0V to Vcc

Vcc = Max, CE = V^IH, or OE = V^IH

I^LO

^I/O= 0V to Vcc

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

V^OL

V^OH

Output Low Voltage

Output High Voltage

Vcc = Max, I^OL= 2mA

Vcc = Min, I^OH= -1mA

0.4

2.4

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

Vcc=3.0V

Vcc=5.0V

Operating Power Supply CE = V^IL, I^DQ= 0mA,

Current

(6)

I^CC

70ns

F = Fmax⁽⁴⁾

I^CCSB

Standby Current-TTL

CE = V^IH, I^DQ= 0mA

CE ≧ Vcc-0.2V,

0.4

1.3

2.5

(5)

I^CCSB1

Standby Current-CMOS

^IN≧ Vcc - 0.2V or V^IN≦ 0.2V

1. Typical characteristics are at TA = 25^oC.

3. Overshoot : Vcc+1.5V in case of pulse width ≦20ns.

5. IccsB1_Max. is 1.3uA/4.0uA at Vcc=3.0V/5.0V and TA=70^oC.

2. Undershoot : -1.5V in case of pulse width ≦20ns.

4. Fmax = 1/t_RC

6. Icc_Max. is 23mA(@3V)/ 50mA(@5V) under 55ns operation.

DATA RETENTION CHARACTERISTICS ( TA = -40^oC to + 85^oC )

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP. ⁽¹⁾MAX.

UNITS

CE ≧ Vcc - 0.2V

V^IN≧ Vcc - 0.2V or V^IN≦ 0.2V

V_DR

Vcc for Data Retention

1.5

CE ≧ Vcc - 0.2V

V^IN≧ Vcc - 0.2V or V^IN≦ 0.2V

(3)

I_CCDR

Data Retention Current

0.15

0.8

Chip Deselect to Data

Retention Time

t_CDR

t_R

See Retention Waveform

(2)

Operation Recovery Time

T_RC

1. Vcc = 1.5V, T_A= + 25^OC

3. IccDR_MAX. is 0.45uA at TA=70^OC.

2. t_RC= Read Cycle Time

Revision 1.0

R0201-BS616LV1011

Apr.

2004

BSI

BS616LV1011

LOW V_CCDATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

^DR≥ 1.5V

Vcc

CDR

≥

CE Vcc - 0.2V

VIH

KEY TO SWITCHING WAVEFORMS

AC TEST CONDITIONS

(Test Load and Input/Output Reference)

Input Pulse Levels

Vcc / 0V

WAVEFORM

INPUTS

OUTPUTS

MUST BE

STEADY

MUST BE

STEADY

Input Rise and Fall Times

1V/ns

MAY CHANGE

FROM H TO L

WILL BE

CHANGE

FROM H TO L

Input and Output

Timing Reference Level

0.5Vcc

MAY CHANGE

FROM L TO H

WILL BE

CHANGE

FROM L TO H

Output Load

C_L= 30pF+1TTL

C_L= 100pF+1TTL

DON T CARE:

CHANGE :

STATE

UNKNOWN

ANY CHANGE

PERMITTED

DOES NOT

APPLY

CENTER

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

AC ELECTRICAL CHARACTERISTICS ( TA = -40^oC to + 85^oC )

READ CYCLE

JEDEC

PARAMETER

CYCLE TIME : 70ns

CYCLE TIME : 55ns

(Vcc = 2.8~5.5V)

PARAMETER

(Vcc = 2.5~5.5V)

DESCRIPTION

Read Cycle Time

UNIT

NAME

MIN. TYP. MAX.

NAME

AVAX

Address Access Time

AVQV

Chip Select Access Time

ELQV

ACS

(1)

Data Byte Control Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Data Byte Control to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Data Byte Control to Output High Z

Output Disable to Output in High Z

(LB,UB)

GLQV

E1LQX

CLZ

GLQX

OLZ

EHQZ

CHZ

BDO

GHQZ

OHZ

Data Hold from Address Change

AXOX

NOTE :

1. tBA is 25ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.

Revision 1.0

Apr. 2004

R0201-BS616LV1011

BSI

BS616LV1011

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 ^(1,2,4)

ADDRESS

D _OUT

READ CYCLE2 ^(1,3,4)

ACS

LB,UB

(5)

CHZ

BDO

(5)

CLZ

D _OUT

READ CYCLE3 ^(1,4)

ADDRESS

OLZ

(5)

₍₅₎t ACS

OHZ

(1,5)

CHZ

CLZ

LB,UB

D _OUT

BDO

NOTES:

1. WE is high for read Cycle.

2. Device is continuously selected when CE = V^IL

3. Address valid prior to or coincident with CE transition low.

4. OE = V^IL

5. The parameter is guaranteed but not 100% tested.

Revision 1.0

Apr. 2004

R0201-BS616LV1011

BSI

BS616LV1011

AC ELECTRICAL CHARACTERISTICS ( TA = -40^oC to + 85^oC )

WRITE CYCLE

JEDEC

PARAMETER

NAME

CYCLE TIME : 55ns

(Vcc = 2.8~5.5V)

CYCLE TIME : 70ns

PARAMETER

(Vcc = 2.5~5.5V)

DESCRIPTION

Write Cycle Time

UNIT

NAME

MIN. TYP. MAX.

t_AVAX

t_E1LWH

t_AVWL

t_AVWH

t_WLWH

t_WHAX

t_BW

t_WC

t_CW

t_AS

Chip Select to End of Write

Address Setup Time

Address Valid to End of Write

Write Pulse Width

t_AW

t_WP

t_WR

Write recovery Time

(CE,WE)

(1)

Date Byte Control to End of Write

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

(LB,UB)

t_BW

t_WHZ

t_DW

t_DH

t_WLQZ

t_DVWH

t_WHDX

t_GHQZ

t_OHZ

t_WHOX

t_OW

End of Write to Output Active

NOTE :

1. tBW is 35ns/45ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1 ⁽¹⁾

ADDRESS

(3)

(11)

(5)

LB,UB

(3)

(2)

(4,10)

OHZ

D _OUT

D _IN

Revision 1.0

Apr. 2004

R0201-BS616LV1011

BSI

BS616LV1011

(1,6)

WRITE CYCLE2

ADDRESS

(11)

(5)

LB,UB

(3)

(2)

(4,10)

(7)

(8)

WHZ

D _OUT

(8,9)

D _IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.

The data input setup and hold timing should be referenced to the second transition edge of

the signal that terminates the write.

3. T^WRis measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V^IL).

7. D^OUTis the same phase of write data of this write cycle.

8. D^OUTis the read data of next address.

9. If CE goes low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. The parameter is guaranteed but not 100% tested.

11. T^CWis measured from the later of CE going low to the end of write.

Revision 1.0

R0201-BS616LV1011

Apr.

2004

BSI

BS616LV1011

ORDERING INFORMATION

BS616LV1011 X X Z Y Y

SPEED

55: 55ns

70: 70ns

PKG MATERIAL

-: Normal

G: Green

P: Pb free

GRADE

C: +0^oC ~ +70^oC

I: -40^oC ~ +85^oC

PACKAGE

E: TSOP2-44

A: BGA-48-0608

Note:

BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products

for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support

systems and critical medical instruments.

PACKAGE DIMENSIONS

TSOP2-44

Revision 1.0

Apr. 2004

R0201-BS616LV1011

BSI

BS616LV1011

PACKAGE DIMENSIONS (continued)

NOTES:

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

BALL PITCH e = 0.75

8.0

6.0

5.25

3.75

VIEW A

48 mini-BGA (6 x 8)

Revision 1.0

Apr. 2004

R0201-BS616LV1011

BS616LV1011EIP70 [BSI]

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