BS616LV2016DI-55 [BSI]
Very Low Power/Voltage CMOS SRAM 128K X 16 bit; 非常低的功率/电压CMOS SRAM 128K ×16位
| 型号： | BS616LV2016DI-55 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 128K X 16 bit |
| 文件： | 总9页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BSI
BS616LV2016
FEATURES
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
• Easy expansion with CE and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
Vcc = 3.0V C-grade: 29mA (@55ns) operating current
I -grade: 30mA (@55ns) operating current
C-grade: 24mA (@70ns) operating current
I -grade: 25mA (@70ns) operating current
0.3uA(Typ.) CMOS standbycurrent
Vcc = 5.0V C-grade: 60mA (@55ns) operating current
I -grade: 62mA (@55ns) operating current
C-grade: 53mA (@70ns) operating current
I -grade: 55mA (@70ns) operating current
1.0uA(Typ.) CMOS standbycurrent
DESCRIPTION
The BS616LV2016 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V/25oC and maximum access time of 55ns at 3.0V/85oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2016 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• High speed access time :
-55
-70
55ns
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
The BS616LV2016 is available in DICE form , JEDEC standard 44-pin
TSOP Type II package and 48-ball BGA package.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
55ns: 3.0~5.5V
70ns: 2.7~5.5V
Vcc=3.0V
70ns
Vcc=5.0V
70ns
Vcc=3.0V
Vcc=5.0V
BS616LV2016DC
BS616LV2016EC
BS616LV2016AC
BS616LV2016DI
BS616LV2016EI
BS616LV2016AI
DICE
+0 O C to +70O
-40 O C to +85O
C
C
2.4V ~5.5V
2.4V ~ 5.5V
55/70
55/70
3.0uA
5.0uA
53mA
10uA
24mA
25mA
TSOP2-44
BGA-48-0608
DICE
TSOP2-44
BGA-48-0608
30uA
55mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
1
44
43
A4
A5
2
A3
A6
3
42
A2
A1
A7
4
41
A8
A13
OE
5
40
A0
UB
6
39
CE
LB
A15
7
Address
38
37
DQ0
DQ15
DQ14
20
8
9
A16
A14
1024
DQ1
36
Input
DQ2
DQ13
Row
Memory Array
1024 x 2048
10
35
DQ3
DQ12
A12
A7
BS616LV2016EC
BS616LV2016EI
11
12
13
14
15
16
17
18
19
20
21
22
34
33
VCC
GND
DQ4
DQ5
DQ6
DQ7
WE
GND
Buffer
Decoder
VCC
32
31
A6
A5
A4
DQ11
DQ10
DQ9
30
29
DQ8
2048
28
NC
Data
Input
Buffer
27
A16
A15
A14
A13
A12
A8
16
16
16
Column I/O
26
25
A9
DQ0
A10
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
24
A11
23
NC
128
Data
Output
1
2
3
4
5
6
16
Buffer
Column Decoder
DQ15
A
B
C
D
E
F
LB
D8
D9
OE
UB
A0
A3
A1
A4
A2
N.C.
D0
14
CE
D1
D3
CE
WE
OE
UB
Control
Address Input Buffer
D10
D11
D12
D13
A5
A6
D2
N.C.
VSS
A7
VCC
VSS
LB
A11 A9 A3 A2 A1
A0 A10
VCC
N.C.
A14
A12
A9
A16
A15
A13
A10
D4
D5
Vcc
Gnd
D14
D15
N.C.
D6
D7
WE
G
H
N.C.
A8
N.C.
A11
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.1
R0201-BS616LV2016
1
Jan.
2004
BS616LV2016
BSI
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
CE
H
WE
X
OE
X
LB
X
UB
D0~D7
High Z
High Z
High Z
High Z
Dout
D8~D15
Vcc CURRENT
Not selected
(Power Down)
X
H
H
X
L
High Z
High Z
High Z
High Z
Dout
Dout
High Z
Din
ICCSB , ICCSB1
X
X
X
H
ICCSB , ICCSB1
L
L
ICC
ICC
ICC
ICC
ICC
ICC
ICC
ICC
X
H
X
H
H
X
Output Disabled
Read
L
H
L
L
L
H
L
L
L
High Z
Dout
H
L
L
Din
Write
X
H
L
L
X
Din
H
Din
X
Revision 1.1
Jan. 2004
R0201-BS616LV2016
2
BS616LV2016
OPERATING RANGE
BSI
ABSOLUTE MAXIMUM RATINGS(1)
AMBIENT
TEMPERATURE
0 O C to +70O
SYMBOL
PARAMETER
RATING
UNITS
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
V
TERM
BIAS
STG
T
V
T
T
P
Commercial
Industrial
C
2.4V ~ 5.5V
2.4V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +85
-60 to +150
1.0
O C
O C
W
-40O C to +85O
C
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
PARAMETER
CONDITIONS
MAX. UNIT
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Input
IN
IN
C
V
=0V
6
8
pF
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER
UNITS
PARAMETER
TEST CONDITIONS
Vcc =3.0V
MIN.
TYP. (1) MAX.
NAME
Guaranteed Input Low
Voltage(3)
VIL
-0.5
--
--
0.8
V
Vcc =5.0V
Vcc =3.0V
Vcc =5.0V
2.0
2.2
--
Guaranteed Input High
Voltage(3)
IH
cc+0.3
V
V
V
IIL
Input Leakage Current
Output Leakage Current
Vcc = Max, VIN = 0V to Vcc
--
--
1
1
uA
uA
Vcc = Max,CE = VIH or OE = VIH
,
LO
I
--
V
I/O = 0V to Vcc
Vcc =3.0V
Vcc =5.0V
Vcc =3.0V
Vcc =5.0V
OL
OL
V
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2.0mA
--
--
0.4
--
V
OH
OH
Vcc = Min, I = -1.0mA
2.4
--
--
--
--
V
Vcc =3V
Vcc =5V
70ns
70ns
25
55
Operating Power Supply CE = VIL
Current
,
(5)
CC
I
mA
mA
I
DQ = 0mA, F = Fmax(2)
Vcc =3.0V
0.5
1.0
IH
CE=V
ICCSB
Standby Current-TTL
--
I
DQ = 0mA
Vcc =5.0V
Vcc =3.0V
Vcc =5.0V
0.3
1.0
5
,
CE≧Vcc-0.2V
V
(4)
CCSB1
I
Standby Current-CMOS
--
uA
IN≧Vcc-0.2V or VIN≦0.2V
30
1. Typical characteristics are at TA = 25oC.
2. Fmax = 1/tRC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4.IccsB1_Max. is 3uA/10uA at Vcc=3V/5V and TA=70oC.
5. Icc_Max. is 30mA(@3V) / 62mA(@5V) under 55ns operation.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
(3)
CE ≧ Vcc - 0.2V
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
ICCDR
Data Retention Current
--
0
0.1
1.0
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
2. tRC = Read Cycle Time
3
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
3. IccDR_MAX. is 0.7uA at TA=70oC.
Revision 1.1
Jan.
R0201-BS616LV2016
2004
BS616LV2016
BSI
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
Vcc
t
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
0.5Vcc
Timing Reference Level
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 100pF+1TTL
CL = 30pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE
JEDEC
PARAMETER
CYCLE TIME : 70ns
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
PARAMETER
(Vcc = 2.7~5.5V)
DESCRIPTION
Read Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
NAME
t
t
55
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
30
30
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAX
RC
t
t
Address Access Time
AVQV
AA
t
t
Chip Select Access Time
(CE)
--
--
ELQV
ACS
(1)
t
t
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
(LB,UB)
--
--
BA
BA
t
t
--
--
GLQV
OE
t
t
10
10
5
10
10
5
(CE)
E1LQX
CLZ
t
t
(LB,UB)
--
--
BE
BE
t
t
--
--
GLQX
OLZ
t
t
--
30
30
25
--
35
35
30
(CE)
EHQZ
CHZ
t
t
(LB,UB)
--
--
BDO
BDO
t
t
--
--
GHQZ
OHZ
t
t
Data Hold from Address Change
AXOX
OH
10
--
--
10
--
--
ns
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
Revision 1.1
Jan. 2004
R0201-BS616LV2016
4
BSI
BS616LV2016
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
t
BA
LB,UB
(5)
CHZ
t
t
BE
t
BDO
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
(5) t ACS
t
t
OHZ
(1,5)
CHZ
t
CLZ
t
BA
LB,UB
D OUT
t
BE
t
BDO
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
5. The parameter is guaranteed but not 100% tested.
.
.
Revision 1.1
Jan. 2004
R0201-BS616LV2016
5
BS616LV2016
BSI
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE
JEDEC
PARAMETER
NAME
CYCLE TIME : 55ns
(Vcc = 3.0~5.5V)
CYCLE TIME : 70ns
PARAMETER
(Vcc = 2.7~5.5V)
DESCRIPTION
Write Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tCW
tAS
Chip Select to End of Write
Address Setup Time
(CE)
--
--
Address Valid to End of Write
Write Pulse Width
55
30
0
--
70
35
0
--
tAW
tWP
tWR
--
--
Write recovery Time
--
--
(CE,WE)
(LB,UB)
(1)
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
25
--
--
30
--
--
tBW
tWHZ
tDW
tDH
tWLQZ
tDVWH
tWHDX
tGHQZ
25
--
30
--
25
0
30
0
--
--
--
25
--
30
tOHZ
tWHOX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
NOTE :
1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(11)
CW
t
(5)
CE
t
BW
LB,UB
WE
t
AW
(3)
t
WP
(2)
t
AS
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 1.1
Jan. 2004
R0201-BS616LV2016
6
BS616LV2016
BSI
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
(11)
t
CW
(5)
CE
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
(7)
(8)
t
WHZ
t
OW
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 1.1
R0201-BS616LV2016
7
Jan.
2004
BS616LV2016
BSI
ORDERING INFORMATION
BS616LV2016 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
E: TSOP2-44
A: BGA-48-0608
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8)
Revision 1.1
Jan. 2004
R0201-BS616LV2016
8
BS616LV2016
BSI
PACKAGE DIMENSIONS
TSOP2-44
Revision 1.1
R0201-BS616LV2016
9
Jan.
2004
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