BS616LV2019DIP70 [BSI]
Very Low Power/Voltage CMOS SRAM 128K X 16 bit; 非常低的功率/电压CMOS SRAM 128K ×16位
| 型号： | BS616LV2019DIP70 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power/Voltage CMOS SRAM 128K X 16 bit |
| 文件： | 总10页 (文件大小：283K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power/Voltage CMOS SRAM
128K X 16 bit
BSI
BS616LV2019
FEATURES
• Easy expansion with CE and OE options
• Vcc operation voltage range : 2.7V ~ 3.6V
• Very low power consumption :
• I/O Configuration x8/x16 selectable by LB and UB pin
Vcc = 3.0V C-grade: 23mA (@55ns) operating current
I -grade: 25mA (@55ns) operating current
C-grade: 15mA (@70ns) operating current
I -grade: 16mA (@70ns) operating current
0.3uA(Typ.) CMOS standbycurrent
DESCRIPTION
The BS616LV2019 is a high performance , very low power CMOS Static
Random Access Memory organized as 131,072 words by 16 bits and
operates from a range of 2.7V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.3uA at 3.0V/25oC and maximum access time of 55ns at 2.7V/85oC.
Easy memory expansion is provided by active LOW chip enable (CE),
active LOW output enable(OE) and three-state output drivers.
The BS616LV2019 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• High speed access time :
-55
-70
55ns
70ns
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
The BS616LV2019 is available in DICE form , JEDEC standard 48-pin
TSOP Type I package and 48-ball BGA package.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
( ns )
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
TEMPERATURE
Vcc
RANGE
( ICCSB1, Max )
( ICC, Max )
PKG TYPE
55ns: 2.7~3.6V
70ns: 2.7~3.6V
Vcc=3.0V
Vcc=3.0V
70ns
55ns
BS616LV2019DC
BS616LV2019TC
BS616LV2019AC
BS616LV2019DI
BS616LV2019TI
BS616LV2019AI
DICE
+0 O C to +70O
-40 O C to +85O
C
C
2.7V ~3.6V
2.7V ~ 3.6V
55/70
55/70
15mA
16mA
3.0uA
23mA
TSOP1-48
BGA-48-0608
DICE
TSOP1-48
BGA-48-0608
25mA
5.0uA
PIN CONFIGURATIONS
BLOCK DIAGRAM
A15
1
48
47
46
A16
NC
A14
A13
A12
A11
A10
A9
VSS
IO15
IO7
A8
A13
IO14
IO6
A15
Address
A8
IO13
IO5
20
A16
A14
1024
NC
NC
/WE
CE2
NC
/UB
/LB
NC
NC
A7
9
Input
10
IO12
IO4
Row
Memory Array
1024 x 2048
A12
A7
37
VCC
IO11
IO3
BS616LV2019TC
BS616LV2019TI
Buffer
13
Decoder
IO10
IO2
A6
A5
A4
16
17
IO9
IO1
A6
IO8
2048
A5
IO0
A4
/OE
VSS
Data
Input
Buffer
A3
27
25
16
16
16
Column I/O
A2
/CE
A0
DQ0
A1
24
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
1
2
3
4
5
6
128
Data
Output
16
A
B
C
D
E
F
LB
D8
OE
UB
A0
A3
A1
A4
A2
N.C.
D0
Buffer
Column Decoder
DQ15
CE
D1
D3
14
CE2,CE
WE
D9
D10
D11
D12
D13
A5
A6
D2
Control
Address Input Buffer
OE
N.C.
VSS
VCC
A7
VCC
VSS
UB
LB
N.C.
A14
A12
A9
A16
A15
A13
A10
D4
D5
A11 A9 A3 A2 A1
A0 A10
D14
D15
N.C.
D6
D7
Vcc
Gnd
WE
A11
G
H
N.C.
A8
N.C.
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
Revision 1.2
R0201-BS616LV2019
1
May
2004
BS616LV2019
BSI
PIN DESCRIPTIONS
Name
Function
A0-A16 Address Input
These 17 address inputs select one of the 131,072 x 16-bit words in the RAM.
CE is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected. (48B BGA ignore CE2 pin)
CE Chip Enable 1 Input
CE2 Chip Enable 2 Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins.
LB and UB Data Byte Control Input
DQ0 - DQ15 Data Input/Output
Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
CE
H
CE2 (1) WE
OE
X
LB
X
UB
D0~D7
High Z
High Z
High Z
High Z
Dout
D8~D15
High Z
High Z
High Z
High Z
Dout
Vcc CURRENT
X
L
X
X
X
X
H
X
L
ICCSB , ICCSB1
Not selected
(Power Down)
X
X
X
ICCSB , ICCSB1
X
L
ICCSB , ICCSB1
X
H
X
H
X
H
H
X
Output Disabled
Read
ICC
ICC
ICC
ICC
ICC
ICC
ICC
L
H
L
L
L
H
H
H
L
L
L
High Z
Dout
Dout
H
L
High Z
Din
L
Din
Write
X
H
L
L
X
Din
H
Din
X
1. 48B BGA ignore CE2 condition.
Revision 1.2
May 2004
R0201-BS616LV2019
2
BS616LV2019
OPERATING RANGE
BSI
ABSOLUTE MAXIMUM RATINGS(1)
SYMBOL
PARAMETER
RATING
UNITS
AMBIENT
TEMPERATURE
0 O C to +70O
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5
-0.5 to
V
V
TERM
cc
V
V
T
T
P
Commercial
Industrial
C
2.7V ~ 3.6V
2.7V ~ 3.6V
Power Supply
Vcc+0.5
-40O C to +85O
C
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
-40 to +85
-60 to +150
1.0
O C
O C
W
BIAS
STG
T
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
20
mA
SYMBOL
PARAMETER
CONDITIONS
MAX. UNIT
OUT
I
Input
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
IN
C
IN
V
=0V
6
8
pF
pF
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
1. This parameter is guaranteed and not 100% tested.
DC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
PARAMETER
TYP.(1) MAX.
UNITS
PARAMETER
TEST CONDITIONS
MIN.
NAME
Guaranteed Input Low
Voltage(2)
VIL
Vcc =3.0V
Vcc =3.0V
-0.3
--
0.8
V
Guaranteed Input High
VIH
IIL
2.0
--
--
--
Vcc+0.3
1
V
Voltage(2)
IN
Input Leakage Current
Output Leakage Current
Vcc = Max, V = 0V to Vcc
uA
Vcc = Max,CE = VIH or CE2 (4) = VIL or OE = VIH
,
ILO
--
--
1
uA
V
I/O = 0V to Vcc
OL
VOL
VOH
Output Low Voltage
Output High Voltage
Vcc = Max, I = 2.0mA
Vcc =3.0V
Vcc =3.0V
--
--
--
0.4
--
V
V
OH
Vcc = Min, I = -1.0mA
2.4
(4)
70ns
55ns
16
25
IL
IH
Operating Power Supply CE = V , CE2 = V
(6)
ICC
3.0 V
--
--
--
--
--
mA
mA
uA
Current
I
DQ = 0mA, F = Fmax(3)
(4)
IH
IL
CE=V or CE2 =V
ICCSB
Standby Current-TTL
Vcc =3.0V
0.5
5.0
I
DQ = 0mA
CE≧Vcc-0.2V or CE2(4)≦0.2V,
IN≧Vcc-0.2V or VIN≦0.2V
(5)
ICCSB1
Standby Current-CMOS
Vcc =3.0V
0.3
V
1. Typical characteristics are at TA = 25oC.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC 4. 48B BGA ignore CE2 condition.
5.IccsB1_Max. is 3.0uA at Vcc=3.0V and TA=70oC.
6. Icc_Max. is 23mA(@55ns) / 15mA(@70ns) at Vcc=3.0V/ 0~70oC.
.
DATA RETENTION CHARACTERISTICS ( TA = -40 to + 85oC )
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
TYP.(1)
MAX.
UNITS
CE ≧ Vcc - 0.2V or CE2 ≦ 0.2V(3)
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
,
,
VDR
Vcc for Data Retention
1.5
--
--
V
CE ≧ Vcc - 0.2V or CE2 ≦ 0.2V(3)
VIN ≧ Vcc - 0.2V or VIN ≦ 0.2V
(4)
ICCDR
Data Retention Current
--
0
0.1
1.0
uA
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
TRC
1. Vcc = 1.5V, TA = + 25OC
3. 48B BGA ignore CE2 condition.
2. tRC = Read Cycle Time
4. IccDR is 0.7uA at TA=70oC.
Revision 1.2
R0201-BS616LV2019
3
May
2004
BS616LV2019
BSI
LOW VCC DATA RETENTION WAVEFORM ( CE Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
Vcc
t
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
CE
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
FROM H TO L
Input and Output
0.5Vcc
Timing Reference Level
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
Output Load
CL = 100pF+1TTL
CL = 30pF+1TTL
,
DON T CARE:
CHANGE :
STATE
UNKNOWN
ANY CHANGE
PERMITTED
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
READ CYCLE (48B BGA ignore CE2 condition)
JEDEC
PARAMETER
CYCLE TIME : 55ns
CYCLE TIME : 70ns
PARAMETER
(Vcc = 2.7~3.6V)
(Vcc = 2.7~3.6V)
DESCRIPTION
Read Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
NAME
t
t
55
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
30
30
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
35
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAX
RC
t
t
Address Access Time
AVQV
AA
t
t
Chip Select Access Time
(CE,CE2)
(LB,UB)
--
--
ELQV
ACS1 , 2
(1)
t
t
Data Byte Control Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
--
--
BA
BA
t
t
--
--
GLQV
OE
t
t
10
10
5
10
10
5
(CE,CE2)
(LB,UB)
E1LQX
CLZ
t
t
--
--
BE
BE
t
t
--
--
GLQX
OLZ
t
t
--
30
30
25
--
35
35
30
(CE,CE2)
(LB,UB)
EHQZ
CHZ
t
t
--
--
BDO
BDO
t
t
--
--
GHQZ
OHZ
t
t
Data Hold from Address Change
AXOX
OH
10
--
--
10
--
--
ns
NOTE :
1. tBA is 30ns/35ns (@speed=55ns/70ns) with address toggle. ; tBA is 55ns/70ns (@speed=55ns/70ns) without address toggle.
Revision 1.2
May 2004
R0201-BS616LV2019
4
BSI
BS616LV2019
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
(6)
t
ACS2
t
ACS1
CE
(5,6)
(5,6)
CLZ
t
CHZ
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
t
AA
OE
t
OH
t
OE
CE2
CE
(6)
ACS2
t
OLZ
(5)
t
ACS1
t
OHZ
(1,5,6)
CHZ
(5,6)
CLZ
t
t
LB,UB
t
BE
t
BDO
t
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
5. The parameter is guaranteed but not 100% tested.
6. 48B BGA ignore this parameters related to CE2 .
Revision 1.2
May 2004
R0201-BS616LV2019
5
BS616LV2019
BSI
AC ELECTRICAL CHARACTERISTICS ( TA = -40 to + 85oC )
WRITE CYCLE (48B BGA ignore CE2 condition)
JEDEC
PARAMETER
NAME
CYCLE TIME : 70ns
CYCLE TIME : 55ns
(Vcc = 2.7~3.6V)
PARAMETER
(Vcc = 2.7~3.6V)
DESCRIPTION
Write Cycle Time
UNIT
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWC
tCW
tAS
Chip Select to End of Write
Address Setup Time
(CE,CE2)
--
--
Address Valid to End of Write
Write Pulse Width
55
30
0
--
70
35
0
--
tAW
tWP
tWR
--
--
Write recovery Time
--
--
(CE,CE2,WE)
(LB,UB)
(1)
Date Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
25
--
--
30
--
--
tBW
tWHZ
tDW
tDH
tWLQZ
tDVWH
tWHDX
tGHQZ
25
--
30
--
25
0
30
0
--
--
--
25
--
30
tOHZ
tWHOX
tOW
End of Write to Output Active
5
--
--
5
--
--
ns
NOTE :
1. tBW is 25ns/30ns (@speed=55ns/70ns) with address toggle. ; tBW is 55ns/70ns (@speed=55ns/70ns) without address toggle.
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(5,12)
(5)
CE2
CE
(11)
CW
t
t
BW
(5)
LB,UB
t
AW
(3)
t
WP
(2)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 1.2
May 2004
R0201-BS616LV2019
6
BS616LV2019
BSI
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
CE2
(5,12)
(5)
(11)
CW
t
CE
t
BW
(5)
LB,UB
t
t
WR
t
AW
(3)
t
WP
(2)
WE
t
AS
(4,10)
WHZ
OW
(7)
(8)
t
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE going low to the end of write.
12. 48B BGA ignore this parameters related to CE2 .
Revision 1.2
May 2004
R0201-BS616LV2019
7
BS616LV2019
BSI
ORDERING INFORMATION
BS616LV2019 X X Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
T: TSOP1-48
A: BGA-48-0608
D: DICE
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products
for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support
systems and critical medical instruments.
PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8)
Revision 1.2
May 2004
R0201-BS616LV2019
8
BS616LV2019
BSI
PACKAGE DIMENSIONS
UNIT
SYMBOL
HD
INCH
MM
A
0.0433±0.004
1.10±0.10
0.10±0.05
1.00±0.05
0.22±0.05
0.20±0.03
0.10 ~ 0.21
0.10 ~ 0.16
16.40±0.10
11.80±0.10
0.50±0.10
18.00±0.20
0.60±0.15
0.80±0.10
0.1 Max.
A1 0.004±0.002
A2 0.039±0.002
1
48
b
0.009±0.002
b1 0.008±0.001
0.004 ~ 0.008
c1 0.004 ~ 0.006
c
D
E
e
0.645±0.004
0.472±0.004
0.020±0.004
HD 0.708±0.008
0.0236±0.006
L1 0.0315±0.004
L
24
25
12°(2x)
Seating Plane
y
y
θ
0.004 Max.
"A"
0°~ 8°
0°~ 8°
D
GAUGE PLANE
A
A
24
25
SEATING PLANE
12°(2x)
L
b
L1
WITH PLATING
"A" DETAIL VIEW
c
c1
BASE METAL
b1
SECTION A-A
48
1
TSOP1-48PIN
Revision 1.2
May 2004
R0201-BS616LV2019
9
BS616LV2019
BSI
REVISION HISTORY
Revision Description
Date
Note
1.1
Initial release
Jan., 05, 2004
1.2
Change Vcc_min
from 2.4V to 2.7V
May, 03, 2004
Revision 1.2
R0201-BS616LV2019
10
May
2004
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Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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