BS616LV4017ECG55 [BSI]

Very Low Power CMOS SRAM 256K X 16 bit; 超低功耗CMOS SRAM 256K ×16位


型号：	BS616LV4017ECG55
厂家：	BRILLIANCE SEMICONDUCTOR
描述：	Very Low Power CMOS SRAM 256K X 16 bit 超低功耗CMOS SRAM 256K ×16位静态存储器
文件：	总11页 (文件大小：242K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Very Low Power CMOS SRAM

256K X 16 bit

BS616LV4017

Pb-Free and Green package materials are compliant to RoHS

FEATURES

DESCRIPTION

y Wide V_CCoperation voltage : 2.4V ~ 5.5V

y Very low power consumption :

The BS616LV4017 is a high performance, very low power CMOS

Static Random Access Memory organized as 262,144 by 16 bits and

operates form a wide range of 2.4V to 5.5V supply voltage.

Advanced CMOS technology and circuit techniques provide both

high speed and low power features with maximum CMOS standby

current of 4/20uA at Vcc=3/5V at 85^OC and maximum access time of

55/70ns.

V_CC= 3.0V

Operation current : 27mA (Max.) at 55ns

2mA (Max.) at 1MHz

Standby current : 2/4uA (Max.) at 70/85^OC

Operation current : 65mA (Max.) at 55ns

10mA (Max.) at 1MHz

V_CC= 5.0V

Standby current : 10/20uA (Max.) at 70/85^OC

y High speed access time :

Easy memory expansion is provided by an active LOW chip enable

(CE) and active LOW output enable (OE) and three-state output

drivers.

The BS616LV4017 has an automatic power down feature, reducing

the power consumption significantly when chip is deselected.

The BS616LV4017 is available in DICE form, JEDEC standard

44-pin TSOP II and 48-ball BGA package.

-55

-70

55ns(Max.) at V_CC=3.0~5.5V

70ns(Max.) at V_CC=2.7~5.5V

y Automatic power down when chip is deselected

y Easy expansion with CE and OE options

y I/O Configuration x8/x16 selectable by LB and UB pin.

y Three state outputs and TTL compatible

y Fully static operation

y Data retention supply voltage as low as 1.5V

POWER CONSUMPTION

POWER DISSIPATION

Operating

STANDBY

PRODUCT

FAMILY

OPERATING

PKG TYPE

(I_CCSB1, Max)

(I_CC, Max)

TEMPERATURE

V_CC=5.0V

10MHz

V_CC=3.0V

10MHz

V_CC=5.0V V_CC=3.0V

1MHz

9mA

f_Max.

1MHz

f_Max.

BS616LV4017DC

BS616LV4017AC

BS616LV4017EC

BS616LV4017AI

BS616LV4017EI

DICE

Commercial

10uA

20uA

2.0uA

4.0uA

39mA

40mA

63mA

1.5mA

14mA

15mA

26mA

BGA-48-0608

TSOP II-44

BGA-48-0608

TSOP II-44

+0^OC to +70^OC

Industrial

10mA

65mA

2mA

27mA

-40^OC to +85^OC

PIN CONFIGURATIONS

BLOCK DIAGRAM

A12

A11

A10

DQ0

DQ1

DQ2

DQ3

VCC

VSS

DQ4

DQ5

DQ6

DQ7

A17

A16

A15

A14

A13

DQ15

DQ14

DQ13

DQ12

VSS

VCC

DQ11

DQ10

DQ9

DQ8

Address

Input

1024

Memory Array

Row

Decoder

BS616LV4017EC

BS616LV4017EI

Buffer

1024 x 4096

4096

DQ0

Data

Column I/O

A10

A11

A12

Input

Buffer

Write Driver

Sense Amp

Data

Output

Buffer

256

Column Decoder

DQ15

D10

D11

D12

D13

Address Input Buffer

Control

VSS

VCC

D14

D15

A17

A14

A12

VCC

VSS

A13 A14 A15 A16 A17 A0 A1 A2

A16

A15

A13

A10

V_CC

V_SS

A11

48-ball BGA top view

Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.

R0201-BS616LV4017

Revision

Oct.

1.4

2008

BS616LV4017

PIN DESCRIPTIONS

Name

Function

These 18 address inputs select one of the 262,144 x 16-bit in the RAM

A0-A17 Address Input

CE is active LOW. Chip enable must be active when data read form or write to the

device. If chip enable is not active, the device is deselected and is in standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

CE Chip Enable Input

WE Write Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impendence state when OE is inactive.

Lower byte and upper byte data input/output control pins.

OE Output Enable Input

LB and UB Data Byte Control Input

There 16 bi-directional ports are used to read data from or write data into the RAM.

DQ0-DQ15 Data Input/Output

Ports

V_CC

Power Supply

Ground

V_SS

TRUTH TABLE

MODE

IO0~IO7

High Z

D_OUT

IO8~IO15

High Z

D_OUT

V_CCCURRENT

I_CCSB, I_CCSB1

Chip De-selected

(Power Down)

I_CCSB, I_CCSB1

I_CC

Output Disabled

Read

High Z

D_OUT

High Z

D_IN

Write

D_IN

NOTES: H means V_IH; L means V_IL; X means don’t care (Must be V_IHor V_ILstate)

Revision

Oct.

1.4

2008

R0201-BS616LV4017

BS616LV4017

ABSOLUTE MAXIMUM RATINGS ⁽¹⁾

OPERATING RANGE

AMBIENT

SYMBOL

V_TERM

T_BIAS

PARAMETER

RATING

-0.5⁽²⁾to 7.0

-40 to +125

-60 to +150

1.0

UNITS

RANG

V_CC

TEMPERATURE

Terminal Voltage with

Commercial

Industrial

0^OC to + 70^OC

2.4V ~ 5.5V

Respect to GND

Temperature Under

Bias

^OC

-40^OC to + 85^OC

T_STG

Storage Temperature

Power Dissipation

DC Output Current

^OC

P_T

CAPACITANCE ⁽¹⁾(T_A= 25^OC, f = 1.0MHz)

I_OUT

SYMBOL PAMAMETER CONDITIONS MAX. UNITS

Input

1. Stresses greater than those listed under ABSOLUTE

MAXIMUM RATINGS may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at these or any other conditions above those

indicated in the operational sections of this specification is not

implied. Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

C_IN

C_IO

V_IN= 0V

V_I/O= 0V

Capacitance

Input/Output

Capacitance

1. This parameter is guaranteed and not 100% tested.

2. –2.0V in case of AC pulse width less than 30 ns.

DC ELECTRICAL CHARACTERISTICS (T_A= -40^OC to +85^OC)

PARAMETER

TEST CONDITIONS

MIN.

2.4

-0.5⁽²⁾

2.2

TYP.⁽¹⁾

MAX.

UNITS

NAME

Power Supply

5.5

V_CC

Input Low Voltage

0.8

V_IL

V_IH

I_IL

Input High Voltage

V_CC+0.3⁽³⁾

V_IN= 0V to V_CC

Input Leakage Current

Output Leakage Current

Output Low Voltage

Output High Voltage

CE= V_IH

V_I/O= 0V to V_CC

I_LO

CE= V_IHor OE = V_IH

V_CC= Max, I_OL= 2.0mA

0.4

V_OL

V_OH

V_CC= Min, I_OH= -1.0mA

CE = V_IL,

2.4

V_CC=3.0V

_CC=5.0V

Operating Power Supply

Current

(5)

I_CC

(4)

I_IO= 0mA, f = F_MAX

V_CC=3.0V

V_CC=5.0V

V_CC=3.0V

V_CC=5.0V

V_CC=3.0V

V_CC=5.0V

CE = V_IL,

Operating Power Supply

Current

I_CC1

1.0

2.0

4.0

_IO= 0mA, f = 1MHz

CE = V_IH,

I_IO= 0mA

Standby Current – TTL

I_CCSB

0.25

1.5

CE≧V_CC-0.2V

(6)

Standby Current – CMOS

I_CCSB1

_IN≧V_CC-0.2V or V_IN≦0.2V

1. Typical characteristics are at T_A=25^OC and not 100% tested.

2. Undershoot: -1.0V in case of pulse width less than 20 ns.

3. Overshoot: V_CC+1.0V in case of pulse width less than 20 ns.

4. F_MAX=1/t_RC.

5. I_{CC (MAX.)}is 26mA/63mA at V_CC=3.0V/5.0V and T_A=70^OC.

6. I_CCSB1(MAX.)is 2.0uA/10uA at V_CC=3.0V/5.0V and T_A=70^OC.

Revision

Oct.

1.4

2008

R0201-BS616LV4017

BS616LV4017

DATA RETENTION CHARACTERISTICS (T_A= -40^OC to +85^OC)

SYMBOL

V_DR

PARAMETER

V_CCfor Data Retention

Data Retention Current

TEST CONDITIONS

MIN.

1.5

TYP. ⁽¹⁾

MAX.

UNITS

CE≧V_CC-0.2V

0.1

1.5

V^IN≧V_CC-0.2V or VIN≦0.2V

CE≧V_CC-0.2V

(3)

I_CCDR

V^IN≧V_CC-0.2V or VIN≦0.2V

Chip Deselect to Data

Retention Time

t_CDR

t_R

See Retention Waveform

(2)

Operation Recovery Time

t_RC

1. V_CC=1.5V, T_A=25^OC and not 100% tested.

2. t_RC= Read Cycle Time.

3. I_CCDR(Max.)is 1.0uA at T_A=70^OC.

LOW V_CCDATA RETENTION WAVEFORM (CE Controlled)

Data Retention Mode

_DR≧1.5V

V_CC

t_CDR

V_CC

t_R

V_CC

CE≧V_CC- 0.2V

V_IH

AC TEST CONDITIONS

KEY TO SWITCHING WAVEFORMS

(Test Load and Input/Output Reference)

WAVEFORM

INPUTS

OUTPUTS

Input Pulse Levels

Vcc / 0V

1V/ns

MUST BE

STEADY

MUST BE

STEADY

Input Rise and Fall Times

Input and Output Timing

Reference Level

0.5Vcc

MAY CHANGE

WILL BE CHANGE

FROM “H” TO “L”

t_CLZ, t_OLZ, t_CHZ, t_OHZ, t_WHZ

C_L= 5pF+1TTL

C_L= 30pF+1TTL

Output Load

Others

MAY CHANGE

WILL BE CHANGE

FROM “L” TO “H”

ALL INPUT PULSES

DON’T CARE

ANY CHANGE

PERMITTED

CHANGE :

V_CC

1 TTL

STATE UNKNOW

90%

Output

10%

CENTER LINE IS

HIGH INPEDANCE

“OFF” STATE

GND

DOES NOT

APPLY

(1)

→

←

→

←

C_L

Rise Time:

Fall Time:

1V/ns

1. Including jig and scope capacitance.

Revision

Oct.

1.4

2008

R0201-BS616LV4017

BS616LV4017

AC ELECTRICAL CHARACTERISTICS (T_A= -40^OC to +85^OC)

READ CYCLE

CYCLE TIME : 55ns CYCLE TIME : 70ns

(V_CC=3.0~5.5V) (V_CC=2.7~5.5V)

MIN. TYP. MAX. MIN. TYP. MAX.

JEDEC

PARANETER

PARAMETER

NAME

DESCRIPTION

Read Cycle Time

UNITS

NAME

t_AVAX

t_AVQX

t_ELQV

t_BLQV

t_GLQV

t_ELQX

t_BLQX

t_GLQX

t_EHQZ

t_BHQZ

t_GHQZ

t_AVQX

t_RC

t_AA

Address Access Time

Chip Select Access Time

(CE)

t_ACS

t_BA

Data Byte Control Access Time

(LB, UB)

t_OE

Output Enable to Output Valid

Chip Select to Output Low Z

(CE)

t_CLZ

t_BE

Data Byte Control to Output Low Z (LB, UB)

t_OLZ

t_CHZ

t_BDO

t_OHZ

t_OH

Output Enable to Output Low Z

Chip Select to Output High Z

(CE)

Data Byte Control to Output High Z (LB, UB)

Output Enable to Output High Z

Data Hold from Address Change

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE 1 ^(1,2,4)

t_RC

ADDRESS

t_AA

t_OH

D_OUT

Revision

Oct.

1.4

R0201-BS616LV4017

2008

BS616LV4017

READ CYCLE 2 ^(1,3,4)

t_ACS

t_BA

t_BE

LB, UB

D_OUT

(5)

t_CHZ

t_BDO

(5)

t_CLZ

READ CYCLE 3 ^{(1, 4)}

ADDRESS

t_RC

t_AA

t_OH

t_OE

t_OLZ

(5)

t_OHZ

(5)

(1,5)

t_CLZ

t_CHZ

t_BA

t_BE

LB, UB

D_OUT

t_BDO

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = V_IL.

3. Address valid prior to or coincident with CE transition low.

4. OE = V_IL.

5. Transition is measured ± 500mV from steady state with C_L= 5pF.

The parameter is guaranteed but not 100% tested.

Revision

Oct.

1.4

R0201-BS616LV4017

2008

BS616LV4017

AC ELECTRICAL CHARACTERISTICS (T_A= -40^OC to +85^OC)

WRITE CYCLE

CYCLE TIME : 55ns CYCLE TIME : 70ns

(V_CC=3.0~5.5V) (V_CC=2.7~5.5V)

MIN. TYP. MAX. MIN. TYP. MAX.

JEDEC

PARANETER

PARAMETER

NAME

DESCRIPTION

Write Cycle Time

UNITS

NAME

t_AVAX

t_AVWL

t_AVWH

t_ELWH

t_BLWH

t_WLWH

t_WHAX

t_WLQZ

t_DVWH

t_WHDX

t_GHQZ

t_WHQX

t_WC

t_AS

Address Set up Time

t_AW

t_CW

t_BW

t_WP

t_WR

t_WHZ

t_DW

t_DH

Address Valid to End of Write

Chip Select to End of Write

(CE)

Data Byte Control to End of Write

(LB, UB)

Write Pulse Width

Write Recovery Time

(CE, WE)

Write to Output High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

t_OHZ

t_OW

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE 1 ⁽¹⁾

t_WC

ADDRESS

(3)

t_WR1

(11)

t_CW

(5)

t_BW

LB, UB

(3)

t_WR2

t_AW

(2)

t_WP

t_AS

(4,10)

t_OHZ

D_OUT

t_DH

t_DW

D_IN

Revision

Oct.

1.4

R0201-BS616LV4017

2008

BS616LV4017

WRITE CYCLE 2 ^(1,6)

ADDRESS

t_WC

(11)

t_CW

(5)

t_BW

(12)

LB, UB

(3)

t_AW

t_WR2

(2)

t_WP

t_AS

(4,10)

t_WHZ

(7)

(8)

t_OW

D_OUT

t_DW

t_DH

(8,9)

D_IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All

signals must be active to initiate a write and any one signal can terminate a write by going

inactive. The data input setup and hold timing should be referenced to the second transition

edge of the signal that terminates the write.

3. t_WRis measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite

phase to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V_IL).

7. D_OUTis the same phase of write data of this write cycle.

8. D_OUTis the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals

of opposite phase to the outputs must not be applied to them.

10.Transition is measured ± 500mV from steady state with C_L= 5pF.

The parameter is guaranteed but not 100% tested.

11.t_CWis measured from the later of CE going low to the end of write.

12.The change of Read/Write cycle must accompany with CE or address toggled.

Revision

Oct.

1.4

2008

R0201-BS616LV4017

BS616LV4017

ORDERING INFORMATION

BS616LV4017

Z Y Y

SPEED

55: 55ns

70: 70ns

PKG MATERIAL

G: Green, RoHS Compliant

P: Pb free, RoHS Compliant

GRADE

C: +0^oC ~ +70^oC

I: -40^oC ~ +85^oC

PACKAGE

D: DICE

A: BGA-48-0608

E: TSOP II-44

Note:

BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does

not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result

in significant injury or death, including life-support systems and critical medical instruments.

PACKAGE DIMENSIONS

TSOP II-44

Revision

Oct.

1.4

R0201-BS616LV4017

2008

BS616LV4017

PACKAGE DIMENSIONS (continued)

NOTES

1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.

3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.

BALL PITCH e = 0.75

8.0

6.0

5.25

3.75

VIEW A

48 mini-BGA (6 x 8mm)

Revision

Oct.

1.4

R0201-BS616LV4017

2008

BS616LV4017

Revision History

Revision No.

1.2

History

Draft Date

Remark

Add Icc1 characteristic parameter

Improve Iccsb1 spec.

Jan. 13, 2006

I-grade from 60uA to 20uA at 5.0V

10uA to 4.0uA at 3.0V

C-grade from 30uA to 10uA at 5.0V

5.0uA to 2.0uA at 3.0V

1.3

1.4

Change I-grade operation temperature range

May. 25, 2006

Oct. 31, 2008

- from –25 C to –40 C

Typical value of standby current is replaced by

maximum value in Featues and Description

section

Remove “-: Normal” (Leaded) PKG Material in

ordering information

Revision

1.4

2008

R0201-BS616LV4017

Oct.

BS616LV4017ECG55 [BSI]

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