BS616UV1010ACI-10 [BSI]
SRAM;
| 型号： | BS616UV1010ACI-10 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | SRAM 静态存储器 |
| 文件： | 总9页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
64K X 16 bit
BSI
BS616UV1010
n FEATURES
n DESCRIPTION
ŸUltra low VCC operation voltage : 1.9V ~ 3.6V
The BS616UV1010 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 65,536 words by 16 bits and
operates form a wide range of 1.9V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical CMOS standby current of
0.01uA and maximum access time of 100ns in 1.9V operation.
Easy memory expansion is provided by an active LOW chip enable (CE)
and active LOW output enable (OE) and three-state output drivers.
The BS616UV1010 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
ŸVery low power consumption :
VCC = 2.0V
10mA(Max.) operating current
0.01uA (Typ.) CMOS standby current
18mA(Max.) operating current
VCC = 3.0V
0.02uA (Typ.) CMOS standby current
ŸHigh speed access time :
-10
100ns(Max.)
ŸAutomatic power down when chip is deselected
ŸEasy expansion with CE and OE options
ŸI/O Configuration x8/x16 selectable by LB and UB pin.
ŸThree state outputs and TTL compatible
ŸFully static operation
The BS616UV1010 is available in JEDEC standard 44-pin TSOP II and
48-ball BGA package.
ŸData retention supply voltage as low as 1.5V
n PRODUCT FAMILY
POWER DISSIPATION
PRODUCT
FAMILY
OPERATING
TEMPERATURE
VCC
RANGE
SPEED
(ns)
STANDBY
(ICCSB1, Max)
Operating
(ICC, Max)
PKG TYPE
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
BS616UV1010EC
BS616UV1010AC
BS616UV1010EI
BS616UV1010AI
TSOP2-44
+0OC to +70OC
-40OC to +85OC
1.9V ~ 3.6V
1.9V ~ 3.6V
100
100
1.0uA
1.5uA
0.5uA
20mA
20mA
15mA
BGA-48-0608
TSOP2-44
1.0uA
15mA
BGA-48-0608
n PIN CONFIGURATIONS
n BLOCK DIAGRAM
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
CE
A8
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A15
A14
A13
A12
NC
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ11
DQ10
DQ9
DQ8
NC
A8
A9
A10
A11
NC
A13
9
A15
10
11
12
13
14
15
16
17
18
19
20
21
22
Address
512
Memory Array
18
A14
A12
A7
BS616UV1010EC
BS616UV1010EI
Input
Row
Decoder
Buffer
512 x 2048
A6
A5
A4
2048
DQ0
Data
Input
Buffer
16
16
16
Column I/O
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
.
1
2
3
4
5
6
16
.
Data
Output
Buffer
.
.
128
A
B
C
D
E
F
UB
D8
OE
A0
A1
A2
NC
D0
Column Decoder
DQ15
LB
D10
D11
D12
D13
NC
A3
A5
A4
A6
CE
D1
14
CE
WE
OE
UB
LB
D9
D2
Address Input Buffer
Control
VSS
VCC
D14
D15
NC
NC
NC
A14
A12
A9
A7
D3
VCC
VSS
D6
NC
A15
A13
A10
D4
A11 A9 A3 A2 A1 A0 A10
VCC
VSS
D5
G
H
WE
A11
D7
A8
NC
48-ball BGA top view
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.
R0201-BS616UV1010
Revision 2.4
May. 2005
1
BSI
BS616UV1010
n PIN DESCRIPTIONS
Name
Function
These 16 address inputs select one of the 65,536 x 16-bit words in the RAM
A0-A15 Address Input
CE Chip Enable 1 Input
CE is active LOW. Chip enable must be active when data read form or write to the device.
If either chip enable is not active, the device is deselected and is in standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ
pins; when WE is LOW, the data present on the DQ pins will be written into the selected
memory location.
WE Write Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they will
be enabled. The DQ pins will be in the high impendence state when OE is inactive.
Lower byte and upper byte data input/output control pins.
OE Output Enable Input
LB and UB Data Byte Control Input
There 16 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ15 Data Input/Output
Ports
VCC
Power Supply
Ground
VSS
n TRUTH TABLE
MODE
Not selected
(Power Down)
DQ0~DQ7
High Z
High Z
DOUT
DQ8~DQ15
High Z
High Z
DOUT
VCC CURRENT
CE
WE
OE
LB
UB
H
X
X
X
X
ICCSB, ICCSB1
Output Disabled
Read
L
L
H
H
H
L
X
L
X
L
ICC
ICC
ICC
ICC
ICC
ICC
ICC
H
L
L
High Z
DOUT
DOUT
H
L
High Z
DIN
L
DIN
Write
L
L
X
H
L
L
X
DIN
H
DIN
X
NOTES: H means VIH; L means VIL; X means don’t care (Must be VIH or VIL state)
Revision 2.4
R0201-BS616UV1010
2
May.
2005
BSI
BS616UV1010
n ABSOLUTE MAXIMUM RATINGS (1)
n OPERATING RANGE
AMBIENT
TEMPERATURE
SYMBOL
PARAMETER
RATING
-0.5 to 7.0
-40 to +125
UNITS
RANG
Vcc
Terminal Voltage with
Respect to GND
Temperature Under
Bias
0OC to + 70OC
1.9V ~ 3.6V
1.9V ~ 3.6V
VTERM
V
Commercial
Industrial
TBIAS
OC
-40OC to + 85OC
TSTG
PT
Storage Temperature
Power Dissipation
DC Output Current
-60 to +150
OC
W
1.0
20
n CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
IOUT
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Capacitance
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
n DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
PARAMETER
Power Supply
TEST CONDITIONS
MIN.
1.9
TYP.(1)
MAX.
UNITS
V
NAME
VCC
--
--
--
--
--
--
--
--
--
3.6
0.6
0.8
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VIL
VIH
Input Low Voltage
-0.5(2)
V
1.4
2.0
Input High Voltage
VCC+0.2(3)
V
IIL
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
VIN = 0V to VCC
VI/O = 0V to VCC
--
--
--
1
1
uA
uA
V
,
ILO
CE= VIH or OE = VIH
VCC = Max, IOL = 1.0mA
VCC = Max, IOL = 2.0mA
VCC = Min, IOH = -0.5mA
VCC = Min, IOH = -1.0mA
0.2
0.4
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VCC=2.0V
VCC=3.0V
VOL
VOH
ICC
VCC-0.2
2.4
--
V
Operating Power Supply CE = VIL,
15
20
--
--
--
mA
mA
uA
(4)
Current
IIO = 0mA, f = FMAX
CE = VIH,
0.5
1.0
1.0
1.5
ICCSB
Standby Current – TTL
IIO = 0mA
CE≧VCC-0.2V
0.01
0.02
(5)
ICCSB1
Standby Current – CMOS
VIN≧VCC-0.2V or VIN≦0.2V
4. FMAX=1/tRC.
5. ICCSB1(MAX.) is 0.5uA/1.0uA at VCC=2.0V/3.0V and TA=70OC.
1. Typical characteristics are at TA=25OC.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
n DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
PARAMETER
TEST CONDITIONS
CE≧VCC-0.2V
MIN.
TYP. (1)
MAX.
UNITS
VDR
VCC for Data Retention
1.5
--
--
V
VIN≧VCC-0.2V or VIN≦0.2V
CE≧VCC-0.2V
(3)
ICCDR
Data Retention Current
--
0
0.01
0.3
uA
VIN≧VCC-0.2V or VIN≦0.2V
Chip Deselect to Data
Retention Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
Operation Recovery Time
tRC
1. VCC=1.5V, TA=25OC.
2. tRC = Read Cycle Time.
3. ICCRD_Max. is 0.2uA at TA=70OC.
Revision 2.4
May. 2005
R0201-BS616UV1010
3
BSI
BS616UV1010
n LOW VCC DATA RETENTION WAVEFORM (1) (CE Controlled)
Data Retention Mode
DR≧1.5V
V
VCC
VCC
VCC
CE
tCDR
tR
CE≧VCC - 0.2V
VIH
VIH
n AC TEST CONDITIONS
n KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
1V/ns
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
CHANGE :
STATE UNKNOW
VCC
1 TTL
90%
90%
Output
10%
10%
GND
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
(1)
®
¬
®
¬
DOES NOT
APPLY
CL
Rise Time:
1V/ns
Fall Time:
1V/ns
1. Including jig and scope capacitance.
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
JEDEC
PARANETER
CYCLE TIME : 100ns
PARAMETER
NAME
DESCRIPTION
UNITS
NAME
MIN.
TYP.
MAX.
tAVAX
tAVQX
tELQV
tBLQV
tGLQV
tELQX
tBLQX
tGLQX
tEHQZ
tBHQZ
tGHQZ
tAVQX
tRC
tAA
tACS
tBA
Read Cycle Time
100
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
100
100
100
50
--
Chip Select Access Time
(CE)
--
Data Byte Control Access Time
(LB, UB)
--
tOE
Output Enable to Output Valid
Chip Select to Output Low Z
--
(CE)
tCLZ
tBE
15
15
15
--
Data Byte Control to Output Low Z
(LB, UB)
--
tOLZ
tCHZ
tBDO
tOHZ
tOH
Output Enable to Output Low Z
Chip Select to Output High Z
--
(CE)
40
40
35
--
Data Byte Control to Output High Z
(LB, UB)
--
Output Enable to Output High Z
Data Hold from Address Change
--
15
Revision 2.4
R0201-BS616UV1010
4
May.
2005
BSI
BS616UV1010
n SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE
tACS
tBA
tBE
LB, UB
DOUT
(5)
tCHZ
tBDO
(5)
tCLZ
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
CE
tOH
tOE
tOLZ
(5)
tOHZ
tCHZ
(5)
(1,5)
tCLZ
tBA
LB, UB
DOUT
tBE
tBDO
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
Revision 2.4
May. 2005
R0201-BS616UV1010
5
BSI
BS616UV1010
n AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
JEDEC
PARAMETER
NAME
PARANETER
CYCLE TIME : 100ns
DESCRIPTION
Write Cycle Time
UNITS
NAME
MIN.
100
0
TYP.
MAX.
tAVAX
tAVWL
tAVWH
tELWH
tBLWH
tWLWH
tWHAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tAS
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Set up Time
--
--
tAW
tCW
tBW
tWP
tWR
tWHZ
tDW
tDH
Address Valid to End of Write
100
100
100
50
0
--
--
Chip Select to End of Write
--
--
Data Byte Control to End of Write
(LB, UB)
--
--
Write Pulse Width
--
--
Write Recovery Time
(CE, WE)
--
--
Write to Output High Z
--
--
40
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
40
0
--
--
--
tOHZ
tOW
--
--
40
--
10
--
n SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR1
(11)
tCW
(5)
CE
tBW
LB, UB
(3)
tWR2
tAW
(2)
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
Revision 2.4
R0201-BS616UV1010
6
May.
2005
BSI
BS616UV1010
WRITE CYCLE 2 (1,6)
tWC
ADDRESS
CE
(11)
tCW
(5)
tBW
(12)
LB, UB
WE
(3)
tAW
tWR2
(2)
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals must be
active to initiate a write and any one signal can terminate a write by going inactive. The data input
setup and hold timing should be referenced to the second transition edge of the signal that terminates
the write.
3. tWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE transition,
output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite
phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.t CW is measured from the later of CE going low to the end of write.
12.The change of Read/Write cycle must accompany with CE or address toggled.
Revision 2.4
R0201-BS616UV1010
7
May.
2005
BSI
BS616UV1010
n ORDERING INFORMATION
BS616UV1010 X
X
Z Y Y
SPEED
10: 100ns
PKG MATERIAL
-: Normal
G: Green
P: Pb free
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
E: TSOP 2-44
F: BGA-48-0912
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not
authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in
significant injury or death, including life-support systems and critical medical instruments.
n PACKAGE DIMENSIONS
TSOP2-44
Revision 2.4
May. 2005
R0201-BS616UV1010
8
BSI
BS616UV1010
n PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
BALL PITCH e = 0.75
D
E
N
D1
E1
8.0
6.0
48
5.25
3.75
D1
VIEW A
48 mini-BGA (6 x 8)
Revision 2.4
May. 2005
R0201-BS616UV1010
9
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