BS616UV1610FC [BSI]
Ultra Low Power/Voltage CMOS SRAM 1M X 16 bit; 超低功率/电压CMOS SRAM 1M ×16位
| 型号： | BS616UV1610FC |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/Voltage CMOS SRAM 1M X 16 bit |
| 文件： | 总10页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
1M X 16 bit
BSI
BS616UV1610
FEATURES
DESCRIPTION
• Ultra low operation voltage : 1.8 ~ 2.3V
• Ultra low power consumption :
The BS616UV1610 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 words by 16 bits and
operates from a wide range of 1.8V to 2.3V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.2uA and maximum access time of 70/100ns in 2V operation.
Easy memory expansion is provided by an active LOW chip enable(CE1),
active HIGH chip enable (CE2), active LOW output enable(OE) and
three-state output drivers.
Vcc = 2.0V C-grade: 25mA (Max.) operating current
I-grade : 30mA (Max.) operating current
1.2uA (Typ.) CMOS standby current
• High speed access time :
-70
-10
70ns (Max.) at Vcc=2V
100ns (Max.) at Vcc=2V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616UV1610 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2,CE1 and OE options
• I/O Configuration x8/x16 selectable by LB and UB pin
The BS616UV1610 is available in 48-pin BGA package.
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
OPERATING
Vcc
RANGE
PRODUCT FAMILY
(I
, Max)
CCSB1
(I
, Max)
CC
PKG TYPE
TEMPERATURE
Vcc=2V
Vcc=2V
Vcc=2V
25mA
BS616UV1610BC
BS616UV1610FC
BS616UV1610BI
BS616UV1610FI
BGA
0810
-
48
-
-
-
-
+0O C to +70O
C
30uA
40uA
1.8 ~ 2.3V 70 / 100
1.8 ~ 2.3V 70 / 100
BGA
BGA
BGA
0912
0810
0912
- 48
48
48
-
-
40O C to +85OC
-
30mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
A4
A3
A2
1
2
3
4
5
6
A1
A0
A17
A16
A15
A14
A13
A12
Address
Input
LB
OE
A0
A1
A2
CE2
A
B
C
D
E
F
22
2048
Row
Memory Array
2048 x 8192
Buffer
D8
D9
A3
A5
A4
A6
D0
D2
UB
D10
D11
D12
CE1
D1
D3
D4
D5
Decoder
8192
Data
16
16
Column I/O
Input
D0
A17
A7
Buffer
VSS
VCC
VSS
D6
.
.
.
.
.
.
.
.
Write Driver
Sense Amp
16
512
A16
A15
A13
A10
Data
VSS
A14
A12
A9
VCC
D14
16
Output
Buffer
Column Decoder
D15
D13
CE2
CE1
WE
OE
UB
LB
18
D15 NC.
A8
D7
G
H
WE
Control
Address Input Buffer
A8
A9
A11
A10
A7 A6
A18
A5 A19
A18
A11
A1.9
Vcc
Gnd
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.2
April 2001
R0201-BS616UV1610
1
BSI
PIN DESCRIPTIONS
Name
BS616UV1610
Function
A0-A19 Address Input
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
Lower byte and upper byte data input/output control pins.
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
CE1
H
X
CE2
X
L
WE
X
X
OE
X
X
LB
X
X
X
L
H
L
L
UB
X
X
X
L
L
H
L
D0~D7
High Z
High Z
High Z
Dout
High Z
Dout
Din
D8~D15
High Z
High Z
High Z
Dout
Dout
High Z
Din
Vcc CURRENT
ICCSB , ICCSB1
Not selected
(Power Down)
I
CCSB , ICCSB1
L
Output Disabled
Read
H
H
H
ICC
ICC
ICC
ICC
ICC
ICC
ICC
L
L
H
H
H
L
L
Write
X
H
L
L
H
X
Din
Din
X
OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS(1)
AMBIENT
SYMBOL
PARAMETER
RATING
UNITS
RANGE
Vcc
TEMPERATURE
Terminal Voltage with
Respect to GND
-0.5 to
V
TERM
V
0O C to +70O C
-40O C to +85O C
1.8V ~ 2.3V
1.8V ~ 2.3V
Vcc+0.5
Commercial
Industrial
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
BIAS
STG
T
T
P
T
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
IN
PARAMETER CONDITIONS MAX.
UNIT
pF
Input
IN
C
V
=0V
10
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Capacitance
Input/Output
Capacitance
DQ
C
I/O
=0V
V
12
pF
1. This parameter is guaranteed and not tested.
Revision 2.2
April 2001
R0201-BS616UV1610
2
BSI
BS616UV1610
DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )
PARAMETER
(1)
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
NAME
Guaranteed Input Low
Vcc=2V
Vcc=2V
IL
V
-0.5
--
0.6
V
(2)
Voltage
Guaranteed Input High
Vcc+0.2
IH
V
1.4
--
--
--
V
(2)
Voltage
IN
IL
I
Input Leakage Current
Vcc = Max, V = 0V to Vcc
1
1
uA
IH
iL
Vcc = Max, CE1 = V , or CE2 = V , or
OL
I
Output Leakage Current
--
--
uA
IH
I/O
OE = V , V = 0V to Vcc
Vcc=2V
Vcc=2V
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc = Max, I = 1mA
--
--
--
0.4
--
V
V
OH
OH
V
Vcc = Min, I = -0.5mA
1.6
IL
Operating Power Supply Vcc= max, CE1 = V and CE2 =
Vcc=2V
Vcc=2V
CC
I
--
--
--
--
25
mA
mA
(3)
IH
DQ
Current
V , I = 0mA, F = Fmax
IH
Vcc= max, CE1 = V or CE2 =
CCSB
I
Standby Current-TTL
0.8
IL
DQ
V , I = 0mA
Vcc= max,CE1
Vcc-0.2V, or
Vcc - 0.2V
Њ
IN
Vcc=2V
CCSB1
CE2
0.2V, V
0.2V
I
Standby Current-CMOS
--
1.2
30
uA
Љ
Њ
IN
or V
Љ
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
DATA RETE.NTION CHARACTERISTICS ( TA = 0 to + 70oC )
(1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
UNITS
CE1
Vcc - 0.2V or CE2 0.2V
Њ
Љ
VDR
Vcc for Data Retention
1.5
--
--
V
IN
IN
Љ
V
Vcc - 0.2V or V
0.2V
Њ
CE1
Vcc - 0.2V or CE2 0.2V
Њ
Љ
ICCDR
Data Retention Current
--
0
0.8
15
uA
IN
IN
V
Vcc - 0.2V or V
0.2V
Њ
Љ
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
V
DR ≥ 1.5V
Vcc
Vcc
t
Vcc
CE1
R
t
CDR
≥
CE1 Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
VDR Њ 1.5V
Vcc
Vcc
t
Vcc
R
t
CDR
CE2 Љ 0.2V
VIL
VIL
CE2
Revision 2.2
April 2001
R0201-BS616UV1610
3
BSI
BS616UV1610
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1333
1333
5PF
MAY CHANGE
FROM L TO H
WILL BE
2V
OUTPUT
2V
OUTPUT
CHANGE
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
100PF
ANY CHANGE
PERMITTED
INCLUDING
INCLUDING
Ω
Ω
2000
2000
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
800
Ω
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=2V)
READ CYCLE
JEDEC
PARAMETER
NAME
BS616UV1610-70
MIN. TYP. MAX.
BS616UV1610-100
MIN. TYP. MAX.
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNIT
tAVAX
tRC
tAA
tACS1
tACS2
tBA
tOE
tCLZ
tBE
tOLZ
tCHZ
tBDO
tOHZ
70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
100
60
60
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAVQV
tELQV
tELQV
tBA
tGLQV
tELQX
tBE
tGLQX
tEHQZ
tBDO
tGHQZ
Address Access Time
70
70
70
50
50
--
Chip Select Access Time
Chip Select Access Time
Data Byte Control Access Time
Output Enable to Output Valid
(CE1)
(CE2)
(LB,UB)
--
--
--
--
--
--
--
--
Chip Select to Output Low Z
(CE2,CE1)
(LB,UB)
10
10
10
0
0
0
15
15
15
0
0
0
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
--
--
35
30
30
--
--
40
35
35
(CE2,CE1)
(LB,UB)
tAXOX
tOH
Output Disable to Address Change
10
--
--
15
--
--
ns
Revision 2.2
April 2001
R0201-BS616UV1610
4
BSI
BS616UV1610
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t
t
ACS2
ACS1
CE1
(5)
CHZ
(5)
CLZ
t
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
CE2
CE1
t
ACS2
t
OLZ
(5)
OHZ
t
ACS1
t
t
(5)
CLZ
(1,5)
t
CHZ
LB,UB
t
BE
t
BDO
t
BA
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.2
April 2001
R0201-BS616UV1610
5
BSI
BS616UV1610
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC, Vcc=2V)
WRITE CYCLE
JEDEC
PARAMETER
BS616UV1610-70
BS616UV1610-10
UNIT
PARAMETER
DESCRIPTION
MIN. TYP. MAX. MIN. TYP. MAX.
NAME
NAME
tWC
tCW
tAS
tAW
tWP
tWR1
tBW
tWHZ
tDW
tDH
Write Cycle Time
tAVAX
tE1LWH
tA
70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
100
100
0
100
70
0
80
0
40
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
40
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Setup Time
70
0
tAVVWWLH
tWLWH
tWHAX
tBW
Address Valid to End of Write
Write Pulse Width
70
50
Write recovery Time
(CE2,CE1,WE)
0
--
--
Date Byte Control to End of Write
Write to Output in High Z
(LB,UB) 60
tWLQZ
tDVWH
tWHDX
tGHQZ
0
30
0
30
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
--
tOHZ
0
30
0
40
tOW
tWHOX
End of Write to Output Active
5
--
--
10
--
--
ns
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
t
WR
(5)
CE2
(11)
CW
t
(5)
CE1
t
BW
(5)
LB,UB
t
AW
(3)
t
WP
(2)
t
AS
WE
(4,10)
t
OHZ
D OUT
t
DH
t
DW
D IN
Revision 2.2
April 2001
R0201-BS616UV1610
6
BSI
BS616UV1610
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
CE2
(11)
CW
t
(5)
(5)
CE1
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
WHZ
(7)
(8)
t
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
Revision 2.2
April 2001
R0201-BS616UV1610
7
BSI
BS616UV1610
ORDERING INFORMATION
BS616UV1610 X X -- Y Y
SPEED
70: 70ns
10: 100ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
B :BGA - 48 PIN(8x10mm)
F :BGA - 48 PIN(9x12mm)
PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
D1
N
48
D
10.0
E
8.0
D1
5.25
E1
3.75
e
0.75
SOLDER BALL
0.35̈́ 0.05
VIEW A
48 mini-BGA (8 x 10mm)
Revision 2.2
April 2001
R0201-BS616UV1610
8
BSI
BS616UV1610
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
N
D
E
D1
E1
e
D1
48
12.0
9.0
5.25
3.75
0.75
3.375
SOLDER BALL 0.35̈́0.05
VIEW A
48 mini-BGA (9 x 12mm)
Revision 2.2
April 2001
R0201-BS616UV1610
9
BSI
REVISION HISTORY
BS616UV1610
Revision Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
Revision 2.2
April 2001
R0201-BS616UV1610
10
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