BS616UV1620FI [BSI]
Ultra Low Power/Voltage CMOS SRAM 1M x 16 or 2M x 8 bit switchable; 超低功率/电压CMOS SRAM 1M ×16或2M ×8位切换
| 型号： | BS616UV1620FI |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/Voltage CMOS SRAM 1M x 16 or 2M x 8 bit switchable |
| 文件： | 总12页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
1M x 16 or 2M x 8 bit switchable
BSI
BS616UV1620
DESCRIPTION
FEATURES
The BS616UV1620 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,676 words by 16 bits or
2,097,152 bytes by 8 bits selectable by CIO pin and operates in a wide
range of 1.8V to 2.3V supply voltage.
• Ultra low operation voltage : 1.8 ~ 2.3V
• Ultra low power consumption :
Vcc = 1.8V C-grade : 25mA (Max.) operating current
I- grade : 30mA (Max.) operating current
1.2uA (Typ.) CMOS standby current
• High speed access time :
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current
of 1.2uA and maximum access time of 70/100ns in 2.0V operation.
This device provide three control inputs and three states output drivers
for easy memory expansion.
-70
70ns (Max.) at Vcc = 2.0V
-10 100ns (Max.) at Vcc = 2.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
The BS616UV1620 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS616UV1620 is available in DICE form and 48-pin BGA type.
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE1, CE2 and OE options
• I/O Configuration x8/x16 selectable by CIO, LB and UB pin
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
(ICCSB1, Max)
(ICC, Max)
Vcc RANGE
PKG TYPE
TEMPERATURE
Vcc=2.0V
70 / 100
70 / 100
Vcc=2.0V
30uA
Vcc=2.0V
25mA
BS616UV1620BC
BS616UV1620FC
BS616UV1620BI
BS616UV1620FI
BGA-48-0810
BGA-48-0912
BGA-48-0810
BGA-48-0912
+0 O C to +70O
-40 O C to +85O
C
C
1.8V ~ 2.3V
1.8V ~ 2.3V
40uA
30mA
BLOCK DIAGRAM
PIN CONFIGURATIONS
A19
A15
A14
A13
1
2
3
4
5
6
A12
A11
A10
A9
Address
Input
A0
A1
A2
24
A
B
C
D
E
F
CE2
4096
LB
OE
Row
Memory Array
4096 x 4096
Buffer
A8
Decoder
D8
D9
UB
A3
A5
A4
A6
CE1
D1
D0
D2
A17
A7
A6
D10
4096
Data
16(8)
16(8)
Column I/O
Input
D0
Buffer
.
.
.
.
VSS
D11
A17
A19
A14
A12
A9
A7
D3
D4
VCC
VSS
.
.
.
.
Write Driver
Sense Amp
16(8)
16(8)
256(512)
Data
VCC D12
A16
Output
Buffer
Column Decoder
D15
D5
D6
D7
D14
D15
A18
D13
CI.O
A8
A15
A13
A10
CE1
CE2
WE
OE
UB
16(18)
Control
Address Input Buffer
G
H
WE
LB
CIO
A16 A0 A1 A2 A3
A5
A18(SAE)
A4
A11 SAE.
Vdd
Vss
48-Ball CSP top View
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.2
April 2001
R0201-BS616UV1620
1
BSI
BS616UV1620
PIN DESCRIPTIONS
Name
Function
A0-A19 Address Input
These 20 address inputs select one of the 1,048,576 x 16-bit words in the RAM.
SAE Address Input
This address input incorporates with the above 20 address inputs select one of the
2,097,152 x 8-bit bytes in the RAM if the CIO is LOW. Don't use when CIO is HIGH.
CIO x8/x16 select input
This input selects the organization of the SRAM. 1,048,576
configuration is selected if CIO is HIGH. 2,097,152 x 8-bit bytes configuration is
selected if CIO is LOW.
x 16-bit words
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input
OE Output Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
Lower byte and upper byte data input/output control pins. The chip is deselected when
both LB and UB pins are HIGH.
LB and UB Data Byte Control Input
D0 - D15 Data Input/Output Ports
These 16 bi-directional ports are used to read data from or write data into the RAM.
Vcc
Power Supply
Ground
Gnd
Revision 2.2
April 2001
R0201-BS616UV1620
2
BSI
BS616UV1620
TRUTH TABLE
MODE
CE1 CE2
OE
WE
CIO
LB
UB
SAE
D0~7
D8~15
High-Z
VCC Current
H
X
L
X
L
X
X
X
L
H
L
L
H
L
X
X
X
H
L
L
H
L
L
Fully Standby
Output Disable
X
H
X
H
X
X
X
X
High-Z
ICCSB, ICCSB1
H
High-Z
Dout
High-Z
Dout
Din
High-Z
High-Z
Dout
Dout
X
ICC
Read from SRAM
( WORD mode )
L
L
H
H
L
X
H
L
H
H
X
X
ICC
Write to SRAM
( WORD mode )
ICC
X
Din
Din
Din
Read from SRAM
( BYTE Mode )
L
L
H
H
L
X
H
L
L
L
X
X
X
X
A-1
A-1
Dout
Din
High-Z
X
ICC
Write to SRAM
( BYTE Mode )
ICC
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
SYMBOL
VTERM
PARAMETER
RATING
UNITS
AMBIENT
TEMPERATURE
0 O C to +70 O
RANGE
Vcc
Terminal Voltage with
Respect to GND
-0.5 to
V
Vcc+0.5
O C
O C
W
Commercial
Industrial
C
1.8V ~ 2.3V
1.8V ~ 2.3V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
TBIAS
-40 O C to +85O
C
STG
T
P
T
DC Output Current
20
mA
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
IOUT
PARAMETER CONDITIONS MAX.
UNIT
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
CIN
VIN=0V
I/O
6
8
pF
Capacitance
Input/Output
Capacitance
DQ
C
V
=0V
pF
1. This parameter is guaranteed and not tested.
Revision 2.2
April 2001
R0201-BS616UV1620
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BS616UV1620
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
(1)
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
0.4
UNITS
NAME
Guaranteed Input Low
Vcc= 2.0V
Vcc= 2.0V
IL
V
-0.5
--
--
--
V
V
(2)
Voltage
Guaranteed Input High
IH
V
1.4
--
Vcc+0.2
1
(2)
Voltage
IL
I
Input Leakage Current
Vcc = Max, VIN
uA
= 0V to Vcc
iL
Vcc = Max, CE1 = VIH, or CE2 =V , or
OL
I
Output Leakage Current
--
--
1
uA
IH
I/O
OE = V , V = 0V to Vcc
Vcc= 2.0V
Vcc= 2.0V
OL
OL
V
Output Low Voltage
Output High Voltage
Vcc= max, I = 1mA
--
--
--
0.4
--
V
V
OH
OH
V
Vcc= Min, I = -0.5mA
1.6
IL
Vcc= max, CE1 = V and CE2 =
Operating Power Supply
Current
Vcc= 2.0V
Vcc= 2.0V
IH
V ,
CC
I
--
--
--
--
25
mA
mA
(3)
DQ
I
= 0mA, F =Fmax
Vcc= max, CE1 = V or CE2 =
IH
CCSB
I
Standby Current-TTL
0.8
IL
DQ
V , I = 0mA
Vcc= max,CE1
Vcc-0.2V, or
Њ
CE2
0.2V, or LB and UB
Љ
Њ
Vcc= 2.0V
CCSB1
I
Standby Current-CMOS
--
1.2
30
uA
Vcc - 0.2V,
IN
V
IN
Vcc - 0.2V or V
0.2V
Њ
Љ
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/ tRC
.
Revision 2.2
April 2001
R0201-BS616UV1620
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BSI
BS616UV1620
DATA RETENTION CHARACTERISTICS ( TA = 0oC to +70oC )
(1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
UNITS
CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V or
LB Њ Vcc - 0.2V and UB Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
V
VDR
Vcc for Data Retention
1.5
--
--
CE1 Њ Vcc - 0.2V or CE2 Љ 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
ICCDR
Data Retention Current
--
0
0.8
15
uA
Chip Deselect to Data
Retention Time
tCDR
--
--
--
--
ns
ns
See Retention Waveform
(2)
tR
Operation Recovery Time
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
Data Retention Mode
DR Њ 1.5V
V
Vcc
Vcc
t
Vcc
CE1
R
t
CDR
CE1 Њ Vcc - 0.2V
VIH
VIH
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
Data Retention Mode
DR Њ 1.5V
V
Vcc
Vcc
t
Vcc
CE2
R
t
CDR
CE2 Љ 0.2V
VIL
VIL
Revision 2.2
April 2001
R0201-BS616UV1620
5
BSI
BS616UV1620
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
5ns
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
MAY CHANGE
FROM L TO H
WILL BE
1333 Ω
1333 Ω
CHANGE
2V
OUTPUT
2V
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
ANY CHANGE
PERMITTED
100PF
5PF
UNKNOWN
INCLUDING
INCLUDING
Ω
Ω
2000
2000
JIG AND
SCOPE
JIG AND
SCOPE
DOES NOT
APPLY
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
FIGURE 1A
FIGURE 1B
THEVENIN EQUIVALENT
800
Ω
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc = 2.0V )
READ CYCLE
JEDEC
BS616UV1620-70
BS616UV1620-10
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
UNIT
PARAMETER PARAMETER
NAME
NAME
MIN. TYP. MAX.
MIN. TYP. MAX.
tAVAX
tAVQV
tE1LQV
tE2LQV
tBA
tRC
70
70
70
70
50
50
10
10
10
100
100
100
100
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
tACS1
tACS2
tBA
(CE1)
(CE2)
(LB,UB)
Chip Select Access Time
Data Byte Control Access Time
tGLQV
tE1LQX
tBE
tOE
Output Enable to Output Valid
Chip Select to Output Low Z
Data Byte Control to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Data Byte Control to Output High Z
Output Disable to Output in High Z
60
tCL1
tBE
(CE2,CE1)
(LB,UB)
15
15
15
tGLQX
tE1HQZ
tBDO
tOLZ
tCHZ
tBDO
tOHZ
(CE2,CE1)
(LB,UB)
0
0
0
35
30
30
0
0
0
40
35
35
tGHQZ
10
15
Output Disable to Output Address Change
ns
tOH
tAXQX
R0201-BS616UV1620
Revision 2.2
April 2001
6
BSI
BS616UV1620
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE2
t
t
ACS2
ACS1
CE1
(5)
CHZ
(5)
CLZ
t
t
D OUT
READ CYCLE3 (1,4)
ADDRESS
t
RC
t
AA
OE
t
OH
t
OE
CE2
CE1
t
ACS2
t
OLZ
(5)
t
ACS1
t
t
OHZ
(1,5)
CHZ
(5)
CLZ
t
LB,UB
D OUT
t
BE
t
BDO
t
BA
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2 = VIH.
3. Address valid prior to or coincident with CE1 transition low and CE2 transition high.
4. OE = VIL .
5. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.2
April 2001
R0201-BS616UV1620
7
BSI
BS616UV1620
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to +70oC, Vcc = 2.0V )
WRITE CYCLE
JEDEC
BS616UV1620-70
BS616UV1620-10
UNIT
MIN. TYP. MAX.
DESCRIPTION
Write Cycle Time
Chip Select to End of Write
Address Set up Time
PARAMETER PARAMETER
NAME
NAME
MIN. TYP. MAX.
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tBW
tWC
tCW
tAS
100
100
0
100
70
0
80
0
70
70
0
70
50
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAW
tWP
tWR
tBW
tWHZ
tDW
tDH
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
(CE2, CE1, WE)
(LB,UB)
Data Byte Control to End of Write
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
60
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
0
30
0
0
5
40
40
30
30
40
0
0
tOHZ
tOW
10
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(5)
CE2
(11)
CW
t
(5)
CE1
t
BW
(5)
LB,UB
t
AW
(3)
t
WP
(2)
t
AS
(4,10)
OHZ
WE
t
D OUT
t
DH
t
DW
D IN
Revision 2.2
April 2001
R0201-BS616UV1620
8
BSI
BS616UV1620
WRITE CYCLE2 (1,6)
t
WC
ADDRESS
CE2
(11)
CW
t
(5)
(5)
CE1
t
BW
LB,UB
t
WR
t
AW
(3)
t
WP
(2)
t
DH
WE
t
AS
(4,10)
WHZ
(7)
(8)
t
D OUT
t
DW
(8,9)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE2, CE1 and WE low.
All signals must be active to initiate a write and any one signal can terminate
a write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. TWR is measured from the earlier of CE2 going low, or CE1 or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE2 high transition or CE1 low transition or LB,UB low transition occurs simultaneously with the WE low transitions
or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE2 is high or CE1 is low during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 30pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE2 going high or CE1 going low to the end of write.
Revision 2.2
April 2001
R0201-BS616UV1620
9
BSI
BS616UV1620
ORDERING INFORMATION
BS616UV1620 X X -- Y Y
SPEED
70: 70ns
10: 100ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
B : BGA - 48 (8x10mm)
F : BGA - 48 (9x12mm)
PACKAGE DIMENSIONS
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
D1
N
D
E
D1
E1
e
48
10.0
8.0
5.25
3.75
0.75
SOLDER BALL
0.35̈́ 0.05
VIEW A
48 mini-BGA (8 x 10mm)
Revision 2.2
April 2001
R0201-BS616UV1620
10
BSI
BS616UV1620
PACKAGE DIMENSIONS (continued)
NOTES:
1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS.
2: PIN#1 DOT MARKING BY LASER OR PAD PRINT.
3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS.
SIDE VIEW
D
0.1
N
D
E
D1
E1
e
D1
48
12.0
9.0
5.25
3.75
0.75
3.375
SOLDER BALL 0.35̈́0.05
VIEW A
48 mini-BGA (9 x 12mm)
Revision 2.2
April 2001
R0201-BS616UV1620
11
BSI
BS616UV1620
REVISION HISTORY
Revision Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
Revision 2.2
April 2001
R0201-BS616UV1620
12
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