BS62LV2006_08 [BSI]
Very Low Power CMOS SRAM 256K X 8 bit; 超低功耗CMOS SRAM 256K ×8位
| 型号： | BS62LV2006_08 |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Very Low Power CMOS SRAM 256K X 8 bit |
| 文件： | 总10页 (文件大小：328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Very Low Power CMOS SRAM
256K X 8 bit
BS62LV2006
Pb-Free and Green package materials are compliant to RoHS
FEATURES
DESCRIPTION
y Wide VCC operation voltage : 2.4V ~ 5.5V
y Very low power consumption :
The BS62LV2006 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 by 8 bits and
operates form a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both
high speed and low power features with maximum CMOS standby
current of 2/20uA at Vcc=3V/5V at 85OC and maximum access time
of 55/70ns.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2), and active LOW output
enable (OE) and three-state output drivers.
V
CC = 3.0V Operation current : 23mA (Max.) at 55ns
2mA (Max.) at 1MHz
Standby current : 0.7/2uA (Max.) at 70/85OC
CC = 5.0V Operation current : 55mA (Max.) at 55ns
10mA (Max.) at 1MHz
V
Standby current : 6/20uA (Max.) at 70/85OC
y High speed access time :
-55
-70
55ns (Max.) at VCC : 3.0~5.5V
70ns (Max.) at VCC : 2.7~5.5V
y Automatic power down when chip is deselected
y Easy expansion with CE2, CE1 and OE options
y Three state outputs and TTL compatible
y Fully static operation
The BS62LV2006 has an automatic power down feature, reducing
the power consumption significantly when chip is deselected.
The BS62LV2006 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP
package.
y Data retention supply voltage as low as 1.5V
POWER CONSUMPTION
POWER DISSIPATION
Operating
STANDBY
PRODUCT
FAMILY
OPERATING
PKG TYPE
(ICCSB1, Max)
(ICC, Max)
TEMPERATURE
VCC=5V
10MHz
VCC=3V
10MHz
VCC=5.0V VCC=3.0V
1MHz
9mA
fMax.
1MHz
fMax.
BS62LV2006DC
BS62LV2006SC
BS62LV2006STC
BS62LV2006TC
BS62LV2006SI
BS62LV2006STI
BS62LV2006TI
DICE
SOP-32
Commercial
6.0uA
20uA
0.7uA
2.0uA
29mA
30mA
53mA
1.5mA
9mA
22mA
+0OC to +70OC
STSOP-32
TSOP-32
SOP-32
STSOP-32
TSOP-32
Industrial
10mA
55mA
2mA
10mA
23mA
-40OC to +85OC
PIN CONFIGURATIONS
BLOCK DIAGRAM
A11
A9
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
2
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A7
A12
A14
A16
A17
A15
A11
A8
A9
A13
A8
3
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
4
5
Address
Input
Memory Array
1024 x 2048
6
10
1024
Row
Decoder
BS62LV2006TC
BS62LV2006TI
BS62LV2006STC
BS62LV2006STI
7
8
9
Buffer
10
11
12
13
14
15
16
A6
A1
2048
A5
A2
A4
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
Data
8
8
8
Column I/O
Input
Buffer
Write Driver
Sense Amp
8
Data
Output
Buffer
A17
A16
A14
A12
A7
1
2
3
4
5
6
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
256
•
Column Decoder
8
CE2
CE1
WE
OE
VCC
A6
A5
A4
7
8
Control
Address Input Buffer
BS62LV2006SC
BS62LV2006SI
A3
A2
A1
A0
DQ0
DQ1
DQ2
9
10
11
12
13
14
15
GND
A6 A5 A10 A4 A3 A2 A1 A0
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.
R0201-BS62LV2006
Revision
Oct.
1.4
1
2008
BS62LV2006
PIN DESCRIPTIONS
Name
Function
These 18 address inputs select one of the 262,144 x 8-bit in the RAM
A0-A17 Address Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read form or write to the device. If either chip enable is not active, the device is
deselected and is in standby power mode. The DQ pins will be in the high impedance
state when the device is deselected.
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impendence state when OE is inactive.
There 8 bi-directional ports are used to read data from or write data into the RAM.
WE Write Enable Input
OE Output Enable Input
DQ0-DQ7 Data Input/Output
Ports
VCC
Power Supply
Ground
GND
TRUTH TABLE
CE1
WE
X
OE
X
MODE
CE2
X
I/O OPERATION VCC CURRENT
H
X
L
L
L
Not selected
High Z
ICCSB, ICCSB1
(Power Down)
L
X
X
Output Disabled
Read
H
H
H
H
H
High Z
DOUT
DIN
ICC
ICC
ICC
H
L
Write
L
X
ABSOLUTE MAXIMUM RATINGS (1)
OPERATING RANGE
AMBIENT
SYMBOL
VTERM
TBIAS
PARAMETER
RATING
UNITS
V
RANG
Commercial
Industrial
VCC
TEMPERATURE
Terminal Voltage with
-0.5(2) to 7.0
-40 to +125
-60 to +150
1.0
0OC to + 70OC
2.4V ~ 5.5V
2.4V ~ 5.5V
Respect to GND
Temperature Under
Bias
OC
-40OC to + 85OC
TSTG
Storage Temperature
Power Dissipation
DC Output Current
OC
PT
W
CAPACITANCE (1) (TA = 25OC, f = 1.0MHz)
IOUT
20
mA
SYMBOL PAMAMETER CONDITIONS MAX. UNITS
Input
1. Stresses greater than those listed under ABSOLUTE
MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CIN
CIO
VIN = 0V
VI/O = 0V
6
8
pF
pF
Capacitance
Input/Output
Capacitance
1. This parameter is guaranteed and not 100% tested.
2. –2.0V in case of AC pulse width less than 30 ns.
Revision
Oct.
1.4
2008
R0201-BS62LV2006
2
BS62LV2006
DC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
PARAMETER
PARAMETER
TEST CONDITIONS
MIN.
2.4
-0.5(2)
2.2
--
TYP.(1)
MAX.
UNITS
NAME
VCC
Power Supply
--
--
--
--
--
--
5.5
V
V
VIL
VIH
IIL
Input Low Voltage
0.8
Input High Voltage
VCC+0.3(3)
V
Input Leakage Current
Output Leakage Current
Output Low Voltage
VCC = Max, VIN = 0V to VCC
1
1
UA
UA
V
VCC = Max, CE1= VIH, CE2= VIL, or
OE = VIH, VI/O = 0V to VCC
ILO
--
VOL
VOH
VCC = Max, IOL = 2.0mA
VCC = Min, IOH = -1.0mA
--
0.4
Output High Voltage
2.4
--
--
V
VCC=3.0V
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0.1
0.6
23
55
2
10
0.5
1.0
2.0
20
Operating Power Supply
Current
(5)
CE1 = VIL, CE2 = VIH,
ICC
mA
mA
mA
uA
(4)
I
DQ = 0mA, f = FMAX
VCC=5.0V
VCC=3.0V
Operating Power Supply
Current
CE1 = VIL, CE2 = VIH,
DQ = 0mA, f = 1MHz
ICC1
I
VCC=5.0V
VCC=3.0V
VCC=5.0V
VCC=3.0V
VCC=5.0V
CE1 = VIH, or CE2 = VIL,
DQ = 0mA
ICCSB
Standby Current – TTL
I
(6)
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
ICCSB1
Standby Current – CMOS
1. Typical characteristics are at TA=25OC and not 100% tested.
2. Undershoot: -1.0V in case of pulse width less than 20 ns.
3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns.
4. FMAX=1/tRC.
5. ICC (MAX.) is 22mA/53mA at VCC=3.0V/5.0V and TA=70OC.
6. ICCSB1(MAX.) is 0.7uA/6.0uA at VCC=3.0V/5.0V and TA=70OC.
DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC)
SYMBOL
VDR
PARAMETER
TEST CONDITIONS
MIN.
TYP. (1)
MAX.
UNITS
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
VCC for Data Retention
1.5
--
--
V
CE1≧VCC-0.2V or CE2≦0.2V,
VIN≧VCC-0.2V or VIN≦0.2V
(3)
ICCDR
Data Retention Current
--
0
0.05
--
1.0
--
uA
ns
ns
Chip Deselect to Data
Retention Time
tCDR
tR
See Retention Waveform
(2)
Operation Recovery Time
tRC
--
--
1. VCC=1.5V, TA=25OC and not 100% tested.
2. tRC = Read Cycle Time.
3. ICCRD(Max.) is 0.5uA at TA=70OC.
LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled)
Data Retention Mode
VDR≧1.5V
VCC
tCDR
VCC
tR
VCC
CE1≧VCC - 0.2V
VIH
VIH
CE1
Revision
Oct.
1.4
R0201-BS62LV2006
3
2008
BS62LV2006
LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled)
Data Retention Mode
VDR≧1.5V
VCC
tCDR
VCC
tR
VCC
CE2≦0.2V
CE2
VIL
VIL
AC TEST CONDITIONS
KEY TO SWITCHING WAVEFORMS
(Test Load and Input/Output Reference)
WAVEFORM
INPUTS
OUTPUTS
Input Pulse Levels
Vcc / 0V
1V/ns
MUST BE
STEADY
MUST BE
STEADY
Input Rise and Fall Times
Input and Output Timing
Reference Level
0.5Vcc
MAY CHANGE
WILL BE CHANGE
FROM “H” TO “L”
FROM “H” TO “L”
tCLZ, tOLZ, tCHZ, tOHZ, tWHZ
CL = 5pF+1TTL
CL = 30pF+1TTL
Output Load
Others
MAY CHANGE
WILL BE CHANGE
FROM “L” TO “H”
FROM “L” TO “H”
ALL INPUT PULSES
DON’T CARE
ANY CHANGE
PERMITTED
VCC
CHANGE :
1 TTL
90%
90%
STATE UNKNOW
Output
10%
10%
GND
(1)
→
←
→
←
CENTER LINE IS
HIGH INPEDANCE
“OFF” STATE
CL
DOES NOT
APPLY
Rise Time :
Fall Time :
1V/ns
1V/ns
1. Including jig and scope capacitance.
AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
READ CYCLE
CYCLE TIME : 55ns CYCLE TIME : 70ns
(VCC = 3.0~5.5V) (VCC = 2.7~5.5V)
MIN. TYP. MAX. MIN. TYP. MAX.
JEDEC
PARANETER
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
UNITS
NAME
tAVAX
tAVQX
tRC
tAA
55
--
--
--
--
--
--
--
--
--
--
--
--
--
--
55
55
55
30
--
70
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
70
35
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
Chip Select Access Time
(CE1)
(CE2)
tE1LQV
tE2HQV
tGLQV
tE1LQX
tE2HQX
tGLQX
tE1HQZ
tE2LQZ
tGHQZ
tAVQX
tACS1
tACS2
tOE
--
--
Chip Select Access Time
--
--
Output Enable to Output Valid
Chip Select to Output Low Z
Chip Select to Output Low Z
Output Enable to Output Low Z
Chip Select to Output High Z
Chip Select to Output High Z
Output Enable to Output High Z
Data Hold from Address Change
--
--
(CE1)
tCLZ1
tCLZ2
tOLZ
tCHZ1
tCHZ2
tOHZ
tOH
10
10
10
5
(CE2) 10
5
--
--
--
--
(CE1)
(CE2)
--
--
30
30
25
--
--
35
35
30
--
--
--
--
10
10
Revision
Oct.
1.4
R0201-BS62LV2006
4
2008
BS62LV2006
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE 1 (1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DOUT
READ CYCLE 2 (1,3,4)
CE1
tACS1
CE2
DOUT
tACS2
(5)
tCHZ1, tCHZ2
(5)
tCLZ
READ CYCLE 3 (1, 4)
ADDRESS
tRC
tAA
OE
tOH
tOE
tOLZ
CE1
(5)
(5)tACS1
tOH(1Z,5)
tCLZ1
tCHZ1
CE2
DOUT
tACS2
(5)
(2,5)
tCHZ2
tCLZ2
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL.
5. Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
Revision
Oct.
1.4
R0201-BS62LV2006
5
2008
BS62LV2006
AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC)
WRITE CYCLE
CYCLE TIME : 55ns CYCLE TIME : 70ns
(VCC = 3.0~5.5V) (VCC = 2.7~5.5V)
MIN. TYP. MAX. MIN. TYP. MAX.
JEDEC
PARANETER
PARAMETER
NAME
DESCRIPTION
Write Cycle Time
UNITS
NAME
tAVAX
tE1LWH
tAVWL
tAVWH
tWLWH
tWHAX
tE2LAX
tWLQZ
tDVWH
tWHDX
tGHQZ
tWHQX
tWC
tCW
tAS
55
55
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
70
70
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set up Time
--
--
tAW
Address Valid to End of Write
Write Pulse Width
55
30
0
--
70
35
0
--
tWP
tWR1
tWR2
tWHZ
tDW
tDH
--
--
Write Recovery Time
(CE1, WE)
(CE2)
--
--
Write Recovery Time
0
--
0
--
Write to Output High Z
--
25
--
--
30
--
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End of Write to Output Active
25
0
30
0
--
--
tOHZ
tOW
--
25
--
--
30
--
5
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE 1 (1)
tWC
ADDRESS
OE
(3)
tWR1
(11)
tCW
(5)
(5)
CE1
CE2
(11)
(2)
tCW
(3)
tWR2
tAW
tWP
WE
tAS
(4,10)
tOHZ
DOUT
tDH
tDW
DIN
Revision
Oct.
1.4
R0201-BS62LV2006
6
2008
BS62LV2006
WRITE CYCLE 2 (1,6)
ADDRESS
tWC
(11)
tCW
(5)
(5)
CE1
CE2
WE
(11)
(2)
tCW
(3)
tAW
tWR2
tWP
tAS
(4,10)
tWHZ
(7)
(8)
tOW
DOUT
tDW
tDH
(8,9)
DIN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and
WE low. All signals must be active to initiate a write and any one signal can terminate a
write by going inactive. The data input setup and hold timing should be referenced to the
second transition edge of the signal that terminates the write.
3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of
write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite
phase to the outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the
data input signals of opposite phase to the outputs must not be applied to them.
10.Transition is measured ± 500mV from steady state with CL = 5pF.
The parameter is guaranteed but not 100% tested.
11.tCW is measured from the later of CE1 going low or CE2 going high to the end of write.
Revision
Oct.
1.4
R0201-BS62LV2006
7
2008
BS62LV2006
ORDERING INFORMATION
BS62LV2006
X
X
Z Y Y
SPEED
55: 55ns
70: 70ns
PKG MATERIAL
G: Green, RoHS Compliant
P: Pb free, RoHS Compliant
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
PACKAGE
D: DICE
S: SOP
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
Note:
BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does
not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result
in significant injury or death, including life-support systems and critical medical instruments.
PACKAGE DIMENSIONS
b
WITH PLATING
c
c1
b1
BASE METAL
SECTION A-A
SOP -32
Revision
Oct.
1.4
R0201-BS62LV2006
8
2008
BS62LV2006
PACKAGE DIMENSIONS (continued)
STSOP - 32
TSOP - 32
Revision
Oct.
1.4
R0201-BS62LV2006
9
2008
BS62LV2006
Revision History
Revision No.
1.2
History
Draft Date
Remark
Add Icc1 characteristic parameter
Improve Iccsb1 spec.
Jan. 13, 2006
I-grade from 30uA to 20uA at 5.0V
5.0uA to 2.0uA at 3.0V
C-grade from 10uA to 6.0uA at 5.0V
3.0uA to 0.7uA at 3.0V
1.3
1.4
Change I-grade operation temperature range
May. 25, 2006
Oct. 31, 2008
O
O
- from –25 C to –40 C
Typical value of standby current is replaced by
maximum value in Featues and Description
section
Remove “-: Normal” (Leaded) PKG Material in
ordering information
Remove BGA Package
Revision
1.4
2008
R0201-BS62LV2006
10
Oct.
相关型号：
©2020 ICPDF网 联系我们和版权申明