BS62UV1024STC15 [BSI]

Standard SRAM, 128KX8, 150ns, CMOS, PDSO32;


型号：	BS62UV1024STC15
厂家：	BRILLIANCE SEMICONDUCTOR
描述：	Standard SRAM, 128KX8, 150ns, CMOS, PDSO32 静态存储器光电二极管内存集成电路
文件：	总10页 (文件大小：433K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Ultra Low Power/Voltage CMOS SRAM

128K X 8 bit

BSI

BS62UV1024

FEATURES

DESCRIPTION

• Wide Vcc operation voltage : 2.0V ~ 3.6V

The BS62UV1024 is a high performance , ultra low power CMOS

Static Random Access Memory organized as 131,072 words by 8 bits

and operates from a wide range of 2.0V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current of

0.01uA@2.2V/25^oC and maximum access time of 150ns.

Easy memory expansion is provided by an active LOW chip

enable (CE1), an active HIGH chip enable (CE2), and active LOW

output enable (OE) and three-state output drivers.

• Ultra low power consumption :

Vcc = 2.2V C-grade : 10mA (Max.) operating current

I- grade : 15mA (Max.) operating current

0.01uA (Typ.) CMOS standby current

Vcc = 3.0V C-grade : 20mA (Max.) operating current

I- grade : 25mA (Max.) operating current

0.02uA (Typ.) CMOS standby current

• High speed access time :

-15

150ns (Max.)

The BS62UV1024 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS62UV1024 is available in the JEDEC standard 32 pin

450mil Plastic SOP, 8mmx13.4mm STSOP 300mil Plastic SOJ and

8mmx20mm TSOP.

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE2, CE1, and OE options

PRODUCT FAMILY

POWER DISSIPATION

SPEED

(ns)

STANDBY

Operating

(ICC, Max)

PRODUCT

FAMILY

OPERATING

TEMPERATURE

Vcc

RANGE

PKG TYPE

(ICCSB1, Max)

Vcc=

2.0V~3.6V

Vcc=

3.0V

Vcc=

2.2V

Vcc=

3.0V

Vcc=

2.2V

-32

SOP

TSOP

BS62UV1024SC

BS62UV1024TC

BS62UV1024JC

BS62UV1024STC

BS62UV1024PC

BS62UV1024DC

BS62UV1024SI

BS62UV1024TI

BS62UV1024JI

BS62UV1024STI

BS62UV1024PI

BS62UV1024DI

-32

STSOP 32

+0 ^OC to +70 ^O

2.0V ~ 3.6V

150

1.0uA

0.7uA

1uA

20mA

10mA

15mA

SOJ

-32

PDIP

DICE

SOP

-32

TSOP

SOJ 32

STSOP

-40 ^OC to +85 ^O

1.5uA

25mA

-32

PDIP-

DICE

BLOCK DIAGRAM

PIN CONFIGURATIONS

A16

A14

A12

VCC

A15

CE2

A12

A14

A16

A15

A13

Address

Memory Array

1024 x 1024

1024

BS62UV1024SC

BS62UV1024SI

BS62UV1024PC

BS62UV1024PI

BS62UV1024JC

BS62UV1024JI

Row

Decoder

Input

A11

Buffer

A10

CE1

DQ7

DQ6

DQ5

DQ4

DQ3

A11

DQ0

DQ1

DQ2

GND

1024

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Data

Input

Buffer

Column I/O

Write Driver

Sense Amp

Data

Output

Buffer

128

A11

A10

CE1

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

Column Decoder

A13

CE2

A15

VCC

A16

A14

A12

CE2

CE1

BS62UV1024TC

Control

BS62UV1024STC

BS62UV1024TI

BS62UV1024STI

Address Input Buffer

Vdd

Gnd

A5 A4 A3 A2 A1 A0 A10

Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.

Revision 2.3

Jan. 2004

R0201-BS62UV1024

BSI

BS62UV1024

PIN DESCRIPTIONS

Name

Function

A0-A16 Address Input

These 17 address inputs select one of the 131,072 x 8-bit words in the RAM

CE1 Chip Enable 1 Input

CE2 Chip Enable 2 Input

CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when

data read from or write to the device. If either chip enable is not active, the device is

deselected and is in a standby power mode. The DQ pins will be in the high

impedance state when the device is deselected.

WE Write Enable Input

OE Output Enable Input

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

DQ0-DQ7 Data Input/Output

Ports

Vcc

Power Supply

Ground

Gnd

TRUTH TABLE

MODE

CE1

CE2

I/O OPERATION

High Z

Vcc CURRENT

Not selected

(Power Down)

I_CCSB, I_CCSB1

Output Disabled

Read

High Z

I_CC

OUT

Write

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

OPERATING RANGE

AMBIENT

TEMPERATURE

0 ^OC to +70 ^O

SYMBOL

PARAMETER

Terminal Voltage with

Respect to GND

RATING

-0.5 to

Vcc+0.5

UNITS

RANGE

Vcc

TERM

BIAS

STG

Commercial

Industrial

2.0V ~ 3.6V

Temperature Under Bias

Storage Temperature

Power Dissipation

-40 to +125

-60 to +150

1.0

^OC

-40 ^OC to +85^O

CAPACITANCE ⁽¹⁾(TA = 25^oC, f = 1.0 MHz)

DC Output Current

OUT

SYMBOL

PARAMETER

CONDITIONS

MAX.

UNIT

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

Input

=0V

Capacitance

Input/Output

Capacitance

CDQ

VI/O=0V

1. This parameter is guaranteed and not 100% tested.

Revision 2.3

Jan. 2004

R0201-BS62UV1024

BSI

BS62UV1024

DC ELECTRICAL CHARACTERISTICS ( TA = 0^oC to + 70^oC )

PARAMETER

MIN. TYP. ⁽¹⁾MAX.

UNITS

PARAMETER

TEST CONDITIONS

NAME

Vcc=2.2V

Vcc=3.0V

Vcc=2.2V

Vcc=3.0V

Guaranteed Input Low

Voltage⁽²⁾

0.6

0.8

-0.5

1.4

2.0

Guaranteed Input High

Voltage⁽²⁾

V^IH

Vcc+0.2

Input Leakage Current

Output Leakage Current

Vcc = Max, V = 0V to Vcc

IL,

Vcc = Max, CE1= V , CE2= V or

OE = V , V = 0V to Vcc

I^LO

I/O

Vcc=2.2V

Vcc=3.0V

Vcc=2.2V

Vcc=3.0V

Vcc=2.2V

Vcc=3.0V

Vcc=2.2V

Vcc=3.0V

Vcc=2.2V

Vcc=3.0V

Output Low Voltage

Output High Voltage

Vcc = Max, I = 1mA

0.4

1.6

2.4

Vcc = Min, I = -0.5mA

0.5

Operating Power Supply CE1 = V , or CE2 = V ,

I^CC

= 0mA, F = Fmax⁽³⁾

Current

CE1 = V , or CE2 = V ,

^DQ= 0mA

I^CCSB

Standby Current-TTL

CE1≧Vcc-0.2V or CE2≦0.2V,

V_INVcc-0.2V or V 0.2V

0.01

0.02

0.7

CCSB1

Standby Current-CMOS

≧

≦

1. Typical characteristics are at TA = 25^oC.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t_RC

DATA RETENTION CHARACTERISTICS ( TA = 0^oC to + 70^oC )

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP.⁽¹⁾

MAX.

UNITS

CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,

V^IN≧ Vcc - 0.2V or V^IN≦ 0.2V

V_DR

Vcc for Data Retention

1.5

CE1 ≧ Vcc - 0.2V or CE2 ≦ 0.2V,

V^IN≧ Vcc - 0.2V or V^IN≦ 0.2V

I_CCDR

Data Retention Current

0.02

0.3

Chip Deselect to Data

Retention Time

t_CDR

t_R

See Retention Waveform

(2)

Operation Recovery Time

T_RC

1. Vcc = 1.5V, T_A= + 25^OC

2. t_RC= Read Cycle Time

LOW V_CCDATA RETENTION WAVEFORM (1) ( CE1 Controlled )

Data Retention Mode

^DR≥ 1.5V

Vcc

CE1

CDR

≥

CE1 Vcc - 0.2V

VIH

LOW V_CCDATA RETENTION WAVEFORM (2) ( CE2 Controlled )

Data Retention Mode

VDR ≧ 1.5V

Vcc

CDR

CE2 ≦ 0.2V

VIL

CE2

Revision 2.3

R0201-BS62UV1024

Jan.

2004

BSI

BS62UV1024

KEY TO SWITCHING WAVEFORMS

AC TEST CONDITIONS

Input Pulse Levels

Input Rise and Fall Times

Input and Output

Vcc/0V

1V/ns

WAVEFORM

INPUTS

OUTPUTS

MUST BE

STEADY

MUST BE

STEADY

Timing Reference Level

0.5Vcc

MAY CHANGE

FROM H TO L

WILL BE

CHANGE

FROM H TO L

AC TEST LOADS AND WAVEFORMS

Ω

1333

5PF

MAY CHANGE

FROM L TO H

WILL BE

CHANGE

FROM L TO H

OUTPUT

DON T CARE:

CHANGE :

STATE

UNKNOWN

100PF

ANY CHANGE

PERMITTED

INCLUDING

JIG AND

SCOPE

INCLUDING

JIG AND

SCOPE

Ω

2000

DOES NOT

APPLY

CENTER

FIGURE 1A

FIGURE 1B

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

THEVENIN EQUIVALENT

800

Ω

OUTPUT

1.2V

ALL INPUT PULSES

Vcc

GND

10%

90% 90%

10%

→

←

← 1V/ns

AC ELECTRICAL CHARACTERISTICS

READ CYCLE

JEDEC

PARAMETER

NAME

CYCLE TIME : 150ns

MIN. TYP. MAX.

DESCRIPTION

Read Cycle Time

UNIT

NAME

t_AVAX

t_AVQV

t_E1LQV

t_E2HOV

t_GLQV

t_RC

150

100

t_AA

Address Access Time

t_ACS1

t_ACS2

t_OE

Chip Select Access Time

(CE1)

(CE2)

Chip Select Access Time

Output Enable to Output Valid

Chip Select to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Output Disable to Output in High Z

t_E1LQX

t_E2HOX

t_GLQX

t_CLZ1

t_CLZ2

t_OLZ

(CE1)

(CE2)

t_E1HQZ

t_E2HQZ

t_GHQZ

t_CHZ1

t_CHZ2

t_OHZ

(CE1)

(CE2)

t_AXOX

t_OH

Output Disable to Output Address Change

Revision 2.3

Jan. 2004

R0201-BS62UV1024

BSI

BS62UV1024

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 ^(1,2,4)

ADDRESS

D _OUT

READ CYCLE2 ^(1,3,4)

CE1

ACS1

ACS2

CE2

(5)

CHZ2

CHZ1,

(5)

CLZ

D _OUT

READ CYCLE3 ^(1,4)

ADDRESS

OLZ

CE1

(5)

ACS1

OHZ

(1,5)

(5)

CLZ1

CHZ1

CE2

ACS2

(2,5)

CHZ2

(5)

CLZ2

D _OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE1 = V^ILand CE2= VIH.

3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.

4. OE = V^IL

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

Revision 2.3

Jan. 2004

R0201-BS62UV1024

BSI

BS62UV1024

AC ELECTRICAL CHARACTERISTICS

WRITE CYCLE

JEDEC

PARAMETER

NAME

CYCLE TIME : 150ns

MIN. TYP. MAX.

DESCRIPTION

Write Cycle Time

UNIT

NAME

t_AVAX

t_E1LWH

t_AVWL

t_AVWH

t_WLWH

t_WHAX

t_E2LAX

t_WLOZ

t_DVWH

t_WHDX

t_GHOZ

t_WHQX

t_WC

t_CW

t_AS

150

Chip Select to End of Write

Address Set up Time

150

t_AW

t_WP

t_WR1

t_WR2

t_WHZ

t_DW

t_DH

Address Valid to End of Write

Write Pulse Width

150

Write Recovery Time

(CE1 , WE)

(CE2)

Write Recovery Time

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

End of Write to Output Active

t_OHZ

t_OW

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1 ⁽¹⁾

ADDRESS

(3)

WR1

(11)

(5)

CE1

(5)

(11)

(2)

CE2

WR2

(3)

(4,10)

OHZ

D _OUT

D _IN

Revision 2.3

Jan. 2004

R0201-BS62UV1024

BSI

BS62UV1024

(1,6)

WRITE CYCLE2

ADDRESS

(11)

(5)

CE1

(11)

CE2

WR2

(3)

(2)

(4,10)

(7)

(8)

WHZ

D _OUT

(8,9)

D _IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.

All signals must be active to initiate a write and any one signal can terminate a write by going

inactive. The data input setup and hold timing should be referenced to the second transition edge

of the signal that terminates the write.

3. T^WRis measured from the earlier of CE1 or WE going high or CE2 going low at the end of write

cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the

outputs must not be applied.

5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low

transitions or after the WE transition, output remain in a high impedance state.

6. OE is continuously low (OE = V^IL).

7. DOUT is the same phase of write data of this write cycle.

8. D^OUTis the read data of next address.

9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input

signals of opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C^L= 5pF as shown in Figure 1B. The

parameter is guaranteed but not 100% tested.

11. T^CWis measured from the later of CE1 going low or CE2 going high to the end of write.

Revision 2.3

R0201-BS62UV1024

Jan.

2004

BSI

BS62UV1024

ORDERING INFORMATION

BS62UV1024 X X Z Y Y

SPEED

15: 150ns

PKG MATERIAL

-: Normal

G: Green

P: Pb free

GRADE

C: +0^oC ~ +70^oC

I: -40^oC ~ +85^oC

PACKAGE

J: SOJ

S: SOP

P: PDIP

T: TSOP (8mm x 20mm)

ST: Small TSOP (8mm x 13.4mm)

D: DICE

Note:

BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products

for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support

systems and critical medical instruments.

PACKAGE DIMENSIONS

WITH PLATING

BASE METAL

SECTION A-A

SOP -32

Revision 2.3

Jan. 2004

R0201-BS62UV1024

BSI

BS62UV1024

PACKAGE DIMENSIONS (continued)

STSOP - 32

TSOP - 32

Revision 2.3

R0201-BS62UV1024

Jan.

2004

BSI

BS62UV1024

PACKAGE DIMENSIONS (continued)

SOJ - 32

PDIP - 32

Revision 2.3

R0201-BS62UV1024

Jan.

2004

BS62UV1024STC15 [BSI]

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