BS62UV256PC [BSI]
Ultra Low Power/Voltage CMOS SRAM 32K X 8 bit; 超低功率/电压CMOS SRAM 32K ×8位
| 型号： | BS62UV256PC |
| 厂家： | 
BRILLIANCE SEMICONDUCTOR |
| 描述： | Ultra Low Power/Voltage CMOS SRAM 32K X 8 bit |
| 文件： | 总11页 (文件大小：332K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultra Low Power/Voltage CMOS SRAM
32K X 8 bit
BSI
BS62UV256
DESCRIPTION
FEATURES
• Ultra low operation voltage : 1.8V ~ 3.6V
• Ultra low power consumption :
The BS62UV256 is a high performance, ultra low power CMOS
Static Random Access Memory organized as 32,768 words by 8 bits
and operates from a wide range of 1.8V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.005uA and maximum access time of 150ns in 2V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE), and active LOW output enable (OE) and three-state
output drivers.
Vcc = 2.0V C-grade : 10mA (Max.) operating current
I- grade : 15mA (Max.) operating current
0.005uA (Typ.) CMOS standby current
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I-grade : 25mA (Max.) operating current
0.01uA (Typ.) CMOS standby current
• High speed access time :
-15
150ns (Max.) at Vcc = 2.0V
The BS62UV256 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62UV256 is available in the JEDEC standard 28 pin
330mil Plastic SOP, 8mmx13.4mm TSOP (normal type), 300mil Plastic
SOJ and 600mil Plastic DIP.
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
PRODUCT FAMILY
POWER DISSIPATION
SPEED
(ns)
STANDBY
Operating
PRODUCT
FAMILY
OPERATING
Vcc
PKG
(ICCSB1, Max)
(ICC, Max)
Vcc=
TEMPERATURE
RANGE
TYPE
Vcc=
Vcc=
Vcc=
2.0V
Vcc=
2.0V
2.0V
3.0V
3.0V
BS62UV256SC
BS62UV256TC
BS62UV256PC
BS62UV256JC
BS62UV256DC
BS62UV256SI
BS62UV256TI
BS62UV256PI
BS62UV256JI
BS62UV256DI
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
+0 O C to +70 O C 1.8V ~ 3.6V
-40 O C to +85 O C 1.8V ~ 3.6V
150
150
0.2uA
0.1uA
0.3uA
20mA
10mA
15mA
SOP-28
TSOP-28
PDIP-28
SOJ-28
DICE
0.4uA
25mA
PIN CONFIGURATIONS
BLOCK DIAGRAM
A14
A12
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
WE
A13
A8
A9
A11
OE
A5
A6
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
A7
Address
Memory Array
512 x 512
A12
A14
A13
18
512
Row
Decoder
Input
BS62UV256SC
BS62UV256SI
BS62UV256PC
BS62UV256PI
Buffer
A10
CE
A8
A9
A11
DQ7
DQ6
DQ5
DQ4
DQ3
512
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Column I/O
8
Input
Buffer
Write Driver
Sense Amp
8
8
Data
64
A10
CE
Output
Buffer
1
28
OE
A11
A9
2
27
26
25
24
23
22
21
20
19
18
17
16
15
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
3
Column Decoder
12
4
A8
5
A13
WE
VCC
A14
A12
A7
6
CE
WE
OE
BS62UV256TC
BS62UV256TI
7
Control
8
Address Input Buffer
9
10
11
12
13
14
Vdd
Gnd
A6
A5
A4 A3 A2 A1 A0 A10
A1
A4
A2
A3
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.
Revision 2.2
April 2001
R0201-BS62UV256
1
BSI
BS62UV256
PIN DESCRIPTIONS
Name
Function
A0-A14 Address Input
These 15 address inputs select one of the 32768 x 8-bit wordsin the RAM
CE Chip Enable Input
WE Write Enable Input
CE is active LOW. Chip enables must be active to read from or write to the device. If
chip enable is not active, the device is deselected and is in a standby power mode.
The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
These 8 bi-directional ports are used to read data from or write data into the RAM.
DQ0-DQ7 Data Input/Output
Ports
Vcc
Power Supply
Ground
Gnd
TRUTH TABLE
MODE
Not selected
Output Disabled
Read
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O OPERATION
High Z
Vcc CURRENT
ICCSB, ICCSB1
High Z
ICC
ICC
ICC
OUT
D
IN
D
Write
ABSOLUTE MAXIMUM RATINGS(1)
OPERATING RANGE
AMBIENT
SYMBOL
PARAMETER
RATING
UNITS
RANGE
Vcc
TEMPERATURE
Terminal Voltage with
Respect to GND
-0.5 to
V
TERM
BIAS
STG
T
V
T
T
P
Vcc+0.5
Commercial
Industrial
0 O C to +70O
-40 O C to +85O
C
1.8V ~ 3.6V
1.8V ~ 3.6V
Temperature Under Bias
Storage Temperature
Power Dissipation
-40 to +125
-60 to +150
1.0
O C
O C
W
C
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
DC Output Current
20
mA
OUT
I
SYMBOL
CIN
PARAMETER
CONDITIONS
MAX.
UNIT
pF
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
Input
VIN=0V
6
Capacitance
Input/Output
Capacitance
CDQ
VI/O=0V
8
pF
1. This parameter is guaranteed and not tested.
Revision 2.2
April 2001
R0201-BS62UV256
2
BSI
BS62UV256
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
PARAMETER
(1)
UNITS
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
NAME
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
0.6
Guaranteed Input Low
VIL
-0.5
--
V
Voltage(2)
0.8
1.4
2.0
--
Guaranteed Input High
Voltage(2)
VIH
IIL
--
--
--
Vcc+0.2
V
Vcc=3.0V
Input Leakage Current
Vcc = Max, VIN = 0V to Vcc
Vcc = Max, CE = VIH, or OE = VIH
I/O = 0V to Vcc
1
1
uA
uA
,
IOL
Output Leakage Current
--
V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
VOL
VOH
Output Low Voltage
Output High Voltage
Vcc = Max, IOL = 1mA
--
--
--
0.4
--
V
V
1.6
2.4
Vcc = Min, IOH = -0.5mA
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
Vcc=2.0V
Vcc=3.0V
--
--
--
--
--
--
--
--
10
20
Operating Power Supply
Current
ICC
CE = VIL, IDQ = 0mA, F = Fmax(3)
mA
mA
uA
--
0.5
1.0
0.1
0.2
ICCSB
Standby Current-TTL
CE = VIH, IDQ = 0mA
--
0.005
0.01
CE Њ Vcc-0.2V,
ICCSB1
Standby Current-CMOS
V
IN Њ Vcc - 0.2V or VIN Љ 0.2V
o
1. Typical characteristics are at TA = 25 C.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC
.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
(1)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN. TYP.
MAX.
UNITS
CE Њ Vcc - 0.2V
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
VDR
Vcc for Data Retention
1.5
--
--
V
CE Њ Vcc -0.2V
ICCDR
Data Retention Current
--
0
0.005
0.1
uA
VIN Њ Vcc - 0.2V or VIN Љ 0.2V
Chip Deselect to Data
Retention Time
Operation Recovery Time
tCDR
tR
--
--
--
--
ns
ns
See Retention Waveform
(2)
TRC
O
1. Vcc = 1.5V, TA = + 25 C
2. tRC = Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM (1) ( CE Controlled )
Data Retention Mode
DR ≥ 1.5V
V
Vcc
Vcc
t
Vcc
CE
R
t
CDR
≥
CE Vcc - 0.2V
VIH
VIH
Revision 2.2
April 2001
R0201-BS62UV256
3
BSI
BS62UV256
KEY TO SWITCHING WAVEFORMS
AC TEST CONDITIONS
Input Pulse Levels
Vcc/0V
WAVEFORM
INPUTS
OUTPUTS
Input Rise and Fall Times 5ns
Input and Output
MUST BE
STEADY
MUST BE
STEADY
Timing Reference Level
0.5Vcc
MAY CHANGE
FROM H TO L
WILL BE
CHANGE
AC TEST LOADS AND WAVEFORMS
FROM H TO L
Ω
Ω
1333
1333
5PF
MAY CHANGE
FROM L TO H
WILL BE
2V
2V
CHANGE
OUTPUT
OUTPUT
FROM L TO H
,
DON T CARE:
CHANGE :
STATE
100PF
ANY CHANGE
PERMITTED
INCLUDING
INCLUDING
Ω
Ω
2000
2000
JIG AND
SCOPE
JIG AND
SCOPE
UNKNOWN
DOES NOT
APPLY
CENTER
FIGURE 1A
FIGURE 1B
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
THEVENIN EQUIVALENT
800
Ω
OUTPUT
1.2V
ALL INPUT PULSES
Vcc
GND
10%
90% 90%
10%
→
→
←
← 5ns
FIGURE 2
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V )
READ CYCLE
JEDEC
PARAMETER
BS62UV256-15
PARAMETER
DESCRIPTION
UNIT
MIN. TYP. MAX.
NAME
NAME
tAVAX
tAVQV
t ELQV
t GLQV
t ELQX
t GLQX
t EHQZ
t GHQZ
tRC
Read Cycle Time
150
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address Access Time
--
--
150
150
100
--
tACS
t OE
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
--
tCLZ
tOLZ
tCHZ
tOHZ
10
10
0
--
35
30
0
t AXOX
tOH
Output Disable to Output Address Change
10
--
--
ns
Revision 2.2
April 2001
R0201-BS62UV256
4
BSI
BS62UV256
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
t
RC
ADDRESS
t
AA
t
OH
t
OH
D OUT
READ CYCLE2 (1,3,4)
CE
t
ACS
(5)
t
CHZ
(5)
CLZ
t
D OUT
READ CYCLE3 (1,4)
t
RC
ADDRESS
OE
t
AA
t
OH
t
OE
t
OLZ
CE
(5)
t
ACS
t
OHZ
(1,5)
t
CHZ
(5)
CLZ
t
D OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = VIL
3. Address valid prior to or coincident with CE transition low.
4. OE = VIL
.
.
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
Revision 2.2
April 2001
R0201-BS62UV256
5
BSI
BS62UV256
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 2.0V )
WRITE CYCLE
JEDEC
PARAMETER
BS62UV256-15
MIN. TYP. MAX.
PARAMETER
DESCRIPTION
UNIT
NAME
NAME
t AVAX
t E1LWH
t AVWL
t AVWH
t WLWH
t WHAX
t WLOZ
t DVWH
t WHDX
t GHOZ
t WHQX
tWC
tCW
tAS
tAW
tWP
tWR
tWHZ
tDW
tDH
Write Cycle Time
150
--
--
--
--
--
--
--
--
--
--
--
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Select to End of Write
Address Set up Time
150
0
--
--
Address Valid to End of Write
Write Pulse Width
150
80
0
--
--
Write Recovery Time
(CE , WE)
--
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Disable to Output in High Z
End ot Write to Output Active
--
30
--
40
0
--
tOHZ
tOW
0
30
--
5
SWITCHING WAVEFORMS (WRITE CYCLE)
WRITE CYCLE1 (1)
t
WC
ADDRESS
OE
(3)
WR
t
(11)
CW
t
(5)
CE
t
AW
t
WP
(2)
t
AS
(4,10)
OHZ
WE
t
D OUT
t
DH
t
DW
D IN
Revision 2.2
April 2001
R0201-BS62UV256
6
BSI
BS62UV256
(1,6)
WRITE CYCLE2
t
WC
ADDRESS
CE
(11)
CW
t
(5)
t
AW
t
WP
(2)
t
DH
WE
t
AS
(4,10)
(7)
(8)
t
WHZ
D OUT
t
DW
(8)
t
DH
D IN
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals
must be active to initiate a write and any one signal can terminate a write by going inactive.
The data input setup and hold timing should be referenced to the second transition edge of
the signal that terminates the write.
3. TWR is measured from the earlier of CE or WE going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase
to the outputs must not be applied.
5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE
transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
Revision 2.2
April 2001
R0201-BS62UV256
7
BSI
BS62UV256
ORDERING INFORMATION
BS62UV256
X X ˀˀ Y Y
SPEED
15: 150ns
GRADE
o
o
C: +0 C ~ +70 C
o
o
I: -40 C ~ +85 C
PACKAGE
S: SOP
P: PDIP
J : SOJ
T: TSOP (8mm x 13.4mm)
D : DICE
PACKAGE DIMENSIONS
0.020 ̈́ 0.005X45̓
θ
b
WITH PLATING
c
c1
BASE METAL
b1
SOP - 28
Revision 2.2
April 2001
R0201-BS62UV256
8
BSI
BS62UV256
PACKAGE DIMENSIONS (continued)
UNIT
SYMBOL
INCH
0.0433̈́0.004
MM
1.10̈́0.10
12̓(2x)
12̓(2x)
A
A1 0.0045̈́0.0026 0.115̈́0.065
HD
c
L
A2 0.039̈́0.002
1.00̈́0.05
0.22̈́0.05
0.20̈́0.03
0.10 ~ 0.21
0.10 ~ 0.16
11.80̈́0.10
8.00̈́0.10
0.55̈́0.10
13.40̈́0.20
b
b1
c
c1
D
E
0.009̈́0.002
0.008̈́0.001
0.004 ~ 0.008
0.004 ~ 0.006
0.465̈́0.004
0.315̈́0.004
0.022̈́0.004
1
28
y
Seating Plane
e
14
15
̓
12 (2X)
HD 0.528̈́0.008
+0.008
0.0197
- 0.004
+0.20
L
0.50
"A"
- 0.10
D
L1
y
0
0.0315̈́0.004
0.004 Max.
0̓~ 8̓
0.80̈́0.10
0.1 Max.
0̓~ 8̓
GAUGE PLANE
A
A
0
SEATING PLANE
14
15
12 (2X)
L
L1
"A" DATAIL VIEW
b
WITH PLATING
1
28
c
c1
BASE METAL
b1
SECTION A-A
TSOP - 28
PDIP - 28
Revision 2.2
April 2001
R0201-BS62UV256
9
BSI
BS62UV256
SOJ - 28
Revision 2.2
April 2001
R0201-BS62UV256
10
BSI
BS62UV256
REVISION HISTORY
Revision
Description
Date
Note
2.2
2001 Data Sheet release
Apr. 15, 2001
Revision 2.2
April 2001
R0201-BS62UV256
11
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