BS62UV4000_技术文档

Ultra Low Power/Voltage CMOS SRAM

512K X 8 bit

BSI

BS62UV4000

DESCRIPTION

FEATURES

• Ultra low operation voltage : 1.8V ~ 3.6V

• Ultra low power consumption :

The BS62UV4000 is a high performance, ultra low power CMOS

Static Random Access Memory organized as 524,288 words by 8 bits

and operates from a wide range of 1.8V to 3.6V supply voltage.

Advanced CMOS technology and circuit techniques provide both high

speed and low power features with a typical CMOS standby current of

0.2uA and maximum access time of 70ns in 2.0V operation.

Easy memory expansion is provided by an active LOW chip

enable (CE), and active LOW output enable (OE) and three-state

output drivers.

Vcc = 2.0V C-grade: 15mA (Max.) operating current

I -grade: 20mA (Max.) operating current

0.2uA (Typ.) CMOS standby current

Vcc = 3.0V C-grade: 20mA (Max.) operating current

I -grade: 25mA (Max.) operating current

0.25uA (Typ.) CMOS standby current

• High speed access time :

-70

-10

70ns (Max.) at Vcc = 2.0V

100ns (Max.) at Vcc = 2.0V

The BS62UV4000 has an automatic power down feature, reducing the

power consumption significantly when chip is deselected.

The BS62UV4000 is available in the JEDEC standard 32 pin SOP

, TSOP, TSOP II and STSOP

• Automatic power down when chip is deselected

• Three state outputs and TTL compatible

• Fully static operation

• Data retention supply voltage as low as 1.5V

• Easy expansion with CE and OE options

PRODUCT FAMILY

POWER DISSIPATION

SPEED

( ns )

STANDBY

Operating

PKG

PRODUCT

FAMILY

OPERATING

Vcc

( I CCSB1 , Max )

( I CC , Max )

TYPE

TEMPERATURE RANGE

Vcc =3.0V

Vcc = 2.0V Vcc = 2.0V

Vcc = 2.0V

15mA

-

BS62UV4000TC

BS62UV4000STC

BS62UV4000SC

BS62UV4000EC

BS62UV4000PC

BS62UV4000TI

BS62UV4000STI

BS62UV4000SI

BS62UV4000EI

BS62UV4000PI

TSOP 32

-

STSOP 32

+0 ^OC to +70^OC

1.8V ~ 3.6V

70 / 100

1uA

2uA

1.5uA

20mA

25mA

-

SOP 32

-

TSOP2 32

-

32

PDIP

-

TSOP 32

-

STSOP 32

O

40 C to +85^OC

3uA

20mA

-

SOP 32

-

TSOP2 32

-

PDIP 32

BLOCK DIAGRAM

PIN CONFIGURATIONS

A18

A16

A14

A12

A7

1

VCC

A15

A17

WE

A13

A8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

2

A13

A17

A15

3

4

Address

Input

A18

A16

A14

A12

A7

Memory Array

2048 X 2048

5

22

2048

Row

Decoder

A6

6

A5

7

A9

A4

BS62UV4000SC

BS62UV4000SI

BS62UV4000EC

BS62UV4000EI

BS62UV4000PC

BS62UV4000PI

8

A11

OE

A10

CE

DQ7

DQ6

DQ5

DQ4

DQ3

Buffer

A3

9

A6

A2

A5

10

11

12

13

14

15

16

A4

A1

A0

2048

DQ0

DQ1

DQ2

GND

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

8

Data

Column I/O

8

Input

Buffer

Write Driver

Sense Amp

8

Data

256

Output

Buffer

1

32

A11

A9

OE

2

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

A10

CE

Column Decoder

16

3

A8

4

A13

WE

A17

A15

VCC

A18

A16

A14

A12

A7

DQ7

DQ6

DQ5

DQ4

DQ3

GND

DQ2

DQ1

DQ0

A0

5

CE

WE

OE

6

Control

BS62UV4000TC

BS62UV4000STC

BS62UV4000TI

BS62UV4000STI

7

Address Input Buffer

8

9

10

11

12

13

14

15

16

Vdd

GND

A11 A9 A8 A3 A2 A1 A0 A10

A6

A1

A5

A2

A4

A3

Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.

Revision 2.4

April 2002

R0201-BS62UV4000

1

BSI

BS62UV4000

PIN DESCRIPTIONS

Name

Function

A0-A18 Address Input

These 19 address inputs select one of the 524,288 x 8-bit words in the RAM

CE Chip Enable Input

WE Write Enable Input

CE is active LOW. Chip enables must be active when data read from or write to the

device. if chip enable is not active, the device is deselected and is in a standby power

mode. The DQ pins will be in the high impedance state when the device is deselected.

The write enable input is active LOW and controls read and write operations. With the

chip selected, when WE is HIGH and OE is LOW, output data will be present on the

DQ pins; when WE is LOW, the data present on the DQ pins will be written into the

selected memory location.

OE Output Enable Input

The output enable input is active LOW. If the output enable is active while the chip is

selected and the write enable is inactive, data will be present on the DQ pins and they

will be enabled. The DQ pins will be in the high impedance state when OE is inactive.

These 8 bi-directional ports are used to read data from or write data into the RAM.

DQ0-DQ7 Data Input/Output

Ports

Vcc

Power Supply

Ground

GND

TRUTH TABLE

MODE

Not selected

Output Disabled

Read

WE

X

H

L

CE

H

L

OE

X

H

L

X

I/O OPERATION

High Z

Vcc CURRENT

I_CCSB, I_CCSB1

High Z

I_CC

OUT

D

IN

D

Write

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

OPERATING RANGE

AMBIENT

TEMPERATURE

0 ^OC to +70 ^O

SYMBOL

VTERM

TBIAS

TSTG

PARAMETER

RATING

UNITS

RANGE

Vcc

Terminal Voltage with

Respect to GND

-0.5 to

V

Vcc+0.5

Commercial

Industrial

C

1.8V ~ 3.6V

Temperature Under Bias

Storage Temperature

Power Dissipation

-40 to +125

-60 to +150

1.0

^OC

W

-40 ^OC to +85 ^O

C

PT

CAPACITANCE ⁽¹⁾(TA = 25^oC, f = 1.0 MHz)

DC Output Current

20

mA

IOUT

SYMBOL

CIN

PARAMETER

CONDITIONS

MAX.

UNIT

pF

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these

or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

reliability.

Input

VIN=0V

6

Capacitance

Input/Output

Capacitance

CDQ

VI/O=0V

8

pF

1. This parameter is guaranteed and not tested.

Revision 2.4

April 2002

R0201-BS62UV4000

2

BSI

BS62UV4000

DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70^oC )

PARAMETER

(1)

UNITS

PARAMETER

TEST CONDITIONS

MIN. TYP.

MAX.

NAME

Guaranteed Input Low

Vcc = 2.0 V

Vcc = 3.0 V

0.6

0.8

V^IL

-0.5

--

V

(2)

Voltage

Guaranteed Input High

Vcc = 2.0 V

Vcc = 3.0 V

1.4

2.0

IH

V

--

Vcc+0.2

1

V

(2)

Voltage

I^IL

Input Leakage Current

Vcc = Max, V^IN= 0V to Vcc

--

1.6

2.4

uA

IH

Vcc = Max, CE = V , or OE = V ,

IOL

Output Leakage Current

--

1

uA

I/O

V

= 0V to Vcc

Vcc = 2.0 V

Vcc = 3.0 V

Vcc = 2.0 V

Vcc = 3.0 V

0.4

--

OL

V

Output Low Voltage

Output High Voltage

Vcc = Max, I = 1mA

--

V

V^OH

OH

= -0.5mA

Vcc = Min, I

Vcc = 2.0 V

Vcc = 3.0 V

15

20

(3)

CC

IL

DQ

I

Operating Power Supply

Current

CE = V , I = 0mA, F = Fmax

--

mA

uA

Vcc = 2.0 V

Vcc = 3.0 V

0.6

1

I^CCSB

CE = V^IH, I^DQ= 0mA

Standby Current-TTL

1

Vcc = 2.0 V

Vcc = 3.0 V

0.2

CE

Vcc-0.2V,

Vcc - 0.2V or V

Њ

Standby Current-CMOS

I^CCSB1

IN

Љ

V

0.2V

1.5

0.25

o

1. Typical characteristics are at TA = 25 C.

2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.

3. Fmax = 1/t_RC

.

DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70^oC )

SYMBOL

PARAMETER

TEST CONDITIONS

MIN.

TYP.⁽¹⁾

MAX.

UNITS

CE Њ Vcc - 0.2V

V^INЊ Vcc - 0.2V or V^INЉ 0.2V

V_DR

Vcc for Data Retention

1.5

--

V

CE Њ Vcc - 0.2V

I_CCDR

Data Retention Current

--

0

0.1

1

uA

V^INЊ Vcc - 0.2V or VIN Љ 0.2V

Chip Deselect to Data

Retention Time

t_CDR

t_R

--

ns

See Retention Waveform

(2)

Operation Recovery Time

T_RC

O

1. Vcc = 1.5V, T_A= + 25 C

2. t_RC= Read Cycle Time

LOW V_CCDATA RETENTION WAVEFORM ( CE Controlled )

Data Retention Mode

^DR≥ 1.5V

V

Vcc

t

Vcc

CE

R

t

CDR

≥

CE Vcc - 0.2V

VIH

Revision 2.4

April 2002

R0201-BS62UV4000

3

BSI

BS62UV4000

KEY TO SWITCHING WAVEFORMS

AC TEST CONDITIONS

Input Pulse Levels

Vcc/0

5ns

WAVEFORM

INPUTS

OUTPUTS

Input Rise and Fall Times

Input and Output

MUST BE

STEADY

MUST BE

STEADY

Timing Reference Level

0.5Vcc

MAY CHANGE

FROM H TO L

WILL BE

CHANGE

AC TEST LOADS AND WAVEFORMS

FROM H TO L

Ω

1333

5PF

MAY CHANGE

FROM L TO H

WILL BE

2V

CHANGE

OUTPUT

FROM L TO H

,

DON T CARE:

CHANGE :

STATE

100PF

ANY CHANGE

PERMITTED

INCLUDING

Ω

2000

JIG AND

SCOPE

JIG AND

SCOPE

UNKNOWN

DOES NOT

APPLY

CENTER

FIGURE 1A

FIGURE 1B

LINE IS HIGH

IMPEDANCE

”OFF ”STATE

THEVENIN EQUIVALENT

800

Ω

OUTPUT

1.2V

ALL INPUT PULSES

Vcc

GND

10%

90% 90%

10%

→

←

← 5ns

FIGURE 2

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70^oC , Vcc = 2.0V )

READ CYCLE

JEDEC

PARAMETER

NAME

BS62UV4000-70

BS62UV4000-10

MIN. TYP. MAX.

PARAMETER

NAME

DESCRIPTION

Read Cycle Time

UNIT

MIN. TYP. MAX.

t

t_RC

t_AA

70

--

100

--

100

50

--

ns

AVAX

t

Address Access Time

--

70

35

--

AVQV

t

t_ACS

t_OE

t_CLZ

t_OLZ

t_CHZ

t_OHZ

Chip Select Access Time

--

ELQV

t

Output Enable to Output Valid

Chip Select to Output Low Z

Output Enable to Output in Low Z

Chip Deselect to Output in High Z

Output Disable to Output in High Z

--

GLQV

t

10

0

15

0

ELQX

t

--

GLQX

t

35

30

40

35

EHQZ

t

0

GHQZ

t_AXOX

t_OH

Output Disable to Output Address Change

10

--

15

--

ns

Revision 2.4

April 2002

R0201-BS62UV4000

4

BSI

BS62UV4000

SWITCHING WAVEFORMS (READ CYCLE)

READ CYCLE1 ^(1,2,4)

t

RC

ADDRESS

t

AA

t

OH

t

OH

D _OUT

READ CYCLE2 ^(1,3,4)

CE

t

ACS

(5)

t

CHZ

(5)

CLZ

t

D _OUT

READ CYCLE3 ^(1,4)

t

RC

ADDRESS

OE

t

AA

t

OH

t

OE

t

ACS

OLZ

CE

(5)

t

OHZ

(1,5)

CHZ

t

(5)

CLZ

t

D _OUT

NOTES:

1. WE is high in read Cycle.

2. Device is continuously selected when CE = V^IL

3. Address valid prior to or coincident with CE transition low.

4. OE = V^IL

.

5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

Revision 2.4

April 2002

R0201-BS62UV4000

5

BSI

BS62UV4000

AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70^oC , Vcc = 2.0V )

WRITE CYCLE

JEDEC

PARAMETER

BS62UV4000-70

MIN. TYP. MAX.

BS62UV4000-10

UNIT

PARAMETER

DESCRIPTION

Write Cycle Time

MIN. TYP. MAX.

NAME

t

t_WC

t_CW

t_AS

AVAX

70

0

--

100

0

--

ns

t_E1LWH

t_AVWL

Chip Select to End of Write

Address Set up Time

--

t_AVWH

t_WLWH

t_WHAX

t_WLOZ

t_DVWH

t_WHDX

t_GHOZ

t_WHQX

t_AW

t_WP

t_WR

t_WHZ

t_DW

t_DH

Address Valid to End of Write

Write Pulse Width

70

35

0

--

100

50

0

--

Write Recovery Time

(CE , WE)

--

Write to Output in High Z

Data to Write Time Overlap

Data Hold from Write Time

Output Disable to Output in High Z

Endot Write to Output Active

--

30

--

40

--

30

0

40

0

--

t_OHZ

t_OW

0

30

--

0

40

--

5

10

SWITCHING WAVEFORMS (WRITE CYCLE)

WRITE CYCLE1 ⁽¹⁾

t

WC

ADDRESS

OE

(3)

t

WR

(11)

CW

t

(5)

CE

t

AW

t

WP

(2)

t

AS

(4,10)

OHZ

WE

t

D _OUT

t

DH

t

DW

D _IN

Revision 2.4

April 2002

R0201-BS62UV4000

6

BSI

BS62UV4000

(1,6)

WRITE CYCLE2

t

WC

ADDRESS

(11)

t

CW

(5)

CE

t

AW

t

WP

(2)

t

DH

WE

t

AS

(4,10)

(7)

(8)

t

WHZ

D _OUT

t

DW

(8,9)

t

DH

D _IN

NOTES:

1. WE must be high during address transitions.

2. The internal write time of the memory is defined by the overlap of CE and WE low. All signals

must be active to initiate a write and any one signal can terminate a write by going inactive.

The data input setup and hold timing should be referenced to the second transition edge of

the signal that terminates the write.

3. T^WRis measured from the earlier of CE or WE going high at the end of write cycle.

4. During this period, DQ pins are in the output state so that the input signals of opposite phase

to the outputs must not be applied.

5. If the CE low transition occurs simultaneously with the WE low transitions or after the WE

transition, output remain in a high impedance state.

6. OE is continuously low (OE = V^IL).

7. D^OUTis the same phase of write data of this write cycle.

8. D^OUTis the read data of next address.

9. If CE is low during this period, DQ pins are in the output state. Then the data input signals of

opposite phase to the outputs must not be applied to them.

10. Transition is measured 500mV from steady state with C^L= 5pF as shown in Figure 1B.

The parameter is guaranteed but not 100% tested.

11. T^CWis measured from the later of CE going low to the end of write.

Revision 2.4

April 2002

R0201-BS62UV4000

7

BSI

BS62UV4000

ORDERING INFORMATION

BS62UV4000

X X ˀˀ Y Y

SPEED

70: 70ns

10: 100ns

GRADE

o

C: +0 C ~ +70 C

o

I: -40 C ~ +85 C

PACKAGE

S: SOP

E: TSOP 2

ST: Small TSOP

T: TSOP

P: PDIP

PACKAGE DIMENSIONS

b

WITH PLATING

c

c1

BASE METAL

b1

SECTION A-A

SOP -32

Revision 2.4

April 2002

R0201-BS62UV4000

8

BSI

BS62UV4000

TSOP2 - 32

TSOP - 32

Revision 2.4

April 2002

R0201-BS62UV4000

9

BSI

BS62UV4000

PACKAGE DIMENSIONS (continued)

STSOP - 32

PDIP - 32

Revision 2.4

April 2002

R0201-BS62UV4000

10

BSI

REVISION HISTORY

BS62UV4000

Revision Description

Date

Note

2.2

2001 Data Sheet release

Apr. 15, 2001

2.3

Modify Standby Current (Typ. Jun. 29, 2001

and Max.)

2.4

Modify some AC parameters

April,10,2002

Revision 2.4

April 2002

R0201-BS62UV4000

11


型号：	BS62UV4000
厂家：	BRILLIANCE SEMICONDUCTOR
描述：	Ultra Low Power/Voltage CMOS SRAM 512K X 8 bit 超低功率/电压CMOS SRAM 512K ×8位静态存储器
文件：	总11页 (文件大小：337K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BS62UV4000 [BSI]

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