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BS62XV1024 [ETC]

Extremely Low Power/Voltage CMOS SRAM 128K X 8 bit(608.41 k) ; 极低的功率/电压CMOS SRAM 128K ×8位（ 608.41 K）
BS62XV1024
型号： BS62XV1024
厂家： ETC    ETC
描述：

Extremely Low Power/Voltage CMOS SRAM 128K X 8 bit(608.41 k)
极低的功率/电压CMOS SRAM 128K ×8位（ 608.41 K）

静态存储器
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Extremely Low Power/Voltage CMOS SRAM  
128K X 8 bit  
BSI  
BS62XV1024  
! DESCRIPTION  
! FEATURES  
The BS62XV1024 is a high performance, extremely low power CMOS  
Static Random Access Memory organized as 131,072 words by 8 bits  
and operates from an extremely low range of 1.2V to 2.4V supply  
voltage.  
• Extremely low operation voltage : 1.2V ~ 2.4V  
• Extremely low power consumption :  
Vcc = 1.5V 10mA (Max.) write current  
0.5mA (Max.) read current  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current of  
0.005uA and maximum access time of 250ns in 1.5V operation.  
Easy memory expansion is provided by an active LOW chip  
enable (CE1), an active HIGH chip enable (CE2), and active LOW  
output enable (OE) and three-state output drivers.  
0.005uA (Typ.) CMOS standby current  
Vcc = 2.2V 15mA (Max.) write current  
0.8mA (Max.) read current  
0.01uA (Typ.) CMOS standby current  
• High speed access time :  
-25  
250ns (Max.)  
The BS62XV1024 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS62XV1024 is available in the JEDEC standard 32 pin  
525mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.  
• Input levels are CMOS-compatible  
• Automatic power down when chip is deselected  
• Three state outputs  
• Fully static operation  
• Data retention supply voltage as low as 1.2V  
• Easy expansion with CE2, CE1, and OE options  
• All I/O pins are 3.3V tolerant  
! PRODUCT FAMILY  
POWER DISSIPATION  
STANDBY  
Operating  
PRODUCT  
FAMILY  
OPERATING  
TEMPERATURE  
Vcc  
RANGE  
SPEED  
(ns)  
(ICCSB1, Max)  
(ICC, Max)  
PKG TYPE  
Vcc=  
Vcc=  
1.5V  
Vcc=  
Vcc=  
1.5V  
2.2V  
2.2V  
BS62XV1024SC  
BS62XV1024TC  
BS62XV1024STC  
BS62XV1024SI  
BS62XV1024TI  
BS62XV1024STI  
SOP-32  
TSOP-32  
STSOP-32  
SOP-32  
TSOP-32  
STSOP-32  
+0 O C to +70O  
-40 O C to +85O  
C
C
1.2V ~ 2.4V  
1.2V ~ 2.4V  
250  
250  
0.3uA  
0.2uA  
0.8uA  
15mA  
10mA  
10mA  
1uA  
15mA  
! PIN CONFIGURATIONS  
! BLOCK DIAGRAM  
NC  
A16  
A14  
A12  
A7  
1
VCC  
A15  
CE2  
WE  
A13  
A8  
A9  
A11  
OE  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
2
3
4
A6  
A7  
A12  
A14  
A16  
A15  
A13  
A8  
5
6
7
8
Address  
Memory Array  
20  
1024  
A6  
A5  
A4  
Row  
Decoder  
Input  
BS62XV1024SC  
BS62XV1024SI  
1024 x 1024  
Buffer  
A3  
A2  
A1  
A0  
9
10  
11  
12  
13  
14  
15  
16  
A9  
A11  
DQ0  
DQ1  
DQ2  
GND  
1024  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
8
Data  
Input  
Buffer  
8
Column I/O  
Write Driver  
Sense Amp  
8
8
Data  
Output  
Buffer  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A11  
A9  
A8  
OE  
128  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
Column Decoder  
14  
A13  
WE  
CE2  
A15  
VCC  
NC  
A16  
A14  
A12  
A7  
BS62XV1024TC  
CE2  
CE1  
WE  
BS62XV1024STC  
BS62XV1024TI  
BS62XV1024STI  
Control  
Address Input Buffer  
9
10  
11  
12  
13  
14  
15  
16  
OE  
Vdd  
Gnd  
A5 A4 A3 A2 A1 A0 A10  
A6  
A5  
A4  
A1  
A2  
A3  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-1  
BSI  
BS62XV1024  
! PIN DESCRIPTIONS  
Name  
Function  
A0-A16 Address Input  
These 17 address input select one of the 131,072 x 8-bit words in the RAM  
CE1 Chip Enable 1 Input  
CE2 Chip Enable 2 Input  
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read  
from or write to the device. If either chip enable is not active, the device is deselected  
and is in a standby power mode. The DQ pins will be in the high impedance state  
when the device is deselected.  
WE Write Enable Input  
OE Output Enable Input  
The write enable input is active LOW and controls read and write operations. With the  
chip selected, when WE is HIGH and OE is LOW, output data will be present on the  
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the  
selected memory location.  
The output enable input is active LOW. If the output enable is active while the chip is  
selected and the write enable is inactive, data will be present on the DQ pins and they  
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.  
These 8 bi-directional ports are used to read data from or write data into the RAM.  
DQ0 – DQ7 Data Input/Output  
Ports  
Vcc  
Power Supply  
Ground  
Gnd  
! TRUTH TABLE  
MODE  
WE  
X
CE1  
H
CE2  
X
OE  
X
I/O OPERATION  
High Z  
Vcc CURRENT  
Not selected  
(Power Down)  
I
CCSB, ICCSB1  
X
X
L
X
Output Disabled  
Read  
H
L
H
H
L
High Z  
ICC  
ICC  
ICC  
OUT  
D
H
L
H
IN  
D
Write  
L
L
H
X
! ABSOLUTE MAXIMUM RATINGS(1)  
! OPERATING RANGE  
AMBIENT  
TEMPERATURE  
0 O C to +70 O  
SYMBOL  
PARAMETER  
Terminal Voltage with  
Respect to GND  
RATING  
UNITS  
RANGE  
Vcc  
-0.5 to +6.0  
-40 to +125  
-60 to +150  
1.0  
V
TERM  
V
Commercial  
Industrial  
C
1.2V ~ 2.4V  
1.2V ~ 2.4V  
Temperature Under Bias  
Storage Temperature  
Power Dissipation  
O C  
O C  
W
-40 O C to +70O  
C
BIAS  
STG  
T
T
P
T
! CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)  
DC Output Current  
20  
mA  
OUT  
I
SYMBOL  
PARAMETER  
CONDITIONS  
MAX.  
UNIT  
Input  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM  
RATINGS may cause permanent damage to the device. This is a  
stress rating only and functional operation of the device at these  
or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
reliability.  
CIN  
VIN=0V  
6
pF  
Capacitance  
Input/Output  
Capacitance  
CDQ  
VI/O=0V  
8
pF  
1. This parameter is guaranteed and not tested.  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-2  
BSI  
BS62XV1024  
! DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )  
PARAMETER  
MIN. TYP.(1) MAX.  
-0.5 -- 0.3Vcc  
UNITS  
PARAMETER  
TEST CONDITIONS  
NAME  
Guaranteed Input Low  
Voltage(2)  
IL  
V
V
Guaranteed Input High  
IH  
V
0.7Vcc  
--  
--  
--  
Vcc+0.2  
1
V
Voltage(2)  
IL  
IN  
I
Input Leakage Current  
Output Leakage Current  
Vcc = Max, V = 0V to Vcc  
uA  
IH  
IL,  
Vcc = Max, CE1= V , CE2= V or  
OE = V , V = 0V to Vcc  
OL  
I
--  
--  
1
uA  
IH  
I/O  
OL  
OL  
V
Output Low Voltage  
Output High Voltage  
Vcc = Max, I = 1mA  
--  
1.2  
--  
--  
--  
0.3  
--  
V
V
OH  
OH  
V
Vcc = Min, I = -0.5mA  
Vcc=1.5V  
Vcc=2.2V  
Vcc=1.5V  
Vcc=2.2V  
Vcc=1.5V  
Vcc=2.2V  
--  
10  
15  
0.5  
1
IL  
IH  
Operating Power Supply CE1 = V , or CE2 = V ,  
CC  
I
mA  
mA  
uA  
(3)  
DQ  
Current  
I
= 0mA, F = Fmax  
--  
--  
--  
--  
IH  
IL  
Standby Power Supply CE1 = V , or CE2 = V ,  
CCSB  
I
(3)  
DQ  
Current  
I
= 0mA, F = Fmax  
--  
--  
--  
0.005  
0.01  
0.2  
0.3  
CE1ꢀVcc-0.2V, CE2ꢁ0.2V,  
V ꢀVcc-0.2V or V ꢁ0.2V  
Power Down Supply  
Current  
CCSB1  
I
IN  
IN  
--  
1. Typical characteristics are at TA = 25oC.  
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.  
3. Fmax = 1/tRC  
.
! DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN.  
TYP.(1)  
MAX.  
UNITS  
CE1 ꢀ Vcc - 0.2V, CE2 ꢁ 0.2V,  
VIN ꢀ Vcc - 0.2V or VIN ꢁ 0.2V  
VDR  
Vcc for Data Retention  
1.2  
--  
--  
V
CE1 ꢀ Vcc - 0.2V, CE2 ꢁ 0.2V,  
VIN ꢀ Vcc - 0.2V or VIN ꢁ 0.2V  
ICCDR  
Data Retention Current  
--  
0
0.005  
0.1  
uA  
Chip Deselect to Data  
Retention Time  
tCDR  
tR  
--  
--  
--  
--  
ns  
ns  
See Retention Waveform  
(2)  
Operation Recovery Time  
TRC  
1. Vcc = 1.5V, TA = + 25OC  
2. tRC = Read Cycle Time  
! LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )  
Data Retention Mode  
DR ≥ 1.2V  
V
Vcc  
Vcc  
Vcc  
CE  
R
t
CDR  
t
CE ≥Vcc - 0.2V  
VIH  
VIH  
! LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )  
Data Retention Mode  
DR ≥ 1.2V  
V
Vcc  
Vcc  
Vcc  
R
t
CDR  
t
CE2  
0.2V  
≤
VIH  
VIH  
CE2  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-3  
BSI  
BS62XV1024  
! KEY TO SWITCHING WAVEFORMS  
! AC TEST CONDITIONS  
Input Pulse Levels  
Input Rise and Fall Times 5ns  
Input and Output  
Vcc/0V  
WAVEFORM  
INPUTS  
OUTPUTS  
MUST BE  
STEADY  
MUST BE  
STEADY  
Timing Reference Level  
0.5Vcc  
MAY CHANGE  
FROM H TO L  
WILL BE  
CHANGE  
FROM H TO L  
! AC TEST LOADS AND WAVEFORMS  
Ω
Ω
1000  
1000  
5PF  
MAY CHANGE  
FROM L TO H  
WILL BE  
CHANGE  
FROM L TO H  
1.5V  
1.5V  
OUTPUT  
OUTPUT  
,
DON T CARE:  
CHANGE :  
STATE  
UNKNOWN  
100PF  
ANY CHANGE  
PERMITTED  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
Ω
Ω
1500  
1500  
DOES NOT  
APPLY  
CENTER  
FIGURE 1A  
FIGURE 1B  
LINE IS HIGH  
IMPEDANCE  
”OFF ”STATE  
THEVENIN EQUIVALENT  
600  
Ω
OUTPUT  
0.9V  
ALL INPUT PULSES  
Vcc  
GND  
10%  
90% 90%  
10%  
→
→
←
← 5ns  
FIGURE 2  
! AC ELECTRICAL CHARACTERISTICS (over the operating range)  
READ CYCLE  
JEDEC  
PARAMETER  
NAME  
PARAMETER  
BS62XV1024-25  
MIN. TYP. MAX.  
DESCRIPTION  
UNIT  
NAME  
t
t
Read Cycle Time  
250  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
250  
250  
250  
150  
--  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
AVAX  
RC  
t
t
Address Access Time  
AVQV  
AA  
t
t
Chip Select Access Time  
(CE1)  
(CE2)  
--  
E1LQV  
ACS1  
t
t
Chip Select Access Time  
--  
E2HOV  
ACS2  
t
t
Output Enable to Output Valid  
Chip Select to Output Low Z  
Chip Select to Output Low Z  
Output Enable to Output in Low Z  
Chip Deselect to Output in High Z  
Chip Deselect to Output in High Z  
Output Disable to Output in High Z  
--  
GLQV  
OE  
t
t
(CE1)  
(CE2)  
15  
10  
10  
0
E1LQX  
CLZ1  
t
t
--  
E2HOX  
CLZ2  
t
t
--  
GLQX  
OLZ  
t
t
(CE1)  
(CE2)  
40  
40  
35  
E1HQZ  
CHZ1  
t
t
E2HQZ  
CHZ1  
t
t
0
--  
--  
ns  
ns  
GHQZ  
OHZ  
t
t
Output Disable to Output Address Change  
AXOX  
OH  
10  
--  
1. Typical characteristics are at Vcc = 1.5V, TA = 25oC.  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-4  
BSI  
BS62XV1024  
! SWITCHING WAVEFORMS (READ CYCLE)  
READ CYCLE1 (1,2,4)  
t
RC  
ADDRESS  
t
AA  
t
OH  
t
OH  
D OUT  
READ CYCLE2 (1,3,4)  
CE1  
ACS1  
ACS2  
t
t
CE2  
(5)  
CHZ  
t
(5)  
CLZ  
t
D OUT  
READ CYCLE3 (1,4)  
ADDRESS  
t
RC  
t
AA  
OE  
t
OH  
t
OE  
t
OLZ  
CE1  
(5)  
ACS1  
(5) t  
CLZ1  
t
t
OHZ  
(1,5)  
CHZ  
t
t
CE2  
ACS2  
t
(2,5)  
CHZ  
t
(5)  
CLZ2  
D OUT  
NOTES:  
1. WE is high for read Cycle.  
2. Device is continuously selected when CE1 = VIL and CE2= VIH.  
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.  
4. OE = VIL  
.
±
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.  
The parameter is guaranteed but not 100% tested.  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-5  
BSI  
BS62XV1024  
! AC ELECTRICAL CHARACTERISTICS (over the operating range)  
WRITE CYCLE  
JEDEC  
PARAMETER  
NAME  
PARAMETER  
BS62XV1024-25  
MIN. TYP. MAX.  
DESCRIPTION  
UNIT  
NAME  
t
t
Write Cycle Time  
AVAX  
WC  
250  
250  
0
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
t
t
Chip Select to End of Write  
Address Set up Time  
E1LWH  
CW  
t
t
AVWL  
AS  
--  
t
t
Address Valid to End of Write  
Write Pulse Width  
AVWH  
AW  
250  
150  
0
--  
t
t
WLWH  
WP  
--  
t
t
Write Recovery Time  
(CE1 , WE)  
(CE2)  
WHAX  
WR1  
--  
t
t
Write Recovery Time  
E2LAX  
WR2  
0
--  
t
t
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Disable to Output in High Z  
End of Write to Output Active  
WLOZ  
WHZ  
--  
40  
--  
t
t
DVWH  
DW  
100  
0
t
t
WHDX  
DH  
--  
t
t
GHOZ  
OHZ  
0
40  
--  
t
t
WHQX  
OW  
5
1. Typical characteristics are at Vcc = 1.5V, T  
A
= 25oC.  
! SWITCHING WAVEFORMS (WRITE CYCLE)  
WRITE CYCLE1 (1)  
t
WC  
ADDRESS  
OE  
(3)  
t
WR1  
(11)  
CW  
t
(5)  
(5)  
CE1  
CE2  
(11)  
t
t
CW  
t
WR2  
t
AW  
(3)  
WP  
(2)  
WE  
t
AS  
(4,10)  
OHZ  
t
D OUT  
t
DH  
t
DW  
D IN  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-6  
BSI  
BS62XV1024  
(1,6)  
WRITE CYCLE2  
t
WC  
ADDRESS  
(11)  
CW  
t
(5)  
(5)  
CE1  
CE2  
(11)  
t
CW  
t
WR2  
t
AW  
(3)  
t
WP  
(2)  
t
DH  
WE  
t AS  
(4,10)  
(7)  
(8)  
t WHZ  
D OUT  
t
DW  
(8)  
t
DH  
D IN  
NOTES:  
1. WE must be high during address transitions.  
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.  
All signals must be active to initiate a write and any one signal can terminate a write by going  
inactive. The data input setup and hold timing should be referenced to the second transition edge  
of the signal that terminates the write.  
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write  
cycle.  
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the  
outputs must not be applied.  
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low  
transitions or after the WE transition, output remain in a high impedance state.  
6. OE is continuously low (OE = VIL ).  
7. DOUT is the same phase of write data of this write cycle.  
8. DOUT is the read data of next address.  
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input  
signals of opposite phase to the outputs must not be applied to them.  
L
10. Transition is measured 500mV from steady state with C = 5pF as shown in Figure 1B. The  
±
parameter is guaranteed but not 100% tested.  
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-7  
BSI  
BS62XV1024  
! ORDERING INFORMATION  
BS62XV1024  
X X  
--  
Y
Y
SPEED  
25: 250ns  
GRADE  
C: +0oC ~ +70oC  
I: -40oC ~ +85oC  
PACKAGE  
S: SOP  
T: TSOP (8mm x 20mm)  
ST: Small TSOP (8mm x 13.4mm)  
! PACKAGE DIMENSIONS  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-8  
BSI  
BS62XV1024  
! PACKAGE DIMENSIONS (continued)  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-9  
BSI  
BS62XV1024  
This page is left blank intentionally.  
Revision 1.0  
March 2000  
R0201-BS62XV1024  
2-10  
Ultra Low Power/Voltage CMOS SRAM  
128K X 8 bit  
BSI  
BS62UV1024  
! DESCRIPTION  
! FEATURES  
The BS62UV1024 is a high performance, ultra low power CMOS  
Static Random Access Memory organized as 131,072 words by 8 bits  
and operates from a ultra low range of 1.8V to 3.6V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current of  
0.01uA and maximum access time of 150ns in 2V operation.  
Easy memory expansion is provided by an active LOW chip  
enable (CE1), an active HIGH chip enable (CE2), and active LOW  
output enable (OE) and three-state output drivers.  
The BS62UV1024 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS62UV1024 is available in the JEDEC standard 32 pin  
525mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.  
• Ultra low operation voltage : 1.8V ~ 3.6V  
• Ultra low power consumption :  
Vcc = 2.0V 15mA (Max.) write current  
0.8mA (Max.) read current  
0.01uA (Typ.) CMOS standby current  
Vcc = 3.3V 20mA (Max.) write current  
1mA (Max.) read current  
0.02uA (Typ.) CMOS standby current  
• High speed access time :  
-15 150ns (Max.)  
• Input levels are CMOS-compatible  
• Automatic power down when chip is deselected  
• Three state outputs  
• Fully static operation  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE2, CE1, and OE options  
• All I/O pins are 3.3V tolerant  
! PRODUCT FAMILY  
POWER DISSIPATION  
STANDBY  
Operating  
PRODUCT  
FAMILY  
OPERATING  
TEMPERATURE  
Vcc  
RANGE  
SPEED  
(ns)  
(ICCSB1, Max)  
(ICC, Max)  
PKG TYPE  
Vcc=  
Vcc=  
2.0V  
Vcc=  
Vcc=  
2.0V  
3.3V  
3.3V  
BS62UV1024SC  
BS62UV1024TC  
BS62UV1024STC  
BS62UV1024SI  
BS62UV1024TI  
BS62UV1024STI  
SOP-32  
TSOP-32  
STSOP-32  
SOP-32  
TSOP-32  
STSOP-32  
+0 O C to +70O  
-40 O C to +85O  
C
C
1.8V ~ 3.6V  
1.8V ~ 3.6V  
150  
150  
0.5uA  
0.3uA  
1uA  
20mA  
15mA  
15mA  
1.5uA  
20mA  
! PIN CONFIGURATIONS  
! BLOCK DIAGRAM  
NC  
A16  
A14  
A12  
A7  
1
VCC  
A15  
CE2  
WE  
A13  
A8  
A9  
A11  
OE  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
2
3
4
A6  
A7  
A12  
A14  
A16  
A15  
A13  
A8  
5
6
7
8
Address  
Memory Array  
20  
1024  
A6  
A5  
A4  
Row  
Decoder  
Input  
BS62UV1024SC  
BS62UV1024SI  
1024 x 1024  
Buffer  
A3  
A2  
A1  
A0  
9
10  
11  
12  
13  
14  
15  
16  
A9  
A11  
DQ0  
DQ1  
DQ2  
GND  
1024  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
8
Data  
Input  
Buffer  
8
Column I/O  
Write Driver  
Sense Amp  
8
8
Data  
Output  
Buffer  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A11  
A9  
A8  
OE  
128  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
Column Decoder  
14  
A13  
WE  
CE2  
A15  
VCC  
NC  
A16  
A14  
A12  
A7  
BS62UV1024TC  
CE2  
CE1  
WE  
BS62UV1024STC  
BS62UV1024TI  
BS62UV1024STI  
Control  
Address Input Buffer  
9
10  
11  
12  
13  
14  
15  
16  
OE  
Vdd  
Gnd  
A5 A4 A3 A2 A1 A0 A10  
A6  
A5  
A4  
A1  
A2  
A3  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-11  
BSI  
BS62UV1024  
! PIN DESCRIPTIONS  
Name  
Function  
A0-A16 Address Input  
These 17 address input select one of the 131,072 x 8-bit words in the RAM  
CE1 Chip Enable 1 Input  
CE2 Chip Enable 2 Input  
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read  
from or write to the device. If either chip enable is not active, the device is deselected  
and is in a standby power mode. The DQ pins will be in the high impedance state  
when the device is deselected.  
WE Write Enable Input  
OE Output Enable Input  
The write enable input is active LOW and controls read and write operations. With the  
chip selected, when WE is HIGH and OE is LOW, output data will be present on the  
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the  
selected memory location.  
The output enable input is active LOW. If the output enable is active while the chip is  
selected and the write enable is inactive, data will be present on the DQ pins and they  
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.  
These 8 bi-directional ports are used to read data from or write data into the RAM.  
DQ0 – DQ7 Data Input/Output  
Ports  
Vcc  
Power Supply  
Ground  
Gnd  
! TRUTH TABLE  
MODE  
WE  
X
CE1  
H
CE2  
X
OE  
X
I/O OPERATION  
High Z  
Vcc CURRENT  
Not selected  
(Power Down)  
I
CCSB, ICCSB1  
X
X
L
X
Output Disabled  
Read  
H
L
H
H
L
High Z  
ICC  
ICC  
ICC  
OUT  
D
H
L
H
IN  
D
Write  
L
L
H
X
! ABSOLUTE MAXIMUM RATINGS(1)  
! OPERATING RANGE  
AMBIENT  
TEMPERATURE  
SYMBOL  
PARAMETER  
Terminal Voltage with  
Respect to GND  
RATING  
UNITS  
RANGE  
Vcc  
-0.5 to +6.0  
-40 to +125  
-60 to +150  
1.0  
V
TERM  
V
Commercial  
Industrial  
0 O C to +70 O  
C
1.8V ~ 3.6V  
1.8V ~ 3.6V  
Temperature Under Bias  
Storage Temperature  
Power Dissipation  
O C  
O C  
W
-40 O C to +70 O  
C
BIAS  
STG  
T
T
P
T
! CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)  
DC Output Current  
20  
mA  
OUT  
I
SYMBOL  
PARAMETER  
CONDITIONS  
MAX.  
UNIT  
Input  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM  
RATINGS may cause permanent damage to the device. This is a  
stress rating only and functional operation of the device at these  
or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
reliability.  
CIN  
VIN=0V  
6
pF  
Capacitance  
Input/Output  
Capacitance  
CDQ  
VI/O=0V  
8
pF  
1. This parameter is guaranteed and not tested.  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-12  
BSI  
BS62UV1024  
! DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )  
PARAMETER  
MIN. TYP.(1) MAX.  
-0.5 -- 0.3Vcc  
UNITS  
PARAMETER  
TEST CONDITIONS  
NAME  
Guaranteed Input Low  
Voltage(2)  
IL  
V
V
Guaranteed Input High  
IH  
V
0.7Vcc  
--  
--  
--  
Vcc+0.2  
1
V
Voltage(2)  
IL  
IN  
I
Input Leakage Current  
Output Leakage Current  
Vcc = Max, V = 0V to Vcc  
uA  
IH  
IL,  
Vcc = Max, CE1= V , CE2= V or  
OE = V , V = 0V to Vcc  
OL  
I
--  
--  
1
uA  
IH  
I/O  
OL  
OL  
V
Output Low Voltage  
Output High Voltage  
Vcc = Max, I = 1mA  
--  
1.6  
--  
--  
--  
0.4  
--  
V
V
OH  
OH  
V
Vcc = Min, I = -0.5mA  
Vcc=2.0V  
Vcc=3.3V  
Vcc=2.0V  
Vcc=3.3V  
Vcc=2.0V  
Vcc=3.3V  
--  
15  
20  
0.5  
1
IL  
IH  
Operating Power Supply CE1 = V , or CE2 = V ,  
CC  
I
mA  
mA  
uA  
(3)  
DQ  
Current  
I
= 0mA, F = Fmax  
--  
--  
--  
--  
IH  
IL  
Standby Power Supply CE1 = V , or CE2 = V ,  
CCSB  
I
(3)  
DQ  
Current  
I
= 0mA, F = Fmax  
--  
--  
--  
0.01  
0.02  
0.3  
0.5  
CE1ꢀVcc-0.2V, CE2ꢁ0.2V,  
V ꢀVcc-0.2V or V ꢁ0.2V  
Power Down Supply  
Current  
CCSB1  
I
IN  
IN  
--  
1. Typical characteristics are at TA = 25oC.  
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.  
3. Fmax = 1/tRC  
.
! DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN.  
TYP.(1)  
MAX.  
UNITS  
CE1 ꢀ Vcc - 0.2V, CE2 ꢁ 0.2V,  
VIN ꢀ Vcc - 0.2V or VIN ꢁ 0.2V  
VDR  
Vcc for Data Retention  
1.5  
--  
--  
V
CE1 ꢀ Vcc - 0.2V, CE2 ꢁ 0.2V,  
VIN ꢀ Vcc - 0.2V or VIN ꢁ 0.2V  
ICCDR  
Data Retention Current  
--  
0
0.01  
0.2  
uA  
Chip Deselect to Data  
Retention Time  
tCDR  
tR  
--  
--  
--  
--  
ns  
ns  
See Retention Waveform  
(2)  
Operation Recovery Time  
TRC  
1. Vcc = 1.5V, TA = + 25OC  
2. tRC = Read Cycle Time  
! LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )  
Data Retention Mode  
DR ≥ 1.5V  
V
Vcc  
Vcc  
Vcc  
CE  
R
t
CDR  
t
CE ≥Vcc - 0.2V  
VIH  
VIH  
! LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )  
Data Retention Mode  
DR ≥ 1.5V  
V
Vcc  
Vcc  
Vcc  
R
t
CDR  
t
CE2  
0.2V  
≤
VIH  
VIH  
CE2  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-13  
BSI  
BS62UV1024  
! KEY TO SWITCHING WAVEFORMS  
! AC TEST CONDITIONS  
Input Pulse Levels  
Input Rise and Fall Times 5ns  
Input and Output  
Vcc/0V  
WAVEFORM  
INPUTS  
OUTPUTS  
MUST BE  
STEADY  
MUST BE  
STEADY  
Timing Reference Level  
0.5Vcc  
MAY CHANGE  
FROM H TO L  
WILL BE  
CHANGE  
FROM H TO L  
! AC TEST LOADS AND WAVEFORMS  
Ω
Ω
1333  
1333  
5PF  
MAY CHANGE  
FROM L TO H  
WILL BE  
CHANGE  
FROM L TO H  
2V  
2V  
OUTPUT  
OUTPUT  
,
DON T CARE:  
CHANGE :  
STATE  
UNKNOWN  
100PF  
ANY CHANGE  
PERMITTED  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
Ω
Ω
2000  
2000  
DOES NOT  
APPLY  
CENTER  
FIGURE 1A  
FIGURE 1B  
LINE IS HIGH  
IMPEDANCE  
”OFF ”STATE  
THEVENIN EQUIVALENT  
800  
Ω
OUTPUT  
1.2V  
ALL INPUT PULSES  
Vcc  
GND  
10%  
90% 90%  
10%  
→
→
←
← 5ns  
! AC ELECTRICAL CHARACTERISTICS (over the operating range)  
READ CYCLE  
JEDEC  
PARAMETER  
NAME  
PARAMETER  
BS62UV1024-15  
MIN. TYP. MAX.  
DESCRIPTION  
Read Cycle Time  
UNIT  
NAME  
tAVAX  
tRC  
150  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
150  
150  
150  
100  
--  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAVQV  
tAA  
Address Access Time  
tE1LQV  
tE2HOV  
tGLQV  
tE1LQX  
tE2HOX  
tGLQX  
tE1HQZ  
tE2HQZ  
tGHQZ  
tACS1  
tACS2  
tOE  
Chip Select Access Time  
(CE1)  
(CE2)  
--  
Chip Select Access Time  
--  
Output Enable to Output Valid  
Chip Select to Output Low Z  
Chip Select to Output Low Z  
Output Enable to Output in Low Z  
Chip Deselect to Output in High Z  
Chip Deselect to Output in High Z  
Output Disable to Output in High Z  
--  
tCLZ1  
tCLZ2  
tOLZ  
(CE1)  
(CE2)  
10  
10  
10  
0
--  
--  
tCHZ1  
tCHZ1  
tOHZ  
(CE1)  
(CE2)  
40  
40  
35  
0
0
--  
--  
ns  
ns  
tAXOX  
tOH  
Output Disable to Output Address Change  
10  
--  
1. Typical characteristics are at Vcc = 2.0V, TA = 25oC.  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-14  
BSI  
BS62UV1024  
! SWITCHING WAVEFORMS (READ CYCLE)  
READ CYCLE1 (1,2,4)  
t
RC  
ADDRESS  
t
AA  
t
OH  
t
OH  
D OUT  
READ CYCLE2 (1,3,4)  
CE1  
ACS1  
ACS2  
t
t
CE2  
(5)  
CHZ  
t
(5)  
CLZ  
t
D OUT  
READ CYCLE3 (1,4)  
ADDRESS  
t
RC  
t
AA  
OE  
t
OH  
t
OE  
t
OLZ  
CE1  
(5)  
ACS1  
(5) t  
CLZ1  
t
t
OHZ  
(1,5)  
CHZ  
t
t
CE2  
ACS2  
t
(2,5)  
CHZ  
t
(5)  
CLZ2  
D OUT  
NOTES:  
1. WE is high for read Cycle.  
2. Device is continuously selected when CE1 = VIL and CE2= VIH.  
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.  
4. OE = VIL  
.
±
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.  
The parameter is guaranteed but not 100% tested.  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-15  
BSI  
BS62UV1024  
! AC ELECTRICAL CHARACTERISTICS (over the operating range)  
WRITE CYCLE  
JEDEC  
PARAMETER  
NAME  
PARAMETER  
BS62UV1024-15  
MIN. TYP. MAX.  
DESCRIPTION  
Write Cycle Time  
UNIT  
NAME  
tAVAX  
tWC  
150  
150  
0
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tE1LWH  
tAVWL  
tAVWH  
tWLWH  
tWHAX  
tE2LAX  
tWLOZ  
tDVWH  
tWHDX  
tGHOZ  
tWHQX  
tCW  
tAS  
Chip Select to End of Write  
Address Set up Time  
--  
tAW  
Address Valid to End of Write  
Write Pulse Width  
150  
80  
0
--  
tWP  
tWR1  
tWR2  
tWHZ  
tDW  
tDH  
--  
Write Recovery Time  
(CE1 , WE)  
(CE2)  
--  
Write Recovery Time  
0
--  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Disable to Output in High Z  
End of Write to Output Active  
--  
40  
--  
50  
0
--  
tOHZ  
tOW  
0
40  
--  
5
1. Typical characteristics are at Vcc = 2.0V, T  
A
= 25oC.  
! SWITCHING WAVEFORMS (WRITE CYCLE)  
WRITE CYCLE1 (1)  
t
WC  
ADDRESS  
OE  
(3)  
t
WR1  
(11)  
CW  
t
(5)  
(5)  
CE1  
CE2  
(11)  
t
t
CW  
t
WR2  
t
AW  
(3)  
WP  
(2)  
WE  
t
AS  
(4,10)  
OHZ  
t
D OUT  
t
DH  
t
DW  
D IN  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-16  
BSI  
BS62UV1024  
(1,6)  
WRITE CYCLE2  
t
WC  
ADDRESS  
(11)  
CW  
t
(5)  
(5)  
CE1  
CE2  
(11)  
t
CW  
t
WR2  
t
AW  
(3)  
t
WP  
(2)  
t
DH  
WE  
t AS  
(4,10)  
(7)  
(8)  
t WHZ  
D OUT  
t
DW  
(8)  
t
DH  
D IN  
NOTES:  
1. WE must be high during address transitions.  
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.  
All signals must be active to initiate a write and any one signal can terminate a write by going  
inactive. The data input setup and hold timing should be referenced to the second transition edge  
of the signal that terminates the write.  
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write  
cycle.  
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the  
outputs must not be applied.  
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low  
transitions or after the WE transition, output remain in a high impedance state.  
6. OE is continuously low (OE = VIL ).  
7. DOUT is the same phase of write data of this write cycle.  
8. DOUT is the read data of next address.  
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input  
signals of opposite phase to the outputs must not be applied to them.  
L
10. Transition is measured 500mV from steady state with C = 5pF as shown in Figure 1B. The  
±
parameter is guaranteed but not 100% tested.  
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-17  
BSI  
BS62UV1024  
! ORDERING INFORMATION  
BS62UV1024  
X X  
--  
Y
Y
SPEED  
15: 150ns  
GRADE  
C: +0oC ~ +70oC  
I: -40oC ~ +85oC  
PACKAGE  
S: SOP  
T: TSOP (8mm x 20mm)  
ST: Small TSOP (8mm x 13.4mm)  
! PACKAGE DIMENSIONS  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-18  
BSI  
BS62UV1024  
! PACKAGE DIMENSIONS (continued)  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-19  
BSI  
BS62UV1024  
This page is left blank intentionally.  
Revision 1.0  
March 2000  
R0201-BS62UV1024  
2-20  
Very Low Power/Voltage CMOS SRAM  
128K X 8 bit  
BSI  
BS62LV1024  
! DESCRIPTION  
! FEATURES  
The BS62LV1024 is a high performance, very low power CMOS  
Static Random Access Memory organized as 131,072 words by 8 bits  
and operates from a wide range of 2.4V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current of  
0.02uA and maximum access time of 70ns in 3V operation.  
Easy memory expansion is provided by an active LOW chip  
enable (CE1), an active HIGH chip enable (CE2), and active LOW  
output enable (OE) and three-state output drivers.  
The BS62LV1024 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS62LV1024 is available in the JEDEC standard 32 pin  
525mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.  
• Wide Vcc operation voltage : 2.4V ~ 5.5V  
• Very low power consumption :  
Vcc = 3.0V 20mA (Max.) write current  
1mA (Max.) read current  
0.02uA (Typ.) CMOS standby current  
Vcc = 5.0V 45mA (Max.) write current  
2mA (Max.) read current  
0.6uA (Typ.) CMOS standby current  
• High speed access time :  
-70 70ns (Max.)  
• Input levels are CMOS-compatible  
• Automatic power down when chip is deselected  
• Three state outputs  
• Fully static operation  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE2, CE1, and OE options  
• All I/O pins are 5V tolerant  
! PRODUCT FAMILY  
POWER DISSIPATION  
STANDBY  
Operating  
PRODUCT  
FAMILY  
OPERATING  
TEMPERATURE  
Vcc  
RANGE  
SPEED  
(ns)  
(ICCSB1, Max)  
(ICC, Max)  
PKG TYPE  
Vcc=  
Vcc=  
3.0V  
Vcc=  
Vcc=  
3.0V  
5.0V  
5.0V  
BS62LV1024SC  
BS62LV1024TC  
BS62LV1024STC  
BS62LV1024SI  
BS62LV1024TI  
BS62LV1024STI  
SOP-32  
TSOP-32  
STSOP-32  
SOP-32  
TSOP-32  
STSOP-32  
+0 O C to +70O  
-40 O C to +85O  
C
C
2.4V ~ 5.5V  
2.4V ~ 5.5V  
70  
70  
3.0uA  
0.5uA  
1.5uA  
45mA  
20mA  
20mA  
5.0uA  
45mA  
! PIN CONFIGURATIONS  
! BLOCK DIAGRAM  
NC  
A16  
A14  
A12  
A7  
1
VCC  
A15  
CE2  
WE  
A13  
A8  
A9  
A11  
OE  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
2
3
4
A6  
A7  
A12  
A14  
A16  
A15  
A13  
A8  
5
6
7
8
Address  
Memory Array  
20  
1024  
A6  
A5  
A4  
Row  
Decoder  
Input  
BS62LV1024SC  
BS62LV1024SI  
1024 x 1024  
Buffer  
A3  
A2  
A1  
A0  
9
10  
11  
12  
13  
14  
15  
16  
A9  
A11  
DQ0  
DQ1  
DQ2  
GND  
1024  
DQ0  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
8
Data  
Input  
Buffer  
8
Column I/O  
Write Driver  
Sense Amp  
8
8
Data  
Output  
Buffer  
1
2
3
4
5
6
7
8
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
A11  
A9  
A8  
OE  
128  
A10  
CE1  
DQ7  
DQ6  
DQ5  
DQ4  
DQ3  
GND  
DQ2  
DQ1  
DQ0  
A0  
Column Decoder  
14  
A13  
WE  
CE2  
A15  
VCC  
NC  
A16  
A14  
A12  
A7  
BS62LV1024TC  
CE2  
CE1  
WE  
BS62LV1024STC  
BS62LV1024TI  
BS62LV1024STI  
Control  
Address Input Buffer  
9
10  
11  
12  
13  
14  
15  
16  
OE  
Vdd  
Gnd  
A5 A4 A3 A2 A1 A0 A10  
A6  
A5  
A4  
A1  
A2  
A3  
Brilliance Semiconductor Inc. reserves the right to modify document contents without notice.  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-21  
BSI  
BS62LV1024  
! PIN DESCRIPTIONS  
Name  
Function  
A0-A16 Address Input  
These 17 address input select one of the 131,072 x 8-bit words in the RAM  
CE1 Chip Enable 1 Input  
CE2 Chip Enable 2 Input  
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active to read  
from or write to the device. If either chip enable is not active, the device is deselected  
and is in a standby power mode. The DQ pins will be in the high impedance state  
when the device is deselected.  
WE Write Enable Input  
OE Output Enable Input  
The write enable input is active LOW and controls read and write operations. With the  
chip selected, when WE is HIGH and OE is LOW, output data will be present on the  
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the  
selected memory location.  
The output enable input is active LOW. If the output enable is active while the chip is  
selected and the write enable is inactive, data will be present on the DQ pins and they  
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.  
These 8 bi-directional ports are used to read data from or write data into the RAM.  
DQ0 – DQ7 Data Input/Output  
Ports  
Vcc  
Power Supply  
Ground  
Gnd  
! TRUTH TABLE  
MODE  
WE  
X
CE1  
H
CE2  
X
OE  
X
I/O OPERATION  
High Z  
Vcc CURRENT  
Not selected  
(Power Down)  
I
CCSB, ICCSB1  
X
X
L
X
Output Disabled  
Read  
H
L
H
H
L
High Z  
ICC  
ICC  
ICC  
OUT  
D
H
L
H
IN  
D
Write  
L
L
H
X
! ABSOLUTE MAXIMUM RATINGS(1)  
! OPERATING RANGE  
AMBIENT  
TEMPERATURE  
0 O C to +70 O  
SYMBOL  
PARAMETER  
Terminal Voltage with  
Respect to GND  
RATING  
UNITS  
RANGE  
Vcc  
-0.5 to +6.0  
-40 to +125  
-60 to +150  
1.0  
V
TERM  
V
Commercial  
Industrial  
C
2.4V ~ 5.5V  
2.4V ~ 5.5V  
Temperature Under Bias  
Storage Temperature  
Power Dissipation  
O C  
O C  
W
-40 O C to +70O  
C
BIAS  
STG  
T
T
P
T
! CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)  
DC Output Current  
20  
mA  
OUT  
I
SYMBOL  
PARAMETER  
CONDITIONS  
MAX.  
UNIT  
Input  
1. Stresses greater than those listed under ABSOLUTE MAXIMUM  
RATINGS may cause permanent damage to the device. This is a  
stress rating only and functional operation of the device at these  
or any other conditions above those indicated in the operational  
sections of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
reliability.  
CIN  
VIN=0V  
6
pF  
Capacitance  
Input/Output  
Capacitance  
CDQ  
VI/O=0V  
8
pF  
1. This parameter is guaranteed and not tested.  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-22  
BSI  
BS62LV1024  
! DC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC )  
PARAMETER  
MIN. TYP.(1) MAX.  
-0.5 -- 0.3Vcc  
UNITS  
PARAMETER  
TEST CONDITIONS  
NAME  
Guaranteed Input Low  
Voltage(2)  
IL  
V
V
Guaranteed Input High  
IH  
V
0.7Vcc  
--  
--  
--  
Vcc+0.2  
1
V
Voltage(2)  
IL  
IN  
I
Input Leakage Current  
Output Leakage Current  
Vcc = Max, V = 0V to Vcc  
uA  
IH  
IL,  
Vcc = Max, CE1= V , CE2= V or  
OE = V , V = 0V to Vcc  
OL  
I
--  
--  
1
uA  
IH  
I/O  
OL  
OL  
V
Output Low Voltage  
Output High Voltage  
Vcc = Max, I = 2mA  
--  
2.4  
--  
--  
--  
0.4  
--  
V
V
OH  
OH  
V
Vcc = Min, I = -1mA  
Vcc=3.0V  
Vcc=5.0V  
Vcc=3.0V  
Vcc=5.0V  
Vcc=3.0V  
Vcc=5.0V  
--  
20  
45  
1
IL  
IH  
Operating Power Supply CE1 = V , or CE2 = V ,  
CC  
I
mA  
mA  
uA  
(3)  
DQ  
Current  
I
= 0mA, F = Fmax  
--  
--  
--  
--  
IH  
IL  
Standby Power Supply CE1 = V , or CE2 = V ,  
CCSB  
I
(3)  
DQ  
Current  
I
= 0mA, F = Fmax  
--  
--  
2
--  
0.02  
0.6  
0.5  
3
CE1ꢀVcc-0.2V, CE2ꢁ0.2V,  
V ꢀVcc-0.2V or V ꢁ0.2V  
Power Down Supply  
Current  
CCSB1  
I
IN  
IN  
--  
1. Typical characteristics are at TA = 25oC.  
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.  
3. Fmax = 1/tRC  
.
! DATA RETENTION CHARACTERISTICS ( TA = 0 to + 70oC )  
SYMBOL  
PARAMETER  
TEST CONDITIONS  
MIN.  
TYP.(1)  
MAX.  
UNITS  
CE1 ꢀ Vcc - 0.2V, CE2 ꢁ 0.2V,  
VIN ꢀ Vcc - 0.2V or VIN ꢁ 0.2V  
VDR  
Vcc for Data Retention  
1.5  
--  
--  
V
CE1 ꢀ Vcc - 0.2V, CE2 ꢁ 0.2V,  
VIN ꢀ Vcc - 0.2V or VIN ꢁ 0.2V  
ICCDR  
Data Retention Current  
--  
0
0.02  
0.3  
uA  
Chip Deselect to Data  
Retention Time  
tCDR  
tR  
--  
--  
--  
--  
ns  
ns  
See Retention Waveform  
(2)  
Operation Recovery Time  
TRC  
1. Vcc = 1.5V, TA = + 25OC  
2. tRC = Read Cycle Time  
! LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )  
Data Retention Mode  
DR ≥ 1.5V  
V
Vcc  
Vcc  
Vcc  
CE  
R
t
CDR  
t
CE ≥Vcc - 0.2V  
VIH  
VIH  
! LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )  
Data Retention Mode  
DR ≥ 1.5V  
V
Vcc  
Vcc  
Vcc  
R
t
CDR  
t
CE2  
0.2V  
≤
VIH  
VIH  
CE2  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-23  
BSI  
BS62LV1024  
! KEY TO SWITCHING WAVEFORMS  
! AC TEST CONDITIONS  
Input Pulse Levels  
Input Rise and Fall Times 5ns  
Input and Output  
Vcc/0V  
WAVEFORM  
INPUTS  
OUTPUTS  
MUST BE  
STEADY  
MUST BE  
STEADY  
Timing Reference Level  
0.5Vcc  
MAY CHANGE  
FROM H TO L  
WILL BE  
CHANGE  
FROM H TO L  
! AC TEST LOADS AND WAVEFORMS  
Ω
Ω
1269  
1269  
5PF  
MAY CHANGE  
FROM L TO H  
WILL BE  
CHANGE  
FROM L TO H  
3.3V  
3.3V  
OUTPUT  
OUTPUT  
,
DON T CARE:  
CHANGE :  
STATE  
UNKNOWN  
100PF  
ANY CHANGE  
PERMITTED  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
Ω
Ω
1404  
1404  
DOES NOT  
APPLY  
CENTER  
FIGURE 1A  
FIGURE 1B  
LINE IS HIGH  
IMPEDANCE  
”OFF ”STATE  
THEVENIN EQUIVALENT  
667  
Ω
OUTPUT  
1.73V  
ALL INPUT PULSES  
Vcc  
GND  
10%  
90% 90%  
10%  
→
→
←
← 5ns  
FIGURE 2  
! AC ELECTRICAL CHARACTERISTICS (over the operating range)  
READ CYCLE  
JEDEC  
PARAMETER  
NAME  
PARAMETER  
BS62LV1024-70  
MIN. TYP. MAX.  
DESCRIPTION  
Read Cycle Time  
UNIT  
NAME  
tAVAX  
tRC  
70  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
70  
70  
70  
50  
--  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAVQV  
tAA  
Address Access Time  
tE1LQV  
tE2HOV  
tGLQV  
tE1LQX  
tE2HOX  
tGLQX  
tE1HQZ  
tE2HQZ  
tGHQZ  
tACS1  
tACS2  
tOE  
Chip Select Access Time  
(CE1)  
(CE2)  
--  
Chip Select Access Time  
--  
Output Enable to Output Valid  
Chip Select to Output Low Z  
Chip Select to Output Low Z  
Output Enable to Output in Low Z  
Chip Deselect to Output in High Z  
Chip Deselect to Output in High Z  
Output Disable to Output in High Z  
--  
tCLZ1  
tCLZ2  
tOLZ  
(CE1)  
(CE2)  
10  
10  
10  
0
--  
--  
tCHZ1  
tCHZ1  
tOHZ  
(CE1)  
(CE2)  
40  
40  
35  
0
0
--  
--  
ns  
ns  
tAXOX  
tOH  
Output Disable to Output Address Change  
10  
--  
1. Typical characteristics are at Vcc = 3.3V, TA = 25oC.  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-24  
BSI  
BS62LV1024  
! SWITCHING WAVEFORMS (READ CYCLE)  
READ CYCLE1 (1,2,4)  
t
RC  
ADDRESS  
t
AA  
t
OH  
t
OH  
D OUT  
READ CYCLE2 (1,3,4)  
CE1  
ACS1  
ACS2  
t
t
CE2  
(5)  
CHZ  
t
(5)  
CLZ  
t
D OUT  
READ CYCLE3 (1,4)  
ADDRESS  
t
RC  
t
AA  
OE  
t
OH  
t
OE  
t
OLZ  
CE1  
(5)  
ACS1  
(5) t  
CLZ1  
t
t
OHZ  
(1,5)  
CHZ  
t
t
CE2  
ACS2  
t
(2,5)  
CHZ  
t
(5)  
CLZ2  
D OUT  
NOTES:  
1. WE is high for read Cycle.  
2. Device is continuously selected when CE1 = VIL and CE2= VIH.  
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.  
4. OE = VIL  
.
±
5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B.  
The parameter is guaranteed but not 100% tested.  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-25  
BSI  
BS62LV1024  
! AC ELECTRICAL CHARACTERISTICS (over the operating range)  
WRITE CYCLE  
JEDEC  
PARAMETER  
NAME  
PARAMETER  
BS62LV1024-70  
MIN. TYP. MAX.  
DESCRIPTION  
Write Cycle Time  
UNIT  
NAME  
tAVAX  
tWC  
70  
70  
0
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
--  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tE1LWH  
tAVWL  
tAVWH  
tWLWH  
tWHAX  
tE2LAX  
tWLOZ  
tDVWH  
tWHDX  
tGHOZ  
tWHQX  
tCW  
tAS  
Chip Select to End of Write  
Address Set up Time  
--  
tAW  
Address Valid to End of Write  
Write Pulse Width  
70  
50  
0
--  
tWP  
tWR1  
tWR2  
tWHZ  
tDW  
tDH  
--  
Write Recovery Time  
(CE1 , WE)  
(CE2)  
--  
Write Recovery Time  
0
--  
Write to Output in High Z  
Data to Write Time Overlap  
Data Hold from Write Time  
Output Disable to Output in High Z  
End of Write to Output Active  
0
30  
--  
30  
0
--  
tOHZ  
tOW  
0
30  
--  
5
1. Typical characteristics are at Vcc = 3.3V, T  
A
= 25oC.  
! SWITCHING WAVEFORMS (WRITE CYCLE)  
WRITE CYCLE1 (1)  
t
WC  
ADDRESS  
OE  
(3)  
t
WR1  
(11)  
CW  
t
(5)  
(5)  
CE1  
CE2  
(11)  
t
t
CW  
t
WR2  
t
AW  
(3)  
WP  
(2)  
WE  
t
AS  
(4,10)  
OHZ  
t
D OUT  
t
DH  
t
DW  
D IN  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-26  
BSI  
BS62LV1024  
(1,6)  
WRITE CYCLE2  
t
WC  
ADDRESS  
(11)  
CW  
t
(5)  
(5)  
CE1  
CE2  
(11)  
t
CW  
t
WR2  
t
AW  
(3)  
t
WP  
(2)  
t
DH  
WE  
t AS  
(4,10)  
(7)  
(8)  
t WHZ  
D OUT  
t
DW  
(8)  
t
DH  
D IN  
NOTES:  
1. WE must be high during address transitions.  
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.  
All signals must be active to initiate a write and any one signal can terminate a write by going  
inactive. The data input setup and hold timing should be referenced to the second transition edge  
of the signal that terminates the write.  
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write  
cycle.  
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the  
outputs must not be applied.  
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low  
transitions or after the WE transition, output remain in a high impedance state.  
6. OE is continuously low (OE = VIL ).  
7. DOUT is the same phase of write data of this write cycle.  
8. DOUT is the read data of next address.  
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input  
signals of opposite phase to the outputs must not be applied to them.  
L
10. Transition is measured 500mV from steady state with C = 5pF as shown in Figure 1B. The  
±
parameter is guaranteed but not 100% tested.  
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-27  
BSI  
BS62LV1024  
! ORDERING INFORMATION  
BS62LV1024  
X X  
--  
Y
Y
SPEED  
70: 70ns  
GRADE  
C: +0oC ~ +70oC  
I: -40oC ~ +85oC  
PACKAGE  
S: SOP  
T: TSOP (8mm x 20mm)  
ST: Small TSOP (8mm x 13.4mm)  
! PACKAGE DIMENSIONS  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-28  
BSI  
BS62LV1024  
! PACKAGE DIMENSIONS (continued)  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-29  
BSI  
BS62LV1024  
This page is left blank intentionally.  
Revision 1.0  
March 2000  
R0201-BS62LV1024  
2-30  

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