CDK1306CTQ32 [CADEKA]
10-bit, 40 MSPS 160mW A/D Converter; 10位， 40 MSPS 160MW A / D转换器
| 型号： | CDK1306CTQ32 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 10-bit, 40 MSPS 160mW A/D Converter |
| 文件： | 总11页 (文件大小：1296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
CDK1306
10-bit, 40 MSPS 160mW A/D Converter
f e a t u r e s
General Description
nꢀ
40 MSPS converter
The CDK1306 is a 10-bit, low power analog-to-digital converter capable
of minimum word rates of 40 MSPS. The on-chip track-and-hold function
assures very good dynamic performance without the need for external
components. The input drive requirements are minimized due to the CDK1306
low input capacitance of only 5pF.
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
160mW power dissipation
On-chip track-and-hold
Single +5V power supply
TTL/CMOS outputs
5pF input capacitance
Tri-state output buffers
Power dissipation is extremely low at only 160mW typical at 40 MSPS with
a power supply of +5.0V. The digital outputs are +3V or +5V, and are user
selectable. The CDK1306 is pin-compatible with an entire family of 10-bit,
CMOS converters (CDK1304/05/06), which simplifies upgrades. The CDK1306
hasincorporatedproprietarycircuitdesign*andCMOSprocessingtechnologies
to achieve its advanced performance. Inputs and outputs are TTL/CMOS-
compatible to interface with TTL/CMOS logic systems. Output data format is
straight binary.
High ESD protection: 3,500V minimum
Selectable +3V or +5V logic I/O
a p p l i c a t i o n s
nꢀ
All high-speed applications where low
power dissipation is required
nꢀ
Video imaging
nꢀ
Medical imaging
nꢀ
Radar receivers
The CDK1306 is available in 28-lead SOIC and 32-lead small (7mm square)
TQFP packages over the commercial temperature range.
nꢀ
IR imaging
nꢀ
Digital communications
Block Diagram
Ordering Information
Part Number
Package
SOIC-28
SOIC-28
TQFP-32
TQFP-32
Pb-Free
Yes
RoHS Compliant
Operating Temperature Range Packaging Method
CDK1306CSO28
CDK1306CSO28_Q
CDK1306CTQ32
CDK1306CTQ32_Q
Yes
No
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Rail
Rail
Rail
Rail
No
Yes
Yes
No
No
Moisture sensitivity level for SOIC-28 is MSL-1 and TQFP is MSL-3.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Pin Configuration
SOIC-28
TQFP-32
CDK1306
CDK1306
Pin Assignments
SOIC-28
TQFP-32
Pin Name
Description
1,8
2
3,4,28,29
AGND
VRHF
VRHS
VRLS
VRLF
VCAL
VIN
Analog Ground
30
31
32
1
Reference High Force
Reference High Sense
Reference Low Sense
Reference Low Force
Calibration Reference
Analog Input
3
5
6
9
5
7
2
10
11
12
13
15
6,7
8,9
10,11
12
14
AVDD
DVDD
DGND
CLK
Analog VDD
Digital VDD
Digital Ground
Input Clock ƒCLK = FS (TTL)
Output Enable
EN
16-20,
23-27
15-19,
22-26
D0-D9
Tri-State Data Output, (D0 = LSB)
28
14
22
21
4
27
13
21
20
–
D10
DAV
Tri-State Output Overrange
Data Valid Output
OVDD
OGND
N/C
Digital Output Supply
Digital Output Ground
No Connect
©2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
Max
Unit
Supply Voltages
AVDD
+6
+6
V
V
DVDD
Input Voltages
Analog input
VRef
-0.5
0
AV
+0.5
V
V
DD
AV
DD
CLK input
V
V
DD
AVDD – DVDD
AGND – DGND
Digital Outputs
-100
-100
100
100
10
mV
mV
mA
Reliability Information
Parameter
Min
Typ
Typ
Max
Unit
Storage Temperature Range
-65
+150
°C
Recommended Operating Conditions
Parameter
Min
0
Max
Unit
Operating Temperature Range
+70
+175
+300
°C
°C
°C
Junction Temperature Range
Lead Temperature (soldering 10 seconds)
©2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics
(T = T to T , AV = DV = OV = +5V, V = 0 to 4V, ƒ = 40 MSPS, V
= 4V, V
= 0V; unless otherwise noted)
Min
A
Max
DD
DD
DD
IN
clk
RHS
RLS
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Resolution
10
bits
DC Performance
DLE
ILE
Differential Linearity Error(1)
Integral Linearity Error(1)
No Missing Codes
-0.5
-1.0
+0.5
+1.0
LSB
LSB
Guaranteed
Analog Input
Input Voltage Range(1)
Input Resistance(2)
Input Capacitance
Input Bandwidth
Gain Error
VRLS
50
VRHS
V
kΩ
5
pF
Small Signal
Small Signal
250
MHz
LSB
LSB
±2.0
±2.0
Offset Error
Reference Input
Resistance(1)
200
400
150
600
Ω
Bandwidth
MHz
(2)
VRLS
0
2.0
V
V
(2)
VRHS
3.0
AVDD
VRHS –VRLS
4.0
90
75
V
Voltage Range
Δ (VRHF –VRHS
)
mV
mV
Δ (VRLS –VRLF
)
Reference Settling Time
VRHS
VRLS
15
20
CLK Cycle
CLK Cycle
Conversion Characteristics
Maximum Conversion Rate(1)
40
2
MHz
MHz
Minimum Conversion Rate(2)
Pipeline Delay (Latency)(2)
Aperture Delay Time
12
CLK Cycle
ns
4.0
15
Aperture Jitter Time
pspp
Dynamic Performance
ƒIN = 3.58MHz
ƒIN = 10.3MHz
ƒIN = 3.58MHz(1)
ƒIN = 10.3MHz(1)
ƒIN = 3.58MHz(1)
9 distortion bins from 1024 pt FFT
ƒIN = 10.3MHz(1)
9 distortion bins from 1024 pt FFT
ƒIN = 3.58MHz(1)
9.2
8.8
58
Bits
Bits
dB
ENOB
SNR
Effective Number of Bits
56
55
Signal-to-Noise Ratio w/o Harmonics
Total Harmonic Distortion
57
dB
,
61
56
63
58
dB
dB
THD
,
54
53
57
55
dB
dB
dB
deg
%
SINAD
SFDR
Signal-to-Noise and Distortion
ƒIN = 10.3MHz(1)
Spurious Free Dynamic Range
Differential Phase
ƒIN = 1MHz
64
±0.3
±0.3
Differential Gain
nꢀꢅꢄꢈ:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Electrical Characteristics
(T = T to T , AV = DV = OV = +5V, V = 0 to 4V, ƒ = 40 MSPS, V
= 4V, V
= 0V; unless otherwise noted)
Min
A
Max
DD
DD
DD
IN
clk
RHS
RLS
symbꢀꢁ
pꢂꢃꢂmꢄꢅꢄꢃ
cꢀꢆdꢇꢅꢇꢀꢆꢈ
Mꢇꢆ
tyꢉ
Mꢂx
uꢆꢇꢅꢈ
Digital Inputs
Logic “1“ Voltage(1)
Logic “0“ Voltage(1)
Maximum Input Current Low(1)
2.0
V
0.8
+10
+10
V
-10
-10
μA
μA
pF
Maximum Input Current High(1)
Input Capacitance
+5
Digital Outputs
Logic “1“ Voltage(1)
Logic “0“ Voltage(1)
Rise Time
IOH = 0.5mA
IOL = 1.6mA
15pF load
3.5
V
0.4
V
TR
TF
10
10
10
22
ns
ns
ns
ns
Fall Time
15pF load
20pF load, TA = 25°C
50pF load over temp
Output Enable to Data Output Delay
Power Supply Requirements
OVDD
3.0
5.0
5.25
5.25
22
V
V
Digital Voltage Supply(2)
DVDD
AVDD
AIDD
DIDD
4.75
4.75
5.0
5.0
14
V
mA
mA
mW
Digital Voltage Current(1)
Power Dissipation(1)
18
23
160
225
nꢀꢅꢄꢈ:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
iꢆꢅꢄgꢃꢂꢁ lꢇꢆꢄꢂꢃꢇꢅy eꢃꢃꢀꢃ (ile)
Specification Definitions
Linearity error refers to the deviation of each individual
code (normalized) from a straight line drawn from –FS
through +FS. The deviation is measured from the edge of
each particular code to the true straight line.
aꢉꢄꢃꢅꢊꢃꢄ Dꢄꢁꢂy
Aperture delay represents the point in time, relative to
the rising edge of the CLOCK input, that the analog input
is sampled.
oꢊꢅꢉꢊꢅ Dꢄꢁꢂy
aꢉꢄꢃꢅꢊꢃꢄ Jꢇꢅꢅꢄꢃ
Time between the clock’s triggering edge and output data
valid.
The variations in aperture delay for successive samples.
Dꢇꢋꢋꢄꢃꢄꢆꢅꢇꢂꢁ Gꢂꢇꢆ (DG)
ovꢄꢃvꢀꢁꢅꢂgꢄ rꢄꢌꢀvꢄꢃy tꢇmꢄ
A signal consisting of a sine wave superimposed on vari-
ous DC levels is applied to the input. Differential gain is
the maximum variation in the sampled sine wave ampli-
tudes at these DC levels.
The time required for the ADC to recover to full accuracy
after an analog input signal 125% of full scale is reduced
to 50% of the full-scale value.
sꢇgꢆꢂꢁ-tꢀ-nꢀꢇꢈꢄ rꢂꢅꢇꢀ (snr)
Dꢇꢋꢋꢄꢃꢄꢆꢅꢇꢂꢁ phꢂꢈꢄ (Dp)
The ratio of the fundamental sinusoid power to the total
noise power. Harmonics are excluded.
A signal consisting of a sine wave superimposed on vari-
ous DC levels is applied to the input. Differential phase is
the maximum variation in the sampled sine wave phases
at these DC levels.
sꢇgꢆꢂꢁ-tꢀ-nꢀꢇꢈꢄ aꢆd Dꢇꢈꢅꢀꢃꢅꢇꢀꢆ (sinaD)
The ratio of the fundamental sinusoid power to the total
noise and distortion power.
eꢋꢋꢄꢌꢅꢇvꢄ nꢊmbꢄꢃ oꢋ Bꢇꢅꢈ (enoB)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
tꢀꢅꢂꢁ Hꢂꢃmꢀꢆꢇꢌ Dꢇꢈꢅꢀꢃꢅꢇꢀꢆ (tHD)
The ratio of the total power of the first 9 harmonics to the
power of the measured sinusoidal signal.
N = SINAD – 1.76
6.02
iꢆꢉꢊꢅ Bꢂꢆdwꢇdꢅh
sꢉꢊꢃꢇꢀꢊꢈ fꢃꢄꢄ Dyꢆꢂmꢇꢌ rꢂꢆgꢄ (sfDr)
Small signal (50mV) bandwidth (3dB) of analog input stage.
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
Dꢇꢋꢋꢄꢃꢄꢆꢅꢇꢂꢁ lꢇꢆꢄꢂꢃꢇꢅy eꢃꢃꢀꢃ (Dle)
Error in the width of each code from its theoretical value.
N
(Theoretical = V /2 )
FS
Figure 1. Timing Diagram 1
©2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Table 1. Timing Parameters
Dꢄꢈꢌꢃꢇꢉꢅꢇꢀꢆ
Conversion Time
CLK Period
sym Mꢇꢆ tyꢉ Mꢂx uꢆꢇꢅꢈ
tC
tCLK
40
ns
ns
%
%
ns
tCLK
tCH
tCL
CLK High Duty Cycle
CLK Low Duty Cycle
40
50
50
17
60
60
40
CLK to Output Delay
(15pF load)
tOD
CLK to DAV
tS
10
ns
Figure 2. Timing Diagram 2
CDK1306
Figure 3. Typical Interface Circuit Diagram
©2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
n
n
ꢀ
Since only 16 comparators are used, a huge power
savings is realized.
Typical Interface Circuit
Very few external components are required to achieve
the stated device performance. Figure 3 shows the typical
interface requirements when using the CDK1306 in normal
circuit operation. The following sections provide
descriptions of the major functions and outline critical
performance criteria to consider for achieving the optimal
device performance.
ꢀ
The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparator’s
response to a reference zero.
n
ꢀ
The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also done
with a closed loop system. Multiple samples of the gain
error are integrated to produce a calibration voltage for
each ADC section.
Power Supplies And Grounding
Cadekasuggeststhatboththedigitalandtheanalogsupply
voltages on the CDK1306 be derived from a single analog
supply as shown in Figure 3. A separate digital supply
should be used for all interface circuitry. Cadeka suggests
using this power supply configuration to prevent a pos-
sible latch-up condition on powerup.
n
ꢀ
Capacitive displacement currents, which can induce
sampling error, are minimized since only one comparator
samples the input during a clock cycle.
n
ꢀ
The total input capacitance is very low since sections of
theconverterthatarenotsamplingthesignalareisolated
from the input by transmission gates.
Operating Description
The general architecture for the CMOS ADC is shown in the
Block Diagram. The design contains 16 identical successive
approximation ADC sections, all operating in parallel, a 16-
phase clock generator, an 11-bit 16:1 digital output multi-
plexer, correction logic, and a voltage reference generator
that provides common reference levels for each ADC section.
Voltage Reference
The CDK1306 requires the use of a single external volt-
age reference for driving the high side of the reference
ladder. It must be within the range of 3V to 5V. The lower
side of the ladder is typically tied to AGND (0.0V), but
can be run up to 2.0V with a second reference. The analog
input voltage range will track the total voltage difference
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
shown in Table 2.
measured between the ladder sense lines, V
and V
.
RHS
RLS
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations.
By using the configuration shown in Figure 4, offset and
gain errors of less than ±2 LSB can be obtained.
Table 2. Clock Cycles
cꢁꢀꢌk
oꢉꢄꢃꢂꢅꢇꢀꢆ
Reference zero sampling
1
2
In cases where wider variations in offset and gain can
Auto-zero comparison
Auto-calibrate comparison
Input sample
be tolerated, V
can be tied directly to V , and AGND
RHF
REF
3
can be tied directly to V
as shown in Figure 5. Decouple
RLF
4
force and sense lines to AGND with a 0.01μF capacitor
(chip cap preferred) to minimize high-frequency noise
injection.
5-15
16
11-bit SAR conversion
Data transfer
If this simplified configuration is used, the following con-
siderations should be taken into account. The reference
ladder circuit shown in Figure 5 is a simplified representa-
tion of the actual reference ladder with force and sense
taps shown. Due to the actual internal structure of the
The 16-phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADC sections are shifted by one clock cycle so that the an-
alog input is sampled on every cycle of the input clock by
exactly one ADC section. After 16 clock periods, the tim-
ing cycle repeats. The latency from analog input sample
to the corresponding digital output is 12 clock cycles.
ladder, the voltage drop from V
lent to the voltage drop from V
to V
to V
is not equiva-
RHS
RHF
.
RLF
RLS
©2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
a specific case. V
of 4.0V is applied to V , and V
RHF RLF
REF
is tied to AGND. A 90mV drop is seen at V
(= 3.91V),
RHS
and a 75mV increase is seen at V
(= 0.075V).
RLS
Analog Input
V
V
is the analog input. The input voltage range is from
IN
to V
(typically 4.0V) and will scale proportionally
RLS
RHS
with respect to the voltage reference. (See Voltage Refer-
ence section.)
The drive requirements for the analog inputs are very
minimal when compared to most other converters due to
the CDK1306 extremely low input capacitance of only 5pF
and very high input resistance of 50kΩ.
The analog input should be protected through a series
resistor and diode clamping circuit as shown in Figure 6.
Figure 4. Ladder Force/Sense Circuit
Figure 6. Recommended Input Protection Circuit
Calibration
The CDK1306 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and
offset errors are continually adjusted to 10-bit accuracy
during device operation. This process is completely trans-
parent to the user.
Upon powerup, the CDK1306 begins its calibration
algorithm. In order to achieve the calibration accuracy
required, the offset and gain adjustment step size is a
fraction of a 10-bit LSB. Since the calibration algorithm
is an oversampling process, a minimum of 10,000 clock
cycles are required. This results in a minimum calibration
time upon powerup of 250μs (for a 40MHz clock). Once
calibrated, the CDK1306 remains calibrated over time and
temperature.
Figure 5. Reference Ladder Circuit
Typically, the top side voltage drop for V
equal:
to V
will
will
RHF
RHS
V
– V
= 2.25 % of (V – V ) (typical)
RHF RLF
RHF
RHS
and the bottom side voltage drop for V
equal:
to V
RLF
RLS
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for
the CDK1306 to remain in calibration.
V
– V
= 1.9 % of (V
– V ) (typical)
RLS
RLF
RHF RLF
Figure 5 shows an example of expected voltage drops for
©2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
Input Protection
Digital Outputs
All I/O pads are protected with an on-chip protection circuit
shown in Figure 7. This circuit provides ESD robustness to
3.5kV and prevents latch-up under severe discharge con-
ditions without degrading analog transition times.
The digital outputs (D0–D10) are driven by a separate
supply (OVDD) ranging from +3 V to +5 V. This feature
makes it possible to drive the CDK1306 TTL/CMOS com-
patible outputs with the user’s logic system supply. The
format of the output data (D0–D9) is straight binary. (See
Table 3.) The outputs are latched on the rising edge of
CLK. These outputs can be switched into a tri-state mode
by bringing EN high.
Table 3. Output Data Information
Analog Input
+F.S. + 1/2 LSB
+F.S. –1/2 LSB
+1/2 F.S.
Overrange D10
Output Code D9-D0
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1Ø
ØØ ØØØØ ØØØØ
0 0 0 0 0 0 0 0 0 Ø
0 0 0 0 0 0 0 0 0 0
1
0
0
0
0
+1/2 LSB
0.0V
(Ø indicates the flickering bit between logic 0 and 1.)
Overrange Output
Figure 7. On-Chip Protection Circuit
TheOverrangeOutput(D10)isanindicationthattheanalog
input signal has exceeded the positive fullscale input volt-
age by 1 LSB. When this condition occurs, D10 will switch
to logic 1. All other data outputs (D0 to D9) will remain at
logic 1 as long as D10 remains at logic 1.
Power Supply Sequencing Considerations
All logic inputs should be held low until power to the de-
vice has settled to the specific tolerances. Avoid power
decoupling networks with large time constants that could
delay VDD power to the device.
This feature makes it possible to include the CDK1306 in
higher resolution systems.
Clock Input
Evaluation Board
The CDK1306 is driven from a single-ended TTL-input
clock. Because the pipelined architecture operates on the
rising edge of the clock input, the device can operate over
a wide range of input clock duty cycles without degrading
the dynamic performance.
The TBD evaluation board is available to aid designers in
demonstrating the full performance of the CDK1306. This
board includes a reference circuit, clock driver circuit, out-
put data latches, and an on-board reconstruction of the
digital data. An application note describing the operation
of this board, as well as information on the testing of the
CDK1306, is also available. Contact the factory for price
and availability.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Mechanical Dimensions
SOIC-28 Package
Inches
Millimeters
Symbol
Min
Max
Min
Max
18.01
0.28
A
B
C
D
E
F
G
H
I
0.699
0.005
0.050 Typ
0.018 Typ
0.0077
0.090
0.031
0.396
0.286
0.709
0.011
17.75
0.13
1.27 BSC
0.46 BSC
0.20
2.29
0.79
10.06
7.26
I
H
0.0083
0.096
0.039
0.416
0.292
0.21
2.44
0.99
10.57
7.42
A
F
B
C
D
H
G
E
TQFP-32 Package
A
B
Inches
Millimeters
G
H
Symbol
Min
Max
Min
Max
9.20
7.10
9.20
7.10
A
B
C
D
E
F
G
H
I
0.346
0.272
0.346
0.272
0.362
0.280
0.362
0.280
8.80
6.90
8.80
6.90
0.031 Typ
0.80 BSC
0.012
0.053
0.002
0.037
0.016
0.057
0.006
0.041
0.007
7°
0.30
1.35
0.05
0.95
0.40
1.45
0.15
1.05
0.17
7°
C
D
J
K
L
0°
0°
I
0.020
0.030
0.50
0.75
J
E
F
K
L
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Hꢄꢂdqꢊꢂꢃꢅꢄꢃꢈ Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
Amplify the Human Experience
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
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