CDK1307DILP40 [CADEKA]
Ultra Low Power, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters (ADCs); 超低功耗， 20/40/ 65 / 80MSPS ， 12月13日位模拟至数字转换器（ADC ）
| 型号： | CDK1307DILP40 |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Ultra Low Power, 20/40/65/80MSPS, 12/13-bit Analog-to-Digital Converters (ADCs) |
| 文件： | 总15页 (文件大小：1149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE Data Sheet
Amplify the Human Experience
CDK1307
Ultra Low Power, 20/40/65/80MSPS,
12/13-bit Analog-to-Digital Converters (ADCs)
F E A T U R E S
General Description
nꢀ
13-bit resolution
The CDK1307 is a high performance ultra low power Analog-to-Digital
Converter (ADC). The ADC employs internal reference circuitry, a CMOS
control interface and CMOS output data, and is based on a proprietary struc-
ture. Digital error correction is employed to ensure no missing codes in the
complete full scale range.
nꢀ
nꢀ
20/40/65/80MSPS max sampling rate
Ultra-Low Power Dissipation:
19/33/50/60mW
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
72.4dB SNR at 8MHz FIN
Internal reference circuitry
1.8V core supply voltage
1.7 – 3.6V I/O supply voltage
Parallel CMOS output
Two idle modes with fast startup times exist. The entire chip can either be
put in Standby Mode or Power Down mode. The two modes are optimized to
allow the user to select the mode resulting in the smallest possible energy
consumption during idle mode and startup.
40-pin QFN package
Pin compatible with CDK1308
The CDK1307 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave, and CMOS clock inputs.
A P P L I C A T I O N S
nꢀ
Medical Imaging
nꢀ
Portable Test Equipment
Functional Block Diagram
nꢀ
Digital Oscilloscopes
nꢀ
IF Communication
Ordering Information
Part Number
Speed
Package
QFN-40
QFN-40
QFN-40
QFN-40
Pb-Free RoHS Compliant Operating Temperature Range Packaging Method
CDK1307AILP40
CDK1307BILP40
CDK1307CILP40
CDK1307DILP40
20MSPS
40MSPS
65MSPS
80MSPS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Tray
Tray
Tray
Tray
Moisture sensitivity level for all parts is MSL-3.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
ADVANCE Data Sheet
Pin Configuration
QFN-40
DVSS
CM_EXT
AVDD
AVDD
IP
D_7
1
2
30
29
28
27
26
25
24
23
22
21
D_6
D_5
3
CLK_EXT
OVDD
OVDD
ORNG
D_4
4
CDK1307
5
QFN-40
IN
6
AVDD
DVDDCLK
CLKP
7
8
D_3
9
CLKN
D_2
10
Pin Assignments
Pin No.
Pin Name
Description
0
Ground connection for all power domains. Exposed pad
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
VSS
1, 11, 16
DVDD
2
3, 4, 7
5, 6
8
CM_EXT
AVDD
Analog supply voltage, 1.8V
IP, IN
Analog input (non-inverting, inverting)
DVDDCLK
Clock circuitry supply voltage, 1.8V
9
Clock input, non-inverting (format: LVDS, LVPECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, Connect CLKN to ground
CLKP
CLKN
10
12
CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high.
13
DFRMT
PD_N
Data format selection. 0: Offset Binary, 1: Two's Complement
14
Full chip Power Down mode when Low. All digital outputs reset to zero. After chip power up
always apply Power Down mode before using Active Mode to reset chip.
15
OE_N
OVDD
Output Enable. Tristate when high
17, 18, 25,
26, 36, 37
I/O ring post-driver supply voltage. Voltage range 1.7 to 3.6V
19
20
21
22
D_0
D_1
D_2
D_3
Output Data (LSB, 13-bit output or 1Vpp full scale range)
Output Data LSB, 12-bit output 2Vpp full scale range)
Output Data
Output Data
©2008 CADEKA Microcircuits LLC
www.cadeka.com
2
ADVANCE Data Sheet
Pin Assignments (Continued)
Pin No.
23
Pin Name
D_4
Description
Output Data
24
ORNG
CLK_EXT
D_5
Out of Range flag. High when input signal is out of range
27
Output clock signal for data synchronization. CMOS levels
28
Output Data
29
D_6
Output Data
30
D_7
Output Data
31
D_8
Output Data
32
D_9
Output Data
33
D_10
D_11
D_12
Output Data
34
Output Data (MSB for 1Vpp full scale range, see Reference Voltages section)
Output Data (MSB for 2Vpp full scale range)
35
38, 39
CM_EXTBC_1, Bias control bits for the buffer driving pin CM_EXT
CM_EXTBC_0
00: OFF
10: 50μA
10: 500μA 11: 1mA
Sleep Mode when low
40
SLP_N
©2008 CADEKA Microcircuits LLC
www.cadeka.com
3
ADVANCE Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
Max
Unit
AVDD
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
+2.3
+2.3
+0.3
+3.9
+3.9
+2.3
+3.9
+3.9
V
V
V
V
V
V
V
V
DVDD
AVSS, DVSSCK, DVSS, OVSS
OVDD, OVSS
CLKP, CLKN
Analog inputs and outpts (IPx, INx)
Digital inputs
Digital outputs
Reliability Information
Parameter
Min
Typ
Max
Unit
Junction Temperature
TBD
°C
°C
°C
Storage Temperature Range
Lead Temperature (Soldering, 10s)
-60
+150
TBD
ESD Protection
Product
QFN-40
Human Body Model (HBM)
2kV
Charged Device Model (CDM)
TBD
Recommended Operating Conditions
Parameter
Min
-40
Typ
Max
+85
Unit
°C
Operating Temperature Range
©2008 CADEKA Microcircuits LLC
www.cadeka.com
4
ADVANCE Data Sheet
Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
DC Accuracy
No Missing Codes
Guaranteed
TBD
Offset Error
Midscale offset
mV
%FS
LSB
LSB
V
Gain Error
Full scale range deviation from typical
12-bit level
-6
-0.5
-1
6
0.5
1
DNL
Differential Non-Linearity
Integral Non-Linearity
Common Mode Voltage Output
INL
12-bit level
VCMO
VAVDD/2
Analog Input
VCMI
Input Common Mode
Analog input common mode voltage
Differential input voltage range,
VCM -0.1
VCM +0.1
V
2.0
1.0
Vpp
Vpp
Full Scale Range, Normal
VFSR
Differential input voltage range, 1V
(see section Reference Voltages)
Full Scale Range, Option
Input Capacitance
Bandwidth
Differential input capacitance
Input bandwidth, full power
1.8
pF
500
MHz
Power Supply
Supply voltage to all 1.8V domain pins.
See Pin Configuration and Description
1.7
1.7
1.8
2.5
2.0
3.6
V
V
AVDD,
DVDD
Core Supply Voltage
I/O Supply Voltage
Output driver supply voltage (OVDD).
Must be higher than or equal to Core Supply
OVDD
Voltage (VOVDD ≥ VOCVDD
)
©2008 CADEKA Microcircuits LLC
www.cadeka.com
5
ADVANCE Data Sheet
Electrical Characteristics - CDK1307A
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
72.7
72.6
72.3
72.0
72.4
72.0
71.3
71.4
84.9
88.7
80.1
85.5
-97.6
-100
-101
-95.7
-94.6
-88.7
-80.1
-96.8
11.7
11.7
11.6
11.6
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
SINAD
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
dBc
dBc
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
dBc
dBc
HD3
dBc
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
bits
bits
ENOB
bits
FIN = 20MHz
bits
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
7.8
1.0
1.7
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT enabled
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
1.3
mA
Analog Power Dissipation
Digital Power Dissipation
14.0
5.1
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
19.1
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode
9.9
9.2
μW
Power Dissipation, Sleep mode
mW
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
20
MSPS
MSPS
15
©2008 CADEKA Microcircuits LLC
www.cadeka.com
6
ADVANCE Data Sheet
Electrical Characteristics - CDK1307B
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
73.2
73.0
72.5
71.2
72.1
72.0
71.7
70.6
81.3
82.0
81.6
82.1
-97.5
-103
-95.3
-85.1
-82.5
-85.3
-81.6
-95.8
11.7
11.7
11.6
11.4
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
SINAD
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
dBc
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
dBc
dBc
dBc
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
dBc
dBc
HD3
dBc
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN ≃ FS/2
dBc
bits
bits
ENOB
bits
FIN = 30MHz
bits
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
13.4
1.7
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT enabled
3.3
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
2.4
mA
Analog Power Dissipation
Digital Power Dissipation
24.1
9.1
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
33.2
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode
9.7
μW
Power Dissipation, Sleep mode
14.2
mW
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
40
MSPS
MSPS
20
©2008 CADEKA Microcircuits LLC
www.cadeka.com
7
ADVANCE Data Sheet
Electrical Characteristics - CDK1307C
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
73.1
72.2
71.6
70.4
72.0
71.8
70.7
69.6
82.1
84.8
78.7
79.6
-97.3
-101
-90.4
-91.1
-84.2
-90.2
-78.7
-89.7
11.7
11.6
11.5
11.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
SINAD
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
dBc
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
dBc
dBc
dBc
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
dBc
dBc
dBc
HD3
dBc
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN ≃ FS/2
dBc
bits
bits
ENOB
bits
FIN = 40MHz
bits
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
20.4
2.3
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT enabled
5.1
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
3.5
mA
Analog Power Dissipation
Digital Power Dissipation
36.7
12.9
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
49.6
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode
9.3
μW
Power Dissipation, Sleep mode
20.4
mW
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
65
MSPS
MSPS
40
©2008 CADEKA Microcircuits LLC
www.cadeka.com
8
ADVANCE Data Sheet
Electrical Characteristics - CDK1307D
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle,
-1dBFS 8MHz input signal, 13-bit output, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Performance
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
72.4
71.8
71.0
70.5
70.7
70.8
70.2
69.6
78.2
79.4
79.1
79.7
-97.2
-94.2
-91.6
-81.8
-78.2
-79.4
-83.0
-79.7
11.5
11.5
11.4
11.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
SINAD
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
Effective number of Bits
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
dBc
dBc
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
dBc
dBc
dBc
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
dBc
dBc
HD3
dBc
dBc
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN ≃ FS/2
bits
bits
ENOB
bits
bits
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
24.5
2.9
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT enabled
6.1
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
4.1
mA
Analog Power Dissipation
Digital Power Dissipation
44.1
15.5
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
59.6
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode
9.1
μW
Power Dissipation, Sleep mode
24.1
mW
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
80
MSPS
MSPS
65
©2008 CADEKA Microcircuits LLC
www.cadeka.com
9
ADVANCE Data Sheet
Digital and Timing Electrical Characteristics
(AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle,
-1 dBFS input signal, 5pF capacitive load, unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Clock Inputs
Duty Cycle
Compliance
20
80
% high
CMOS, LVDS, LVPECL, Sine Wave
-200
-800
0.3
200
800
mVpp
mVpp
V
Differential input swing
Input Range
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of OVDD
Differential
Input Common Mode Voltage
Input Capacitance
VOVDD -0.3
1.7
pF
Timing
TPD
From Power Down Mode to Active Mode
References has reached 99% of final value
Start Up Time from Power Down
900
clk cycles
TSLP
TOVR
TAP
Start Up Time from Sleep
Out Of Range Recovery Time
Aperture Delay
From Sleep Mode to Active Mode
0.5
1
μs
clk cycles
0.8
<0.5
12
ns
εRMS
TLAT
Aperture Jitter
ps
clk cycles
ns
Pipeline Delay
5pF load on output bits (see timing diagram)
10pF load on output bits (see timing diagram)
See timing diagram
4
TD
Output Delay
TBD
ns
TDC
Output Delay Relative to CLK_EXT
2
ns
Logic Inputs
VOVDD ≥ 3.0V
2
V
V
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VOVDD = 1.7V – 3.0V
VOVDD ≥ 3.0V
0.8 • VOVDD
0
0.8
0.2 • VOVDD
10
V
VOVDD = 1.7V – 3.0V
0
V
IIH
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
-10
-10
μA
μA
pF
IIL
10
CI
3
Logic Outputs
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
-0.1 +VOVDD
V
V
0.1
5
Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VOCVDD
Post-driver supply voltage above 2.25V (1)
pF
CL
Max Capacitive Load
10
pF
Note:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
©2008 CADEKA Microcircuits LLC
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10
ADVANCE Data Sheet
N+4
N+3
N+5
N+2
N+1
N
N-13
CLK_EXT
Figure 1. Timing Diagram
Recommended Usage
Analog Input
DC-Coupling
Figure 3 shows a recommended configuration for DC-
coupling. Note that the common mode input voltage must
be controlled according to specified values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The analog inputs to the CDK1307 is a switched capacitor
track-and-hold amplifier optimized for differential opera-
tion. Operation at common mode voltages at mid supply
is recommended even if performance will be good for the
ranges specified. The CM_EXT pin provides a voltage suit-
able as common mode voltage reference. The internal
buffer for the CM_EXT voltage can be switched off, and
driving capabilities can be changed by using the CM_EXT-
BC control input.
The input amplifier could be inside a companion chip or
it could be a dedicated amplifier. Several suitable single
ended to differential driver amplifiers exist in the market.
The system designer should make sure the specifications
of the selected amplifier is adequate for the total system,
and that driving capabilities comply with the CDK1307 in-
put specifications.
Figure 2 shows a simplified drawing of the input net-
work. The signal source must have sufficiently low output
impedance to charge the sampling capacitors within one
clock cycle. A small external resistor (e.g. 22Ω) in series
with each input is recommended as it helps reducing
transient currents and dampens ringing behavior. A small
differential shunt capacitor at the chip side of the resistors
may be used to provide dynamic charging currents and
may improve performance. The resistors form a low pass
filter with the capacitor, and values must therefore be
determined by requirements for the application.
Ω
pF
Ω
Figure 3. DC-Coupled Input
Detailed configuration and usage instructions must be
found in the documentation of the selected driver, and
the values given in Figure 3 must be varied according to
the recommendations for the driver.
AC-Coupling
A signal transformer or series capacitors can be used
to make an AC-coupled input network. Figure 4 shows
Figure 2. Input Configuration
©2008 CADEKA Microcircuits LLC
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11
ADVANCE Data Sheet
a recommended configuration using a transformer. Make
sure that a transformer with sufficient linearity is selected,
and that the bandwidth of the transformer is appropriate.
The bandwidth should exceed the sampling rate of the
ADC with at least a factor of 10. It is also important to
keep phase mismatch between the differential ADC inputs
small for good HD2 performance. This type of transformer
coupled input is the preferred configuration for high fre-
quency signals as most differential amplifiers do not have
adequate performance at high frequencies. If the input
signal is traveling a long physical distance from the signal
source to the transformer (for example a long cable), kick-
backs from the ADC will also travel along this distance. If
these kick-backs are not terminated properly at the source
side, they are reflected and will add to the input signal at
the ADC input. This could reduce the ADC performance.
To avoid this effect, the source must effectively terminate
the ADC kick-backs, or the traveling distance should be
very short. If this problem could not be avoided, the cir-
cuit in Figure 6 can be used.
Note that startup time from Sleep Mode and Power Down
Mode will be affected by this filter as the time required
to charge the series capacitors is dependent on the filter
cut-off frequency.
If the input signal has a long traveling distance, and the
kick-backs from the ADC not are effectively terminated at
thesignalsource,theinputnetworkofFigure6canbeused.
The configuration is designed to attenuate the kickback
from the ADC and to provide an input impedance that looks
as resistive as possible for frequencies below Nyquist.
Values of the series inductor will however depend on board
design and conversion rate. In some instances a shunt ca-
pacitor in parallel with the termination resistor (e.g. 33pF)
may improve ADC performance further. This capacitor at-
tenuate the ADC kick-back even more, and minimize the
kicks traveling towards the source. However, the imped-
ance match seen into the transformer becomes worse.
33Ω
220Ω
33Ω
120nH
1:1
33Ω
R
T
RT
47Ω
pF
68Ω
optional
120nH
33Ω
Figure 4. Transformer-Coupled Input
Figure 6. Alternative Input Network
Figure 5 shows AC-coupling using capacitors. Resistors
from the CM_EXT output, R , should be used to bias the
differential input signals to the correct voltage. The series
CM
Clock Input And Jitter Considerations
Typically high-speed ADCs use both clock edges to gener-
ate internal timing signals. In the CDK1307 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% is acceptable.
capacitor, C , form the high-pass pole with these resistors,
I
and the values must therefore be determined based on
the requirement to the high-pass cut-off frequency.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a wide
common mode voltage range is accepted. Differential
clock sources as LVDS, LVPECL or differential sine wave
can be connected directly to the input pins. For CMOS
inputs, the CLKN pin should be connected to ground, and
the CMOS clock signal should be connected to CLKP. For
differential sine wave clock input the amplitude must be
Ω
pF
Ω
Figure 5. AC-Coupled Input
at least ±800mV .
pp
©2008 CADEKA Microcircuits LLC
www.cadeka.com
12
ADVANCE Data Sheet
The quality of the input clock is extremely important for The timing is described in the Timing Diagram section.
Note that the load or equivalent delay on CK_EXT always
should be lower than the load on data outputs to ensure
sufficient timing margins.
high-speed, high-resolution ADCs. The contribution to SNR
from clock jitter with a full scale signal at a given frequency
is shown in the equation below:
The digital outputs can be set in tristate mode by setting
the OE_N signal high.
•
•
•
•
SNR
= 20 log (2 π F εt)
jitter
IN
where F is the signal frequency, and εt is the total rms
IN
The CDK1307 employs digital offset correction. This means
that the output code will be 4096 with shorted inputs.
However, small mismatches in parasitics at the input can
cause this to alter slightly. The offset correction also re-
sults in possible loss of codes at the edges of the full scale
range. With no offset correction, the ADC would clip in one
end before the other, in practice resulting in code loss at
the opposite end. With the output being centered digitally,
the output will clip, and the out of range flags will be set,
before max code is reached. When out of range flags are
set, the code is forced to all ones for over-range and all
zeros for under-range.
jitter measured in seconds. The rms jitter is the total of all
jitter sources including the clock generation circuitry, clock
distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable per-
formance, it is of utmost importance to limit the clock
jitter. This can be obtained by using precise and stable
clock references (e.g. crystal oscillators with good jitter
specifications) and make sure the clock distribution is well
controlled. It might be advantageous to use analog power
and ground planes to ensure low noise on the supplies
to all circuitry in the clock distribution. It is of utmost im-
portance to avoid crosstalk between the ADC output bits
and the clock and between the analog input signal and
the clock since such crosstalk often results in harmonic
distortion.
Data Format Selection
The output data are presented on offset binary form
when DFRMT is low (connect to OV ). Setting DFRMT
SS
high (connect to OV ) results in 2’s complement output
DD
The jitter performance is improved with reduced rise and
fall times of the input clock. Hence, optimum jitter per-
formance is obtained with LVDS or LVPECL clock with fast
edges. CMOS and sine wave clock inputs will result in
slightly degraded jitter performance.
format. Details are shown in Table 1 on page 14.
The data outputs can be used in three different configurations.
Normal mode:
All 13-bits are used. MSB is D_12 and LSB is D_0. This
mode gives optimum performance due to reduced quanti-
zation noise.
If the clock is generated by other circuitry, it should be re-
timed with a low jitter master clock as the last operation
before it is applied to the ADC clock input.
12-bit mode:
The LSB is left unconnected such that only 12 bits are
used. MSB is D_12 and LSB is D_1. This mode gives slightly
reduced performance, due to increased quantization noise.
Digital Outputs
Digital output data are presented on parallel CMOS form.
The voltage on the OVDD pin set the levels of the CMOS
outputs. The output drivers are dimensioned to drive a
wide range of loads for OVDD above 2.25V, but it is rec-
ommended to minimize the load to ensure as low transient
switching currents and resulting noise as possible. In ap-
plications with a large fanout or large capacitive loads, it
is recommended to add external buffers located close to
the ADC chip.
Reduced full scale range mode:
The full scale range is reduced from 2V to 1V which is
pp
pp
equivalent to 6dB gain in the ADC frontend. MSB is D_11
and LSB is D_0. Note that the codes will wrap around
when exceeding the full scale range, and that out of range
bits should be used to clamp output data. See section
Reference Voltages for details. This mode gives slightly
reduced performance.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
13
ADVANCE Data Sheet
Table 1: Data Format Description for 2V Full Scale Range
pp
Output data: D_12 : D_0
Output Data: D_12 : D_0
(DFRMT = 1, 2’s complement)
Differential Input Voltage (IP - IN)
(DFRMT = 0, offset binary)
1 1111 1111 1111
1 0000 0000 0000
0 1111 1111 1111
0 0000 0000 0000
1.0 V
+0.24mV
-0.24mV
-1.0V
0 1111 1111 1111
0 0000 0000 0000
1 1111 1111 1111
1 0000 0000 0000
Reference Voltages
Operational Modes
The operational modes are controlled with the PD_N and
SLP_N pins. If PD_N is set low, all other control pins are
overridden and the chip is set in Power Down mode. In
this mode all circuitry is completely turned off and the
internal clock is disabled. Hence, only leakage current
contributes to the Power Down Dissipation. The startup
time from this mode is longer than for other idle modes
as all references need to settle to their final values before
normal operation can resume.
The reference voltages are internally generated and buff-
ered based on a bandgap voltage reference. No external
decoupling is necessary, and the reference voltages are
not available externally. This simplifies usage of the ADC
since two extremely sensitive pins, otherwise needed, are
removed from the interface.
If a lower full scale range is required the 13-bit output
word provides sufficient resolution to perform digital scaling
with an equivalent impact on noise compared to adjusting
the reference voltages.
The SLP_N bus can be used to power down each channel
independently, or to set the full chip in Sleep Mode. In this
mode internal clocking is disabled, but some low band-
width circuitry is kept on to allow for a short startup time.
However, Sleep Mode represents a significant reduction in
supply current, and it can be used to save power even for
short idle periods.
A simple way to obtain 1.0V input range with a 12-bit
pp
output word is shown in the Table 2 below. Note that only
2‘s complement output data are available in this mode
and that out of range conditions must be determined
based on a two bit output. The output code will wrap
around when the code goes outside the full scale range.
The out of range bits should be used to clamp the output
data for overrange conditions.
The input clock could be kept running in all idle modes.
However, even lower power dissipation is possible in
Power Down mode if the input clock is stopped. In this
case it is important to start the input clock prior to en-
abling active mode.
Table 2: Data Format Description for 1V Full Scale Range
pp
Differential Input
Voltage
Output data: D_11:
D_0 (DFRMT = 0)
(2’s Complement)
Output Data: D_11:
Out of Range
Out of Range
(Use Logical AND Function for &)
D_0 (DFRMT = 1)
(Use Logical AND Function for &)
(IP - IN)
(2’s Complement)
0111 1111 1111
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
1000 0000 0000
> 0.5V
0.5V
0111 1111 1111
0111 1111 1111
0000 0000 0000
1111 1111 1111
1000 0000 0000
1000 0000 0000
D_12 = 1 & D_11 = 1
D_12 = 0 & D_11 = 1
+0.24mV
-0.24mV
-0.5V
< -0.5V
D_12 = 0 & D_11 = 0
D_12 = 1 & D_11 = 0
©2008 CADEKA Microcircuits LLC
www.cadeka.com
14
ADVANCE Data Sheet
Mechanical Dimensions
QFN-40 Package
D
Inches
Typ
–
0.0004
0.023
0.008 REF
0.010
Millimeters
Typ
–
0.01
0.65
0.2 REF
0.25
Symbol
A
Min
–
0.001
–
Max
0.035
0.002
0.028
Min
–
0.00
–
Max
0.9
D2
A
1
A
2
A
3
0.05
0.7
Pin 1 ID - Dia. 0.5
(Top Side)
1.14
F
Pin 1 ID - Dia. R
A
b
0.008
0.013
0.2
0.32
G
D
0.236 BSC
0.226 BSC
0.162
0.016
0.020 BSC
–
6.00 BSC
5.75 BSC
4.10
0.4
0.50 BSC
–
–
0.42
0.2
D
1
A3
A1
D
0.156
0.012
0.167
0.020
3.95
0.3
4.25
0.5
2
L
e
0.45
Pin 0 Exposed Pad
θ
1
0°
12°
–
0.024
–
0°
0.2
0.24
0.1
12°
–
0.6
–
F
G
R
0.008
0.0096
0.004
–
0.0168
0.008
NOTE:
Package dimensions in millimeter unless otherwise noted.
D
D2
D1
θ1
L
e
b
A2
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
Amplify the Human Experience
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
designed by
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
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