CDK2308DITQ64X [CADEKA]
Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters; 双通道， 20/40/ 65 / 80MSPS ， 10位模拟 - 数字转换器
| 型号： | CDK2308DITQ64X |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Dual, 20/40/65/80MSPS, 10-bit Analog-to-Digital Converters |
| 文件： | 总14页 (文件大小：1173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY Data Sheet
Amplify the Human Experience
CDK2308
Dual, 20/40/65/80MSPS, 10-bit
Analog-to-Digital Converters
f E A t u R E s
General Description
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10-bit resolution
The CDK2308 is a high performance, low power dual Analog-to-Digital Con-
verters (ADC). The ADC employs internal reference circuitry, a CMOS control
interface and CMOS output data, and is based on a proprietary structure.
Digital error correction is employed to ensure no missing codes in the com-
plete full scale range.
20/40/65/80MSPS maximum sampling rate
Ultra-low power dissipation: 24/43/65/78mW
61.6dB SNR at 8MHz FIN
Internal reference circuitry
1.8V core supply voltage
1.7V – 3.6V I/O supply voltage
Parallel CMOS output
Several idle modes with fast startup times exist. Each channel can indepen-
dently be powered down and the entire chip can either be put in Standby
Mode or Power Down mode. The different modes are optimized to allow the
user to select the mode resulting in the smallest possible energy consumption
during idle mode and startup.
64-pin TQFP package
Dual channel
Pin compatible with CDK2307
The CDK2308 has a highly linear THA optimized for frequencies up to Nyquist.
The differential clock interface is optimized for low jitter clock sources and
supports LVDS, LVPECL, sine wave and CMOS clock inputs.
A P P L I c A t I o N s
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Medical Imaging
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Portable Test Equipment
Functional Block Diagram
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Digital Oscilloscopes
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IF Communication
CLK_EXT
Ordering Information
Part Number
Speed
Package
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
TQFP-64
Pb-Free RoHS Compliant Operating Temperature Range Packaging Method
CDK2308AITQ64
CDK2308AITQ64X
CDK2308BITQ64
CDK2308BITQ64X
CDK2308CITQ64
CDK2308CITQ64X
CDK2308DITQ64
CDK2308DITQ64X
20MSPS
20MSPS
40MSPS
40MSPS
65MSPS
65MSPS
80MSPS
80MSPS
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Moisture sensitivity level for all parts is MSL-3.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
PRELIMINARY Data Sheet
Pin Configuration
TQFP-64
1
2
48
47
3
46
4
45 N/C
5
44 N/C
6
43 N/C
CDK2308
7
42 CLK_EXT
TQFP-64
8
41
40
39
38
37
36
35
34
33
9
10
11
12
DVSSCLK
13
14
15
16
DVDDCLK
CLKP
CLKN
Pin Assignments
Pin No.
1, 18, 23
2
Pin Name
Description
DVDD
CM_EXT
AVDD
Digital and I/O-ring pre driver supply voltage, 1.8V
Common Mode voltage output
3, 9, 12
4, 5, 8
6, 7
Analog supply voltage, 1.8V
AVSS
Analog ground
IP0, IN0
IP1, IN1
DVSSCLK
DVDDCLK
CLKP
Analog input Channel 0 (non-inverting, inverting)
Analog input Channel 1 (non-inverting, inverting)
Clock circuitry ground
10, 11
13
14
Clock circuitry supply voltage, 1.8V
15
Clock input, non-inverting (Format: LVDS, PECL, CMOS/TTL, Sine Wave)
Clock input, inverting. For CMOS input on CLKP, bypass CLKN to ground with a 10nF capacitor
Digital circuitry ground
16
CLKN
17, 64
19
DVSS
CLK_EXT_EN CLK_EXT signal enabled when low (zero). Tristate when high.
20
DFRMT
PD_N
OE_N_1
OVDD
OVSS
Data format selection. 0: Offset Binary, 1: Two's Complement
Full chip Power Down mode when Low. All digital outputs reset to zero.
Output Enable Channel 0. Tristate when high
I/O ring post-driver supply voltage. Voltage range 1.7V to 3.6V.
Ground for I/O ring
21
22
24, 41, 58
25, 40, 57
26
NC
No Connect
©2008 CADEKA Microcircuits LLC
www.cadeka.com
2
PRELIMINARY Data Sheet
Pin Assignments (Continued)
Pin No.
27
28
29
30
31
32
33
34
35
36
37
38
39
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
59
Pin Name
NC
Description
No Connect
NC
No Connect
D1_0
D1_1
D1_2
D1_3
D1_4
D1_5
D1_6
D1_7
D1_8
D1_9
ORNG_1
CLK_EXT
NC
Output Data Channel 1 (LSB)
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1
Output Data Channel 1 (MSB for 1Vpp full scale range, see Reference Voltages section)
Output Data Channel 1 (MSB for 2Vpp full scale range)
Out of Range flag Channel 1. High when input signal is out of range
Output clock signal for data synchronization. CMOS levels.
No Connect
NC
No Connect
NC
No Connect
D0_0
D0_1
D0_2
D0_3
D0_4
D0_5
D0_6
D0_7
D0_8
D0_9
ORNG_0
OE_N_0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0
Output Data Channel 0 (MSB for 1Vpp full scale range, see Reference Voltages section)
Output Data Channel 0 (MSB for 2Vpp full scale range)
Out of Range flag Channel 0. High when input signal is out of range.
Output Enable Channel 0. Tristate when low.
Bias control bits for the buffer driving pin CM_EXT
CM_EXTBC_1,
CM_EXTBC_0
00: Off
10: 500uA@50MSPS
10: 50uA@50MSPS
11: 1mA@50MSPS
60, 61
62, 63
Sleep Mode
00: Sleep Mode
10: Channel 1 active
SLP_N_1,
SLP_N_0
01: Channel 0 active
11: Both channels active
©2008 CADEKA Microcircuits LLC
www.cadeka.com
3
PRELIMINARY Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
Max
Unit
AVDD, AVSS
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
+2.3
+2.3
+0.3
+3.9
+3.9
+2.3
+3.9
+3.9
V
V
V
V
V
V
V
V
DVDD, DVSS
AVSS, DVSSCK, DVSS, OVSS
OVDD, OVSS
CKP, CKN, DVSSCK
Analog inputs and outpts (IPx, INx, AVSS)
Digital inputs
Digital outputs
Reliability Information
Parameter
Min
Typ
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
64-Lead TQFP
TBD
°C
°C
°C
-60
+150
TBD
TBD
°C/W
Notes:
Package thermal resistance (θ ), JDEC standard, multi-layer test boards, still air.
JA
ESD Protection
Product
TQFP-64
Human Body Model (HBM)
TBD
TBD
Charged Device Model (CDM)
Recommended Operating Conditions
Parameter
Min
-40
Typ
Max
+85
Unit
°C
Operating Temperature Range
©2008 CADEKA Microcircuits LLC
www.cadeka.com
4
PRELIMINARY Data Sheet
Electrical Characteristics
(AV =1.8V, DV =1.8V, DV
=1.8V, OV =2.5V, 50MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal,
DD
DD
DD
DDCLK
13-bit output, unless otherwise noted)
symbꢀl
Parameꢁer
cꢀndiꢁiꢀnꢂ
Min
typ
Max
uniꢁꢂ
DC Accuracy
No Missing Codes
Offset Error
Guaranteed
TBD
Midscale offset
mV
%FS
%FS
LSB
LSB
V
Gain Error
Full scale range deviation from typical
Gain matching between channels
12-bit level
-6
6
Gain Matching
±0.05
DLE
Differential Non-Linearity
Integral Non-Linearity
Common Mode Voltage Output
-1
-1
1
1
ILE
12-bit level
VCMO
VAVDD/2
Analog Input
VCMI
Input Common Mode
Analog input common mode voltage
Differential input voltage range,
VCM -0.1
VCM +0.1
V
2.0
1.0
Vpp
Vpp
Full Scale Range, Normal
VFSR
Differential input voltage range, 1V
(see section Reference Voltages)
Full Scale Range, Option
Input Capacitance
Bandwidth
Differential input capacitance
Input bandwidth, full power
1.8
pF
500
MHz
Power Supply
AVDD, DVDD
Supply voltage to all 1.8V domain pins.
See Pin Configuration and Description
1.7
1.7
1.8
2.5
1.9
3.6
V
V
Core Supply Voltage
I/O Supply Voltage
Output driver supply voltage (OVDD).
Must be higher than or equal to Core Supply
OVDD
Voltage (VOVDD ≥ VOCVDD
)
©2008 CADEKA Microcircuits LLC
www.cadeka.com
5
PRELIMINARY Data Sheet
Electrical Characteristics - CDK2308A
(AV =1.8V, DV =1.8V, DV
=1.8V, OV =2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal,
DD
DD
DDCLK
DD
13-bit output, unless otherwise noted)
symbꢀl
Parameꢁer
cꢀndiꢁiꢀnꢂ
Min
typ
Max
uniꢁꢂ
Performance
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 20MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 20MHz
61.7
61.6
61.6
61.6
61.7
61.6
60.5
61.6
84.1
85.5
70.3
87.5
-88.8
-89.5
-95.9
-91.4
-89.5
-90.5
-70.3
-89.7
10.0
9.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
SNDR
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
HD3
dBc
dBc
bits
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
9.8
bits
9.9
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-105
dBc
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
8.2
1.7
2.8
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
2.3
mA
Analog Power Dissipation
Digital Power Dissipation
14.8
8.8
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
23.7
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.9
15.2
7.7
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
20
MSPS
MSPS
15
©2008 CADEKA Microcircuits LLC
www.cadeka.com
6
PRELIMINARY Data Sheet
Electrical Characteristics - CDK2308B
(AV =1.8V, DV =1.8V, DV
=1.8V, OV =2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal,
DD
DD
DDCLK
DD
13-bit output, unless otherwise noted)
symbꢀl
Parameꢁer
cꢀndiꢁiꢀnꢂ
Min
typ
Max
uniꢁꢂ
Performance
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
FIN = 2MHz
FIN = 8MHz
FIN = FS / 2
FIN = 30MHz
61.6
61.6
61.6
61.5
61.6
61.6
61.2
61.4
78.8
82.3
72.0
82.5
-87.9
-92.0
-84.8
-88.8
-81.8
-85.7
-72.0
-83.9
9.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
SNDR
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
HD3
dBc
dBc
bits
9.9
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
9.9
bits
9.9
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-102
dBc
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
14.4
3.4
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
5.1
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
4.2
mA
Analog Power Dissipation
Digital Power Dissipation
25.9
16.6
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
42.5
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.7
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
25.7
11.3
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
40
MSPS
MSPS
20
©2008 CADEKA Microcircuits LLC
www.cadeka.com
7
PRELIMINARY Data Sheet
Electrical Characteristics - CDK2308C
(AV =1.8V, DV =1.8V, DV
=1.8V, OV =2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal,
DD
DD
DDCLK
DD
13-bit output, unless otherwise noted)
symbꢀl
Parameꢁer
cꢀndiꢁiꢀnꢂ
Min
typ
Max
uniꢁꢂ
Performance
FIN = 8MHz
FIN = 20MHz
FIN = FS / 2
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN = FS / 2
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN = FS / 2
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN = FS / 2
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN = FS / 2
FIN = 40MHz
FIN = 8MHz
FIN = 20MHz
FIN = FS / 2
FIN = 40MHz
61.6
61.6
61.5
61.3
61.6
61.6
60.4
61.1
80.6
85.6
66.4
76.9
-91.4
-93
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
SNDR
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
dBc
dBc
dBc
dBc
dBc
-83.8
-90.7
-80.6
-86.4
-66.4
-76.9
9.9
dBc
dBc
dBc
dBc
HD3
dBc
dBc
bits
9.9
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
9.7
bits
9.9
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-97.0
dBc
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
22.0
5.2
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
7.9
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
6.4
mA
Analog Power Dissipation
Digital Power Dissipation
39.6
25.4
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
65.0
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.3
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
38.2
15.7
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
65
MSPS
MSPS
40
©2008 CADEKA Microcircuits LLC
www.cadeka.com
8
PRELIMINARY Data Sheet
Electrical Characteristics - CDK2308D
(AV =1.8V, DV =1.8V, DV
=1.8V, OV =2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal,
DD
DD
DDCLK
DD
13-bit output, unless otherwise noted)
symbꢀl
Parameꢁer
cꢀndiꢁiꢀnꢂ
Min
typ
Max
uniꢁꢂ
Performance
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN = FS / 2
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN = FS / 2
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN = FS / 2
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN = FS / 2
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN = FS / 2
FIN = 8MHz
FIN = 20MHz
FIN = 30MHz
FIN = FS / 2
61.6
61.2
61.3
61.3
61.3
60.7
61.0
58.7
74.8
73.9
74.7
61.7
-88.5
-95.0
-88.9
-79.0
-74.8
-75.0
-74.7
-61.7
9.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBc
SNR
Signal to Noise Ratio
SNDR
SFDR
HD2
Signal to Noise and Distortion Ratio
Spurious Free Dynamic Range
Second order Harmonic Distortion
Third order Harmonic Distortion
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
HD3
dBc
dBc
bits
9.8
bits
ENOB
XTALK
Effective number of Bits
Crosstalk
9.8
bits
9.5
bits
Signal crosstalk between channels, FIN1
8MHz, FIN0 = 9.9MHz
=
-95.0
dBc
Power Supply
AIDD
Analog Supply Current
Digital Supply Current
26.5
6.1
mA
mA
mA
DIDD
Digital core supply
2.5V output driver supply, sine wave input,
FIN = 1MHz
9.5
OIDD
Output Driver Supply
2.5V output driver supply, sine wave input,
FIN = 1MHz, CLK_EXT disabled
7.6
mA
Analog Power Dissipation
Digital Power Dissipation
47.7
30.0
mW
mW
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
OVDD = 2.5V, 5pF load on output bits,
FIN = 1MHz, CLK_EXT disabled
77.7
mW
Total Power Dissipation
Power Down Dissipation
Sleep Mode 1
9.1
µW
mW
mW
Power Dissipation, Sleep mode one channel
Power Dissipation, Sleep mode both channels
46.1
18.3
Sleep Mode 2
Clock Inputs
Max. Conversion Rate
Min. Conversion Rate
80
MSPS
MSPS
65
©2008 CADEKA Microcircuits LLC
www.cadeka.com
9
PRELIMINARY Data Sheet
Digital and Timing Electrical Characteristics
(AV =1.8V, DV =1.8V, DV
=1.8V, OV =2.5V, 50 MSPS clock, 50% clock duty cycle, -1 dBFS input signal,
DD
DD
DDCLK
DD
5pF capacitive load, unless otherwise noted)
symbꢀl
Parameꢁer
cꢀndiꢁiꢀnꢂ
Min
typ
Max
uniꢁꢂ
Clock Inputs
Duty Cycle
Compliance
20
80
% high
CMOS, LVDS, LVPECL, Sine Wave
-200
-800
0.3
200
800
mVpp
mVpp
V
Differential input swing
Input Range
Differential input swing, sine wave clock input
Keep voltages within ground and voltage of OVDD
Differential
Input Common Mode Voltage
Input Resistance
VOVDD -0.3
TBD
1.7
kΩ
Input Capacitance
pF
Differential
Timing
TPD
From Power Down Mode to References has
eached 99% of final value
Start Up Time Active Mode
580
clk cycles
TSLP
TOVR
TAP
Start Up Time Mode
Out Of Range Recovery Time
Aperture Delay
From Sleep Mode to Active
0.5
4
µs
clk cycles
ns
0.8
12
4
TLAT
Pipeline Delay
clk cycles
ns
5pF load on output bits
10pF load on output bits
Relative to CLK_EXT
TD
Output Delay (see timing diagram)
Output Delay (see timing diagram)
TBD
ns
TDC
2
ns
Logic Inputs
VOVDD ≥ 3.0V
2
V
V
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
VOVDD = 1.7V – 3.0V
VOVDD ≥ 3.0V
0.8 • VOVDD
0
0.8
0.2 • VOVDD
10
V
VOVDD = 1.7V – 3.0V
0
V
IIH
High Level Input Leakage Current
Low Level Input Leakage Current
Input Capacitance
-10
-10
µA
µA
pF
IIL
10
CI
3
Logic Outputs
VOH
VOL
High Level Output Voltage
Low Level Output Voltage
-0.1 +VOVDD
V
V
0.1
5
Post-driver supply voltage equal to pre-driver
supply voltage VOVDD = VOCVDD
Post-driver supply voltage above 2.25V (1)
pF
CL
Max Capacitive Load
10
pF
Nꢀꢁe:
(1) The outputs will be functional with higher loads. However, it is recommended to keep the load on output data bits as low as possible to keep dynamic currents
and resulting switching noise at a minimum.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
10
PRELIMINARY Data Sheet
+F4
+F1
+F
+F2
+F0
+
N-13
N-10
N-9
N-8
N-12
N-11
CLK_EXT
Figure 1. Timing Diagram
Recommended Usage
Analog Input
DC-Coupling
Figure 3 shows a recommended configuration for DC-
coupling. Note that the common mode input voltage must
be controlled according to specified values. Preferably, the
CM_EXT output should be used as a reference to set the
common mode voltage.
The analog inputs to the CDK2308 is a switched capacitor
track-and-hold amplifier optimized for differential opera-
tion. Operation at common mode voltages at mid sup-
ply is recommended even if performance will be good for
the ranges specified. The CM_EXT pin provides a voltage
suitable as common mode voltage reference. The internal
buffer for the CM_EXT voltage can be switched off, and
driving capabilities can be changed by using the CM_EXT-
BC control input.
The input amplifier could be inside a companion chip or
it could be a dedicated amplifier. Several suitable single
ended to differential driver amplifiers exist in the market.
The system designer should make sure the specifications
of the selected amplifier is adequate for the total system,
and that driving capabilities comply with the CDK2308
input specifications.
Figure 2 shows a simplified drawing of the input network.
The signal source must have sufficiently low output imped-
ance to charge the sampling capacitors within one clock
cycle. A small external resistor (e.g. 22Ω) in series with
each input is recommended as it helps reducing transient
currents and dampens ringing behavior. A small differential
shunt capacitor at the chip side of the resistors may be
used to provide dynamic charging currents and may im-
prove performance. The resistors form a low pass filter
with the capacitor, and values must therefore be deter-
mined by requirements for the application.
Ω
pF
Ω
Figure 3. DC-Coupled Input
Detailed configuration and usage instructions must be
found in the documentation of the selected driver.
AC-Coupling
A signal transformer or series capacitors can be used to
make an AC-coupled input network. Figure 4 shows a
recommended configuration using a transformer. Make
sure that a transformer with sufficient linearity is selected,
Figure 2. Input Configuration
©2008 CADEKA Microcircuits LLC
www.cadeka.com
11
PRELIMINARY Data Sheet
and that the bandwidth of the transformer is appropriate.
The bandwidth should exceed the sampling rate of the
ADC with at least a factor of 10. It is also important to
keep phase mismatch between the differential ADC inputs
small for good HD2 performance. This type of transformer
coupled input is the preferred configuration for high fre-
quency signals as most differential amplifiers do not have
adequate performance at high frequencies. Magnetic
coupling between the transformers and PCB traces may
impact channel crosstalk, and must hence be taken into
account during PCB layout.
Note that startup time from Sleep Mode and Power Down
Mode will be affected by this filter as the time required
to charge the series capacitors is dependent on the filter
cut-off frequency.
If the input signal has a long traveling distance, and the
kick-backs from the ADC not are effectively terminated
at the signal source, the input network of figure 8 can
be used. The configuration in figure 8 is designed to at-
tenuate the kickback from the ADC and to provide an in-
put impedance that looks as resistive as possible for fre-
quencies below Nyquist. Values of the series inductor will
however depend on board design and conversion rate.
In some instances a shunt capacitor in parallel with the
termination resistor (e.g. 33pF) may improve ADC per-
formance further. This capacitor attenuate the ADC kick-
back even more, and minimize the kicks traveling towards
the source. However, the impedance match seen into the
transformer becomes worse.
If the input signal is traveling a long physical distance
from the signal source to the transformer (for example a
long cable), kick-backs from the ADC will also travel along
this distance. If these kick-backs are not terminated prop-
erly at the source side, they are reflected and will add to
the input signal at the ADC input. This could reduce the
ADC performance. To avoid this effect, the source must
effectively terminate the ADC kick-backs, or the traveling
distance should be very short. If this problem could not be
avoided, the circuit in Figure 6 can be used.
33Ω
220Ω
33Ω
120nH
1:1
33Ω
R
T
pF
68Ω
optional
RT
47Ω
120nH
33Ω
Figure 6. Alternative Input Network
Figure 4. Transformer-Coupled Input
Figure 5 shows AC-coupling using capacitors. Resistors
from the CM_EXT output, RCM, should be used to bias the
differential input signals to the correct voltage. The series
capacitor, CI, form the high-pass pole with these resistors,
and the values must therefore be determined based on
the requirement to the high-pass cut-off frequency.
Clock Input And Jitter Considerations
Typicallyhigh-speedADCsusebothclockedgestogenerate
internal timing signals. In the CDK2308 only the rising
edge of the clock is used. Hence, input clock duty cycles
between 20% and 80% is acceptable.
The input clock can be supplied in a variety of formats.
The clock pins are AC-coupled internally, and hence a wide
common mode voltage range is accepted. Differential
clock sources as LVDS, LVPECL or differential sine wave
can be connected directly to the input pins. For CMOS
inputs, the CLKN pin should be connected to ground, and
the CMOS clock signal should be connected to CLKP. For
differential sine wave clock input the amplitude must be
Ω
pF
Ω
at least 1V .
Figure 5. AC-Coupled Input
pp
©2008 CADEKA Microcircuits LLC
www.cadeka.com
12
PRELIMINARY Data Sheet
The quality of the input clock is extremely important for The CDK2308 employs digital offset correction. This means
that the output code will be 4096 with the positive and
negative inputs shorted together(zero differential). How-
ever, small mismatches in parasitics at the input can cause
this to alter slightly. The offset correction also results in
possible loss of codes at the edges of the full scale range.
With “NO” offset correction, the ADC would clip in one
end before the other, in practice resulting in code loss at
the opposite end. With the output being centered digitally,
the output will clip, and the out of range flags will be set,
before max code is reached. When out of range flags are
set, the code is forced to all ones for over-range and all
zeros for under-range.
high-speed, high-resolution ADCs. The contribution to SNR
from clock jitter with a full scale signal at a given frequency
is shown in equation 1.
•
•
•
•
SNR
= 20 log (2 π F εt)
jitter
IN
where F is the signal frequency, and εt is the total rms
IN
jitter measured in seconds. The rms jitter is the total of all
jitter sources including the clock generation circuitry, clock
distribution and internal ADC circuitry.
For applications where jitter may limit the obtainable per-
formance, it is of utmost importance to limit the clock jitter.
This can be obtained by using precise and stable clock refer-
ences (e.g. crystal oscillators with good jitter specifications)
and make sure the clock distribution is well controlled. It
might be advantageous to use analog power and ground
planes to ensure low noise on the supplies to all circuitry
Data Format Selection
The output data are presented on offset binary form
when DFRMT is low (connect to OV ). Setting DFRMT
SS
high (connect to OV ) results in 2’s complement output
DD
in the clock distribution. It is of utmost importance to avoid format. Details are shown in Table 1 on page 14.
crosstalk between the ADC output bits and the clock and
Reference Voltages
between the analog input signal and the clock since such
crosstalk often results in harmonic distortion.
The reference voltages are internally generated and buff-
ered based on a bandgap voltage reference. No external
decoupling is necessary, and the reference voltages are
not available externally. This simplifies usage of the ADC
since two extremely sensitive pins, otherwise needed, are
removed from the interface.
The jitter performance is improved with reduced rise and
fall times of the input clock. Hence, optimum jitter per-
formance is obtained with LVDS or LVPECL clock with fast
edges. CMOS and sine wave clock inputs will result in
slightly degraded jitter performance.
If the clock is generated by other circuitry, it should be
retimed with a low jitter master clock as the last operation
before it is applied to the ADC clock input.
Operational Modes
The operational modes are controlled with the PD_N and
SLP_N pins. If PD_N is set low, all other control pins are
overridden and the chip is set in Power Down mode. In this
mode all circuitry is completely turned off and the internal
clock is disabled. Hence, only leakage current contributes
to the Power Down Dissipation. The startup time from this
mode is longer than for other idle modes as all references
need to settle to their final values before normal operation
can resume.
Digital Outputs
Digital output data are presented on parallel CMOS form.
The voltage on the OV pin set the levels of the CMOS
DD
outputs. The output drivers are dimensioned to drive
a wide range of loads for OV above 2.25V, but it is rec-
DD
ommended to minimize the load to ensure as low tran-
sient switching currents and resulting noise as possible. In
applications with a large fanout or large capacitive loads,
it is recommended to add external buffers located close to
the ADC chip.
The SLP_N bus can be used to power down each channel
independently, or to set the full chip in Sleep Mode. In this
mode internal clocking is disabled, but some low band-
width circuitry is kept on to allow for a short startup time.
However, Sleep Mode represents a significant reduction in
supply current, and it can be used to save power even for
short idle periods.
The timing is described in the Timing Diagram section.
Note that the load or equivalent delay on CLK_EXT always
should be lower than the load on data outputs to ensure
sufficient timing margins.
The input clock should be kept running in all idle modes.
However, even lower power dissipation is possible in Power
Down mode if the input clock is stopped. In this case it is
important to start the input clock prior to enabling active mode.
The digital outputs can be set in tristate mode by setting
the OE_N signal high.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
13
PRELIMINARY Data Sheet
Table 1: Data Format Description for 2V Full Scale Range
pp
Output data: Dx_9 : Dx_0
(DFRMT = 0, offset binary)
Output Data: Dx_9 : Dx_0
(DFRMT = 1, 2’s complement)
Differential Input Voltage (IPx - INx)
1.0 V
+0.24mV
-0.24mV
-1.0V
11 1111 1111
01 1111 1111
00 0000 0000
11 1111 1111
10 0000 0000
10 0000 0000
01 1111 1111
00 0000 0000
Mechanical Dimensions
TQFP-64 Package
Inches
Millimeters
Symbol
A
Min
–
0.002
0.037
Typ
–
–
0.039
0.472 BSC
0.393 BSC
0.472 BSC
0.393 BSC
–
Max
0.047
0.006
0.041
Min
–
0.05
0.95
Typ
–
–
Max
–
0.15
1.05
A
A
1
1.00
2
D
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
–
D
1
E
E
1
R
R
0.003
0.003
0°
0.008
–
7°
0.08
0.08
0°
0.20
–
7°
2
–
3.5°
–
3.5°
1
θ
θ
θ
θ
c
L
0°
11°
11°
0.004
0.018
–
12°
12°
–
–
0°
–
12°
12°
0.20
–
13°
13°
1
2
3
13°
13°
0.008
0.030
11°
11°
0.09
0.45
0.24
0.75
L
0.039 REF
–
1.00 REF
–
0.20
0.520 BSC
7.50
7.50
0.20
0.20
0.08
0.08
1
S
b
e
D
E
aaa
bbb
ccc
0.008
0.007
–
0.20
0.17
–
0.27
0.008
0.020 BSC
0.295
0.295
0.008
0.008
0.003
0.003
0.011
2
2
ddd
NOTE:
1. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25mm per side.
D1 and E1 are maxmum plastic body size dimensions including mold mismatch.
2. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause
the lead width to exceed the maximum b dimension by more than 0.08mm.
3. Dambar can not be located on the lower radius or the foot. Minimum space between protrusion
and an adjacent lead is 0.07mm for 0.4mm and 0.5mm pitch packages.
For additional information regarding our products, please visit CADEKA at: cadeka.com
cADEKA Headqꢃarꢁerꢂ Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
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CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
designed by
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
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