CDK3401CTQ48Y [CADEKA]
10-bit, 100/150MSPS, Triple Video DACs; 10位， 100 / 150MSPS ，三路视频数模转换器
| 型号： | CDK3401CTQ48Y |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 10-bit, 100/150MSPS, Triple Video DACs |
| 文件： | 总11页 (文件大小：962K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
Amplify the Human Experience
CDK3400/CDK3401
10-bit, 100/150MSPS, Triple Video DACs
f e a t u r e s
General Description
nꢀ
10-bit resolution
CDK3400/3401 products are low-cost triple D/A converters that are tailored
to fit graphics and video applications where speed is critical. Two speed
grades are available: CDK3400 at 100MSPS and CDK3401 at 150MSPS.
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
nꢀ
150 megapixels per second
±0.1% linearity error
Sync and blank controls
TTL-level inputs are converted to analog current outputs that can drive
25-37.5Ω loads corresponding to doubly-terminated 50-75Ω loads. A sync
1.0Vpp video into 37.5Ω or 75Ω load
Internal bandgap voltage reference
Double-buffered data for low distortion
TTL-compatible inputs
current following SYNC input timing is added to the IO output. BLANK
G
will override RGB inputs, setting IO , IO and IO currents to zero when
G
B
R
BLANK = L. Although appropriate for many applications, the internal 1.235V
reference voltage can be overridden by the V input.
Low glitch energy
REF
Single +5V power supply
Few external components are required, just the current reference resistor,
current output load resistors, and decoupling capacitors.
a p p l i c a t i o n s
nꢀ
Package is a 48-lead TQFP. Fabrication technology is CMOS. Performance is
guaranteed from 0 to 70°C.
Video signal conversion
– RGB
– YCBCR
– Composite, Y, C
Block Diagram
nꢀ
Multimedia systems
nꢀ
Image processing
SYNC
SYNC
BLANK
nꢀ
True-color graphics systems
(1 billion colors)
nꢀ
Broadcast television equipment
10
10
10
10-bit D/A
Converter
nꢀ
IO
IO
IO
High-Definition Television (HDTV)
equipment
G9-0
B9-0
G
B
R
nꢀ
Direct digital synthesis
10-bit D/A
Converter
10-bit D/A
Converter
R9-0
CLOCK
COMP
R
V
REF
REF
+1.235V
Ref
Ordering Information
Part Number
Package
TQFP-48
TQFP-48
TQFP-48
TQFP-48
Pb-Free
Yes
RoHS Compliant Operating Temp Range Packaging Method Package Quantity
CDK3400CTQ48
CDK3400CTQ48Y
CDK3401CTQ48
CDK3401CTQ48Y
Yes
Yes
Yes
Yes
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
Tray
Tray
Tray
Tray
250
Yes
1,250
250
Yes
Yes
1,250
Moisture sensitivity level for all parts is MSL-3.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
Data Sheet
Pin Configuration
TQFP-48
1
2
3
4
5
6
7
8
36
35
34
33
32
31
30
29
28
27
26
25
G1
G2
G3
G4
G5
G6
G7
G8
G9
R
V
REF
REF
COMP
IO
IO
R
G
TQFP
CDK3400/3401
V
V
DD
DD
IO
B
9
GND
GND
CLOCK
NC
BLANK
SYNC
10
11
12
V
DD
Pin Assignments
Pin No.
Pin Name
Description
Clock Input
cꢀꢁꢂk ꢃꢄd pꢅxꢆꢀ i/o
26
47-37
CLK
R9-0
G9-0
B9-0
Red Pixel Data Inputs
Green Pixel Data Inputs
Blue Pixel Data Inputs
48, 9–1
23–14
cꢁꢄꢇꢈꢁꢀꢉ
11
Sync Pulse Input
Blanking Input
SYNC
10
BLANK
Vꢅdꢆꢁ oꢊꢇꢋꢊꢇꢉ
Red Current Output
Green Current Output
Blue Current Output
33
32
29
IOR
IOG
IOB
Vꢁꢀꢇꢃgꢆ rꢆꢌꢆꢈꢆꢄꢂꢆ
35
36
34
V
Voltage Reference Output/Input
REF
R
Current-Setting Resistor
Compensation Capacitor
REF
COMP
pꢁwꢆꢈ ꢃꢄd Gꢈꢁꢊꢄd
12, 30, 31
27, 28
V
Power Supply
Ground
DD
GND
©2008 CADEKA Microcircuits LLC
www.cadeka.com
2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper device
function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
Max
Unit
Power Supply Voltage
V
DD
(Measured to GND)
-0.5
7.0
V
Inputs
Applied Voltage (measured to GND)(2)
Forced Current(3,4)
-0.5
V
V
+ 0.5
V
DD
-10.0
10.0
mA
Outputs
Applied Voltage (measured to GND)(2)
Forced Current(3,4)
-0.5
+ 0.5
V
DD
-60.0
60.0
mA
sec
Short Circuit Duration (single output in HIGH state to GND)
Temperature
Infinite
Operating, Ambient
-20
110
150
300
220
150
°C
°C
°C
°C
°C
Junction
Lead Soldering (10 seconds)
Vapor Phase Soldering (1 minute)
Storage
-65
nꢁꢇꢆꢉ:
1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded.
2. Applied voltage must be current limited to specified range.
3. Forcing voltage must be limited to specified range.
4. Current is specified as conventional current flowing into the device.
Recommended Operating Conditions
Symbol
VDD
Parameter
Min
Typ
5.0
Max
Unit
Power Supply Voltage
4.75
5.25
100
150
V
MSPS
MSPS
ns
CDK3400
CDK3401
CDK3400
CDK3401
CDK3400
CDK3401
CDK3400
CDK3401
fS
Conversion Rate
3.1
2.5
3.1
2.5
10
tPWH
tPWL
tW
CLK Pulsewidth, HIGH
CLK Pulsewidth, LOW
CLK Pulsewidth
ns
ns
ns
ns
6.6
1.7
0
ns
tS
Input Data Setup Time
Input Date Hold Time
Reference Voltage, External
Compensation Capacitor
Output Load
ns
th
ns
VREF
CC
RL
1.0
1.235
0.1
1.5
V
µF
Ω
37.5
VIH
VIL
TA
Input Voltage, Logic HIGH
Input Voltage, Logic LOW
Ambient Temperature, Still Air
2.0
GND
0
VDD
0.8
70
V
V
°C
©2008 CADEKA Microcircuits LLC
www.cadeka.com
3
Data Sheet
Electrical Characteristics
(T = 25°C, V = +5V, V
= 1.235V, R = 37.5Ω, R
= 540Ω; unless otherwise noted)
REF
A
DD
REF
L
symbꢁꢀ
pꢃꢈꢃmꢆꢇꢆꢈ
cꢁꢄdꢅꢇꢅꢁꢄꢉ
Mꢅꢄ
tyꢋ
Mꢃx
uꢄꢅꢇꢉ
IDD
PD
Power Supply Current(1)
Total Power Dissipation(1)
Output Resistance
VDD = 5.25V, TA = 0°C
125
655
mA
mW
kΩ
pF
µA
µA
µA
V
5.25V, TA = 0°C
VDD =
RO
100
CO
Output Capacitance
30
-5
IOUT = 0mA
IIH
Input Current, HIGH
Input Current, LOW
VDD = 5.25V, VIN = 2.4V
VDD = 5.25V, VIN = 0.4V
IIL
5
IREF
VREF
VOC
CDI
VREF Input Bias Current
Reference Voltage Output
Output Compliance
0
1.235
0
±100
Referred to VDD
-0.4
+1.5
10
V
Digital Input Capacitance
4
pF
nꢁꢇꢆꢉ:
1. 100% tested at 25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
Switching Characteristics
(T = 25°C, V = +5V, V
= 1.235V, R = 37.5Ω, R
= 590Ω; unless otherwise noted)
REF
A
DD
REF
L
symbꢁꢀ
pꢃꢈꢃmꢆꢇꢆꢈ
cꢁꢄdꢅꢇꢅꢁꢄꢉ
Mꢅꢄ
tyꢋ
Mꢃx
uꢄꢅꢇꢉ
tD
Clock to Output Delay
Output Skew
VDD = 4.75V, TA = 0°C
10
1
15
2
ns
ns
ns
ns
tSKEW
tR
Output Risetime
Output Falltime
10% to 90% of Full Scale
90% to 10% of Full Scale
3
tF
3
nꢁꢇꢆꢉ:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
System Performance Characteristics
(T = 25°C, V = +5V, V
= 1.235V, R = 37.5Ω, R
= 590Ω; unless otherwise noted)
REF
A
DD
REF
L
symbꢁꢀ
pꢃꢈꢃmꢆꢇꢆꢈ
cꢁꢄdꢅꢇꢅꢁꢄꢉ
Mꢅꢄ
tyꢋ
Mꢃx
uꢄꢅꢇꢉ
INL
Integral Linearity Error
Differential Linearity Error
DAC to DAC Matching
±0.1
±0.1
3
±0.25
±0.25
10
%/FS
%/FS
%
DNL
EDM
PSRR
Power Supply Rejection Ratio
0.05
%/%
nꢁꢇꢆꢉ:
1. 100% production tested at +25°C.
2. Parameter is guaranteed (but not tested) by design and characterization data.
©2008 CADEKA Microcircuits LLC
www.cadeka.com
4
Data Sheet
Table 1. Output Voltage vs. Input Code, SYNC and BLANK, V
= 1.235V, R
= 590Ω, R = 37.5Ω
REF L
REF
Blue anD reD D/as
Green D/a
rGB9-0 (MsB…lsB)
sYnc
BlanK
Vout
0.7140
0.7140
0.7134
0.7127
•
sYnc
BlanK
Vout
1.0000
0.7140
0.9994
0.9987
•
11 1111 1111
11 1111 1111
11 1111 1110
11 1111 1101
•
X
X
X
X
•
1
1
1
1
•
1
0
1
1
•
1
1
1
1
•
•
•
•
•
•
•
•
10 0000 0000
01 1111 1111
•
X
X
•
1
1
•
0.3843
0.3837
•
1
1
•
1
1
•
0.6703
0.6697
•
•
•
•
•
•
•
•
00 0000 0010
00 0000 0001
00 0000 0000
XX XXXX XXXX
XX XXXX XXXX
X
X
X
X
X
1
1
1
0
0
0.0553
0.0546
0.0540
0.0000
0.0000
1
1
1
1
0
1
1
1
0
0
0.3413
0.3406
0.3400
0.2860
0.0000
1/f
s
t
t
PWL
PWH
CLK
t
t
H
s
Pixel Data
and Controls
Data N
Data N+1
Data N+2
3%/FS
90%
10%
t
D
t
SET
t
t
F
R
OUTPUT
50%
Figure 1. CDK3400/3401 Timing Diagram
©2008 CADEKA Microcircuits LLC
www.cadeka.com
5
Data Sheet
which offsets the current output. If BLANK = Low, data
inputs and the pedestal are disabled.
Functional Description
Within the CDK3400/3401 are three identical 10-bit D/A
converters, each with a current source output. External
loads are required to convert the current to voltage out-
puts. Data inputs RGB7-0 are overridden by the BLANK
input. SYNC = H activates, sync current from I for sync-
on-green video signals.
Sync Pulse Input - SYNC
Bringing SYNC LOW, turns off a 40 I (7.62mA) current
RE
source which forms a sync pulse on the Green D/A con-
verter output. SYNC is registered on the rising edge of
CLK with the same pipeline latency as BLANK and pixel
data. SYNC does not override any other data and should
be used only during the blanking interval.
OS
Digital Inputs
All digital inputs are TTL-compatible. Data is registered
on the rising edge of the CLK signal. Following one stage
Since this is a single-supply D/A and all signals are posi-
tive-going, sync is added to the bottom of the Green D/A
range. So turning SYNC OFF means turning the current
source ON. When a sync pulse is desired, the current
source is turned OFF. If the system does not require sync
pulses from the Green D/A converter, SYNC should con-
nected to GND.
of pipeline delay, the analog output changes t after the
DO
rising edge of CLK.
Clock Input - CLK
The clock input is TTL-compatible and all pixel data is
registered on the rising edge of CLK. It is recommended
that CLK be driven by a dedicated TTL buffer to avoid
reflection induced jitter, overshoot, and undershoot.
Blanking Input - BLANK
When BLANK is LOW, pixel inputs are ignored and the
D/A converter outputs fall to the blanking level. BLANK
is registered on the rising edge of CLK and has the same
pipeline latency as SYNC.
Pixel Data Inputs - R9-0, B9-0, G9-0
TTL-compatible Red, Green and Blue Data Inputs are reg-
istered on the rising edge of CLK.
D/A Outputs
Each D/A output is a current source. To obtain a voltage
output, a resistor must be connected to ground. Output
voltage depends upon this external resistor, the reference
voltage, and the value of the gain-setting resistor con-
SYNC and BLANK
SYNC and BLANK inputs control the output level (Figure 2
and Table 1, on the previous page) of the D/A converters
during CRT retrace intervals. BLANK forces the D/A outputs
to the blanking level while SYNC = L turns off a current
source that is connected to the green D/A converter. SYNC
nected between R
and GND.
REF
Normally, a source termination resistor of 75Ω is connect-
ed between the D/A current output pin and GND near the
D/A converter. A 75Ω line may then be connected with an-
other 75Ω termination resistor at the far end of the cable.
This “double termination” presents the D/A converter with
a net resistive load of 37.5Ω.
= H adds a 40 I sync pulse to the green output, SYNC =
RE
L sets the green output to 0.0V during the sync tip. SYNC
and BLANK are registered on the rising edge of CLK.
The CDK3400/3401 may also be operated with a single
75Ω terminating resistor. To lower the output voltage
swing to the desired range, the nominal value of the
Data: 660mV max.
resistor on R
should be doubled.
REF
Pedestal: 54mV
Sync: 286mV
R, G, and B Current Outputs - IO , IO , IO
B
R
G
The R, G, and B current source outputs of the D/A
converters are capable of driving RS-343A/SMPTE-170M
compatible levels into doubly-terminated 75Ω lines. Sync
pulses may be added to the Green D/A output.
Figure 2. Normal Output Levels
BLANK gates the D/A inputs and sets the pedestal voltage.
If BLANK = HIGH, the D/A inputs are added to a pedestal
©2008 CADEKA Microcircuits LLC
www.cadeka.com
6
Data Sheet
Current-Setting Resistor - R
A 0.1µF capacitor must be connected between the COMP
REF
pin and V to stabilize internal bias circuitry and ensure
low-noise operation.
DD
Full-scale output current of each D/A converter is deter-
mined by the value of the resistor connected between
R
and GND. Nominal value of R
is found from:
REF
REF
Voltage Reference Output/Input - V
REF
R
= 9.1 (V /I )
An internal voltage source of +1.235V is output on the
pin. An external +1.235V reference may be applied
REF
REF FS
V
REF
where I is the full-scale (white) output current (in amps)
from the D/A converter (without sync). Sync is 0.4 * I .
FS
here which overrides the internal reference. Decoupling
to GND with a 0.1µF ceramic capacitor is required.
FS
V
REF
D/A full-scale (white) current may also be calculated from:
Power and Ground
I
= V /R
FS L
FS
Required power is a single +5.0V supply. To minimize power
supply induced noise, analog +5V should be connected
Where V is the white voltage level and R is the total
resistive load (Ω) on each D/A converter. V is the blank
to full-scale voltage.
FS
L
to V pins with 0.1µF and 0.01µF decoupling capacitors
DD
FS
placed adjacent to each V pin or pin pair.
DD
The high slew-rate of digital data makes capacitive cou-
pling to the outputs of any D/A converter a potential
problem. Since the digital signals contain high-frequency
components of the CLK signal, as well as the video out-
put signal, the resulting data feedthrough often looks
like harmonic distortion or reduced signal-to-noise perfor-
mance. All ground pins should be connected to a common
solid ground plane for best performance.
Voltage Reference
All three D/A converters are supplied with a common
voltage reference. Internal bandgap voltage reference
voltage is +1.235V with a 3kΩ source resistance. An
external voltage reference may be connected to the V
pin, overriding the internal voltage reference.
REF
©2008 CADEKA Microcircuits LLC
www.cadeka.com
7
Data Sheet
Equivalent Circuits
V
V
DD
DD
p
n
p
Digital
Input
V
DD
n
OUT
GND
GND
Figure 3. Equivalent Digital Input Circuit
Figure 4. Equivalent Analog Output Circuit
V
DD
p
p
R
V
REF
REF
GND
Figure 5. Equivalent Analog Input Circuit
©2008 CADEKA Microcircuits LLC
www.cadeka.com
8
Data Sheet
Typical Application Diagrams
75Ω
Video Cables
220µF
220µF
220µF
R
G
B
75Ω
75Ω
75Ω
1
2
3
4
8
7
6
5
IOR
IN1
IN2
IN3
+Vs
OUT1
OUT2
OUT3
GND
75Ω
75Ω
75Ω
75Ω
CDK3400/
CDK3401
IOG
75Ω
CLC3800
IOB
75Ω
+3V or +5V
1.0µF
0.1µF
AC-Coupling Caps
are Optional
DVD Player or STB
Figure 6. Standard Definition Video Output Circuit Diagram
+Vs
75Ω
Video Cables
IOR
IOG
IOB
+
75Ω
1/3
CDK3400/
CDK3401
CLC3605
-
75Ω
330Ω
75Ω
330Ω
-Vs
Figure 7. Graphics Output Driver Circuit Diagram
+Vs
75Ω
IOR
IOG
IOB
Video Cables
+
75Ω
75Ω
75Ω
1/3
CDK3400/
CDK3401
CLC3605
-
75Ω
75Ω
75Ω
75Ω
75Ω
Video Cables
330Ω
330Ω
-Vs
75Ω
Video Cables
Figure 8. Standard Definition Video Distribution Circuit Diagram
©2008 CADEKA Microcircuits LLC
www.cadeka.com
9
Data Sheet
regulated and free of high-frequency noise. Careful power
supply decoupling will ensure the highest quality video
signals at the output of the circuit. The CDK3400/3401 has
separate analog and digital circuits. To keep digital system
noise from the D/A converter, it is recommended that
Applications Dicussion
Figure 9 below illustrates a typical CDK3400/3401 inter-
face circuit. In this example, an optional 1.2V bandgap
reference is connected to the V
output, overriding the
REF
internal voltage reference source.
power supply voltages (V ) come from the system analog
DD
power source and all ground connections (GND) be made
to the analog ground plane. Power supply pins should be
Grounding
It is important that the CDK3400/3401 power supply is well- individually decoupled at the pin.
+5V
10µF
0.1µF
Red
o
75Ω
75Ω
75Ω
VDD
GND
Z
= 75Ω
IOR
IOG
IOB
RED PIXEL
INPUT
R9-0
G9-0
B9-0
Green w/Sync
75Ω
75Ω
75Ω
Z
Z
= 75Ω
o
Blue
GREEN PIXEL
INPUT
= 75Ω
o
CDK3400/3401
Triple 10-bit D/A Converter
BLUE PIXEL
INPUT
+5V
COMP
CLOCK
SYNC
CLK
3.3kΩ
0.1µF
(not required without external reference)
SYNC
BLANK
VREF
RREF
BLANK
0.1µF
LM185-1.2
(Optional)
560Ω
Figure 9. Typical Interface Circuit Diagram
3. The ground plane should be solid, not cross-hatched.
Printed Circuit Board Layout
Connections to the ground plane should have very short
leads.
Designing with high-performance mixed-signal circuits
demands printed circuits with ground planes. Overall
system performance is strongly influenced by the board
layout. Capacitive coupling from digital to analog circuits
may result in poor D/A conversion. Consider the following
suggestions when doing the layout:
4. If the digital power supply has a dedicated power plane
layer, it should not be placed under the CDK3400/3401,
the voltage reference, or the analog outputs. Capacitive
coupling of digital power supply noise from this layer
to the CDK3400/3401 and its related analog circuitry can
have an adverse effect on performance.
1. Keep the critical analog traces (V , I , COMP, IO ,
REF REF
S
IO , IO ) as short as possible and as far as possible
R
G
from all digital signals. The CDK3400/3401 should be
located near the board edge, close to the analog out-put
connectors.
5. CLK should be handled carefully. Jitter and noise on this
clock will degrade performance. Terminate the clock line
carefully to eliminate overshoot and ringing.
2. Power plane for the CDK3400/3401 should be separate
from that which supplies the digital circuitry. A single
Evaluation boards are available (CEB3400 and CEB3401),
contact CADEKA for more information.
power plane should be used for all of the V pins. If
DD
the power supply for the CDK3400/3401 is the same
as that of the system’s digital circuitry, power to the
CDK3400/3401 should be decoupled with 0.1µF and
0.01µF capacitors and iso-lated with a ferrite bead.
Related Products
n
ꢀ
CDK3402/3403 Triple 8-bit 100/150MSPS DACs
CDK3404 Triple 8-bit 180MSPS DAC
n
ꢀ
©2008 CADEKA Microcircuits LLC
www.cadeka.com
10
Data Sheet
Mechanical Dimensions
TQFP-48 Package
For additional information regarding our products, please visit CADEKA at: cadeka.com
caDeKa Hꢆꢃdqꢊꢃꢈꢇꢆꢈꢉ Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
Amplify the Human Experience
CADEKA, the CADEKA logo design, COMLINEAR and the COMLINEAR logo design are trademarks or registered trademarks of CADEKA
Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
Copyright ©2008 by CADEKA Microcircuits LLC. All rights reserved.
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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