CLC2011IMP8X [CADEKA]
Low Power, Low Cost, Rail-to-Rail I/O Amplifiers; 低功耗，低成本，轨到轨输入/输出放大器
| 型号： | CLC2011IMP8X |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | Low Power, Low Cost, Rail-to-Rail I/O Amplifiers |
| 文件： | 总16页 (文件大小：2674K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Data Sheet
Amplify the Human Experience
Comlinear® CLC1011, CLC2011, CLC4011
Low Power, Low Cost, Rail-to-Rail I/O Amplifiers
F E A T U R E S
General Description
n
136μA supply current
The COMLINEAR CLC1011 (single), CLC2011 (dual), and CLC4011 (quad) are
n
n
4.9MHz bandwidth
ultra-low cost, low power, voltage feedback amplifiers. At 5V, the CLCx011
family uses only 160μA of supply current per amplifier and are designed to
operate from a supply range of 2.5V to 5.5V (±1.25 to ±2.75). The input volt-
age range exceeds the negative and positive rails.
Output swings to within 20mV of either
rail
n
Input voltage range exceeds the rail by
>250mV
n
n
n
n
n
5.3V/μs slew rate
The CLCx011 family of amplifiers offer high bipolar performance at a low
CMOS prices. They offer superior dynamic performance with 4.9MHz small
signal bandwidths and 5.3V/μs slew rates. The combination of low power,
high bandwidth, and rail-to-rail performance make the CLCx011 amplifiers
well suited for battery-powered communication/computing systems
21nV/√Hz input voltage noise
16mA output current
Fully specified at 2.7V and 5V supplies
CLC1011: Pb-free SOT23-5, SC70-5,
SOIC-8
n
n
CLC2011: Pb-free SOIC-8, MSOP-8
CLC4011: Pb-free SOIC-14. TSSOP-14
Typical Performance Examples
A P P L I C A T I O N S
Large Signal Frequency Response
Output Swing vs. Load
n
Portable/battery-powered applications
1.35
R
= 10kΩ
L
V
= 5V
s
n
PCMCIA, USB
R
= 1kΩ
V
= 1V
pp
L
o
n
Mobile communications, cell phones,
pagers
R
= 75Ω
L
n
ADC buffer
0
R
= 100Ω
L
n
Active filters
V
= 4V
pp
o
R
= 200Ω
L
n
Portable test instruments
R
= 75/100Ω
L
V
= 2V
pp
o
n
Notebooks and PDA’s
n
Signal conditioning
-1.35
0.01
0.1
1
10
-2.0
0
2.0
n
Medical Equipment
Frequency (MHz)
Input Voltage (0.4V/div)
n
Portable medical instrumentation
Ordering Information
Part Number
Package
SC70-5
Pb-Free
RoHS Compliant
Operating Temperature Range Packaging Method
CLC1011ISC5X*
CLC1011IST5X*
CLC2011ISO8X*
CLC2011IMP8X*
CLC4011ISO14X*
CLC4011ITP14X*
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Reel
Reel
Reel
Reel
Reel
Reel
SOT23-5
SOIC-8
MSOP-8
SOIC-14
TSSOP-14
Moisture sensitivity level for all parts is MSL-1. *Advance Information.
©2009 CADEKA Microcircuits LLC
www.cadeka.com
Advance Data Sheet
CLC1011 Pin Assignments
CLC1011 Pin Configuration
Pin No.
Pin Name
OUT
Description
1
2
3
4
5
Output
-V
Negative supply
Positive input
Negative input
Positive supply
S
OUT
-V
1
2
3
5
4
+V
S
+IN
-IN
-
+
S
-IN
+IN
+V
S
CLC2011 Pin Configuration
CLC2011 Pin Configuration
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
3
4
5
6
7
8
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Negative supply
1
2
3
4
8
+V
S
OUT1
-IN1
+IN1
7
OUT2
-IN2
-V
S
6
5
+IN1
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
Positive supply
+IN2
-V
S
OUT2
+V
S
CLC4011 Pin Configuration
CLC4011 Pin Configuration
Pin No.
Pin Name
OUT1
-IN1
Description
1
2
Output, channel 1
Negative input, channel 1
Positive input, channel 1
Positive supply
1
2
3
4
14
13
12
11
10
9
3
+IN1
OUT1
-IN1
OUT4
-IN4
4
+V
S
5
+IN2
-IN2
Positive input, channel 2
Negative input, channel 2
Output, channel 2
+IN1
+VS
+IN4
-VS
6
7
OUT2
OUT3
-IN3
8
Output, channel 3
5
6
7
+IN2
+IN3
-IN3
9
Negative input, channel 3
Positive input, channel 3
Negative supply
-IN2
10
11
12
13
14
+IN3
8
OUT2
-V
S
OUT3
+IN4
-IN4
Positive input, channel 4
Negative input, channel 4
Output, channel 4
OUT4
©2009 CADEKA Microcircuits LLC
www.cadeka.com
2
Advance Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device
should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-
vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the
operating conditions noted on the tables and plots.
Parameter
Min
0
Max
6
Unit
Supply Voltage
V
V
Input Voltage Range
Continuous Output Current
-V -0.5V
s
+V +0.5V
s
-30
30
mA
Reliability Information
Parameter
Min
-65
Typ
Max
Unit
Junction Temperature
Storage Temperature Range
Lead Temperature (Soldering, 10s)
Package Thermal Resistance
5-Lead SC70
175
150
260
°C
°C
°C
TBD
TBD
TBD
TBD
TBD
TBD
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
5-Lead SOT23
8-Lead SOIC
8-Lead MSOP
14-Lead SOIC
14-Lead TSSOP
Notes:
Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.
JA
ESD Protection
Product
SC70-5
SOT23-5
SOIC-8
MSOP-8
SOIC-14
TSSOP-14
Human Body Model (HBM)
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
Charged Device Model (CDM)
Recommended Operating Conditions
Parameter
Min
Typ
Max
Unit
Operating Temperature Range
-40
2.5
+85
5.5
°C
V
Supply Voltage Range
©2009 CADEKA Microcircuits LLC
www.cadeka.com
3
Advance Data Sheet
Electrical Characteristics at +2.7V
T = 25°C, V = +2.7V, R = R =5kΩ, R = 10kΩ to V /2, G = 2; unless otherwise noted.
A
s
f
g
L
S
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
UGBWSS
BWSS
Unity Gain -3dB Bandwidth
-3dB Bandwidth
G = +1, VOUT = 0.02Vpp
G = +2, VOUT = 0.2Vpp
G = +2, VOUT = 2Vpp
4.9
3.7
1.4
2.2
MHz
MHz
MHz
MHz
BWLS
Large Signal Bandwidth
Gain Bandwdith Product
GBWP
G = +11, VOUT = 0.2Vpp
Time Domain Response
tR, tF
OS
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
VOUT = 1V step
163
<1
ns
%
Overshoot
Slew Rate
SR
1V step
5.3
V/µs
Distortion/Noise Response
HD2
2nd Harmonic Distortion
VOUT = 1Vpp, 10kHz
VOUT = 1Vpp, 10kHz
VOUT = 1Vpp, 10kHz
> 10kHz
-72
-72
0.03
21
dBc
dBc
HD3
3rd Harmonic Distortion
Total Harmonic Distortion
Input Voltage Noise
THD
%
en
nV/√Hz
DC Performance
VIO
dVIO
Ib
Input Offset Voltage (1)
-6
0.5
5
6
mV
µV/°C
nA
Average Drift
Input Bias Current (1)
Average Drift
90
32
83
90
136
420
dIb
PSRR
AOL
IS
pA/°C
dB
Power Supply Rejection Ratio (1)
Open-Loop Gain
DC
55
VOUT = VS / 2
per channel
dB
Supply Current (1)
190
μA
Input Characteristics
RIN
CIN
Input Resistance
Non-inverting
12
2
MΩ
Input Capacitance
pF
-0.25 to
2.95
CMIR
Common Mode Input Range
V
CMRR
Common Mode Rejection Ratio (1)
DC
55
81
dB
Output Characteristics
0.06 to
2.64
0.02 to
2.68
RL = 10kΩ to VS / 2 (1)
RL = 1kΩ to VS / 2
RL = 200Ω to VS / 2
V
V
0.05 to
2.63
VOUT
Output Voltage Swing
0.11 to
2.52
V
IOUT
Output Current
±16
mA
Notes:
1. 100% tested at 25°C
©2009 CADEKA Microcircuits LLC
www.cadeka.com
4
Advance Data Sheet
Electrical Characteristics at +5V
T = 25°C, V = +5V, R = R =5kΩ, R = 10kΩ to V /2, G = 2; unless otherwise noted.
A
s
f
g
L
S
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Frequency Domain Response
UGBWSS
BWSS
Unity Gain -3dB Bandwidth
-3dB Bandwidth
G = +1, VOUT = 0.02Vpp
G = +2, VOUT = 0.2Vpp
G = +2, VOUT = 2Vpp
4.3
3.0
2.3
2.0
MHz
MHz
MHz
MHz
BWLS
Large Signal Bandwidth
Gain Bandwdith Product
GBWP
G = +11, VOUT = 0.2Vpp
Time Domain Response
tR, tF
OS
Rise and Fall Time
VOUT = 1V step; (10% to 90%)
VOUT = 1V step
110
<1
9
ns
%
Overshoot
Slew Rate
SR
1V step
V/µs
Distortion/Noise Response
HD2
2nd Harmonic Distortion
VOUT = 1Vpp, 10kHz
VOUT = 1Vpp, 10kHz
VOUT = 1Vpp, 10kHz
> 10kHz
-73
-75
0.03
22
dBc
dBc
HD3
3rd Harmonic Distortion
Total Harmonic Distortion
Input Voltage Noise
THD
%
en
nV/√Hz
DC Performance
VIO
dVIO
Ib
Input Offset Voltage (1)
-8
1.5
15
8
mV
µV/°C
nA
Average Drift
Input Bias Current (1)
Average Drift
90
450
dIb
PSRR
AOL
IS
40
pA/°C
dB
Power Supply Rejection Ratio (1)
Open-Loop Gain
DC
40
60
VOUT = VS / 2
per channel
80
dB
Supply Current (1)
160
235
μA
Input Characteristics
RIN
CIN
Input Resistance
Non-inverting
12
2
MΩ
Input Capacitance
pF
-0.25 to
5.25
CMIR
Common Mode Input Range
V
CMRR
Common Mode Rejection Ratio (1)
DC
58
85
dB
Output Characteristics
0.08 to
4.92
0.04 to
4.96
RL = 10kΩ to VS / 2 (1)
RL = 1kΩ to VS / 2
RL = 200Ω to VS / 2
V
V
0.07 to
4.9
VOUT
Output Voltage Swing
0.14 to
4.67
V
IOUT
Output Current
±30
mA
Notes:
1. 100% tested at 25°C
©2009 CADEKA Microcircuits LLC
www.cadeka.com
5
Advance Data Sheet
Typical Performance Characteristics
T = 25°C, V = +2.7V, R = R =5kΩ, R = 10kΩ to V /2, G = 2; unless otherwise noted.
A
s
f
g
L
S
Non-Inverting Frequency Response at V = 5V
Inverting Frequency Response at V = 5V
S
S
V
= 0.2V
V
= 0.2V
o
pp
o
pp
G = 1
R = 0
f
G = 2
R = 5kΩ
R = 5kΩ
f
f
R = 5kΩ
f
R = 5kΩ
f
R = 5kΩ
f
G = 5
R = 5kΩ
f
R = 5kΩ
f
0.01
0.1
0.01
0.1
1
10
1
10
Frequency (MHz)
Frequency (MHz)
Non-Inverting Frequency Response
Inverting Frequency Response
V
= 0.2V
R = 5kΩ
G = 1
R = 0
f
o
pp
f
G = 2
R = 5kΩ
G = -2
f
G = -1
R = 5kΩ
f
G = -10
G = -5
G = 5
R = 5kΩ
f
0.01
0.1
0.01
0.1
1
10
1
10
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. C
Frequency Response vs. R
L
L
V
= 0.05V
C
R
o
L
= 100Ω
s
C
R
L
s
= 0Ω
R
= 1kΩ
R
= 10kΩ
L
L
C
L
R
= 0Ω
s
R
= 200Ω
C
L
R
L
= 0Ω
s
+
Rs
R
= 50Ω
L
-
CL RL
5kΩ
5kΩ
0.01
0.1
1
10
0.01
0.1
1
10
Frequency (MHz)
Frequency (MHz)
©2009 CADEKA Microcircuits LLC
www.cadeka.com
6
Advance Data Sheet
Typical Performance Characteristics
T = 25°C, V = +2.7V, R = R =5kΩ, R = 10kΩ to V /2, G = 2; unless otherwise noted.
A
s
f
g
L
S
Frequency Response vs. V
Open Loop Gain & Phase vs. Frequency
OUT
140
V
= 5V
V = 5V
s
s
R
= 10kΩ
L
120
No load
V
= 1V
pp
o
100
80
0
60
40
20
0
-45
-90
-135
-180
V
= 4V
pp
o
V
= 2V
pp
o
R
= 10kΩ
No load
L
-20
100 101 102 103 104 105 106 107 108
Frequency (Hz)
0.01
0.1
1
10
Frequency (MHz)
2nd Harmonic Distortion vs. V
3rd Harmonic Distortion vs. V
OUT
OUT
-20
-30
-40
-50
-60
-20
-30
-40
50kHz
-50
100kHz
50kHz
100kHz
-60
20kHz
50kHz
-70
-70
10kHz
10kHz, 20kHz
-80
-80
10kHz
-90
-90
0.5
1
0.5
1
1.5
2
2.5
1.5
2
2.5
Output Amplitude (V )
Output Amplitude (V )
pp
pp
2nd & 3rd Harmonic Distortion
Input Voltage Noise
-20
55
50
45
40
35
30
25
20
15
10
5
V
= 1V
pp
o
R
= 200Ω
-30
-40
-50
-60
-70
-80
-90
L
R
= 1kΩ
L
R
= 200Ω
L
R
= 10kΩ
L
R
= 1kΩ
L
R
= 10kΩ
L
0
0
20
0.1k
40
60
80
100
1k
10k
100k
1M
Frequency (kHz)
Frequency (Hz)
©2009 CADEKA Microcircuits LLC
www.cadeka.com
7
Advance Data Sheet
Typical Performance Characteristics - Continued
T = 25°C, V = ±5V, R = R =150Ω, R = 150Ω, G = 2; unless otherwise noted.
A
s
f
g
L
CMRR
PSRR
0
0
-10
-20
-10
-20
-30
-40
-50
-60
-70
-80
-90
-30
-40
-50
-60
-70
-80
-90
10
100
10
1000
10000
100000
100
1000
10000
100000
Frequency (Hz)
Frequency (Hz)
Output Swing vs. Load
Pulse Response vs. Common Mode Voltage
1.35
R
= 10kΩ
L
R
= 1kΩ
L
R
= 75Ω
L
0
R
= 100Ω
L
R
= 200Ω
L
R
= 75/100Ω
L
-1.35
-2.0
0
2.0
Input Voltage (0.4V/div)
©2009 CADEKA Microcircuits LLC
www.cadeka.com
8
Advance Data Sheet
Power Dissipation
Application Information
Power dissipation should not be a factor when operating
under the stated 10k ohm load condition. However, ap-
plications with low impedance, DC coupled loads should
be analyzed to ensure that maximum allowed junction
temperature is not exceeded. Guidelines listed below can
be used to verify that the particular application will not
cause the device to operate beyond it’s intended operat-
ing range.
General Description
The CLCx011 family of amplifiers are single supply, general
purpose, voltage-feedback amplifiers. They are fabricated
on a complimentary bipolar process, feature a rail-to-rail in-
put and output, and are unity gain stable.
Basic Operation
Figures 1, 2, and 3 illustrate typical circuit configurations for
non-inverting, inverting, and unity gain topologies for dual
supply applications. They show the recommended bypass
capacitor values and overall closed loop gain equations.
Maximum power levels are set by the absolute maximum
junction rating of 150°C. To calculate the junction tem-
perature, the package thermal resistance value Theta
JA
(Ө ) is used along with the total die power dissipation.
JA
+Vs
6.8μF
T
= T + (Ө × P )
Ambient JA D
Junction
Where T
is the temperature of the working environment.
Ambient
0.1μF
Input
+
-
In order to determine P , the power dissipated in the load
needs to be subtracted from the total power delivered by
the supplies.
D
Output
RL
0.1μF
6.8μF
Rf
P = P
- P
load
D
supply
Rg
Supply power is calculated by the standard power equa-
tion.
G = 1 + (Rf/Rg)
-Vs
P
= V
× I
supply
supply RMS supply
Figure 1. Typical Non-Inverting Gain Circuit
+Vs
V
= V - V
S+ S-
supply
6.8μF
Power delivered to a purely resistive load is:
R1
2
P
= ((V
)
)/Rload
eff
0.1μF
load
LOAD RMS
+
Output
Rg
The effective load resistor (Rload ) will need to include
eff
Input
-
RL
the effect of the feedback network. For instance,
0.1μF
Rf
Rload in figure 3 would be calculated as:
eff
6.8μF
G = - (Rf/Rg)
-Vs
R || (R + R )
L
f
g
For optimum input offset
voltage set R1 = Rf ||Rg
These measurements are basic and are relatively easy to
perform with standard lab equipment. For design purpos-
es however, prior knowledge of actual signal levels and
load impedance is needed to determine the dissipated
Figure 2. Typical Inverting Gain Circuit
+Vs
6.8μF
power. Here, P can be found from
D
P = P
+ P
- P
D
Quiescent
Dynamic Load
0.1μF
Input
+
Quiescent power can be derived from the specified I val-
S
Output
ues along with known supply voltage, V
. Load power
Supply
-
RL
can be calculated as above with the desired signal ampli-
tudes using:
0.1μF
(V
)
= V
/ √2
LOAD RMS
PEAK
6.8μF
G = 1
-Vs
( I
)
= ( V
)
/ Rload
LOAD RMS
LOAD RMS eff
Figure 3. Unity Gain Circuit
©2009 CADEKA Microcircuits LLC
www.cadeka.com
9
Advance Data Sheet
The dynamic power is focused primarily within the output
and possible unstable behavior. Use a series resistance, R ,
S
stage driving the load. This value can be calculated as:
between the amplifier and the load to help improve stability
and settling performance. Refer to Figure 6.
P
= (V - V
)
× ( I )
LOAD RMS
DYNAMIC
S+
LOAD RMS
Assuming the load is referenced in the middle of the pow-
er rails or V /2.
Input
+
-
Rs
Output
supply
CL
RL
Figure 4 shows the maximum safe power dissipation in
the package vs. the ambient temperature for the pack-
ages available.
Rf
Rg
Figure 6. Addition of R for Driving
S
Capacitive Loads
Table 1 provides the recommended R for various capaci-
S
tive loads. The recommended R values result in approxi-
S
mately <1dB peaking in the frequency response. The Fre-
quency Response vs. C plot, on page 6, illustrates the
L
response of the CLCx011.
C (pF)
L
R (Ω)
S
-3dB BW (kHz)
10pF
20pF
50pF
100pF
0
0
2.2
2.4
2.5
2
0
100
Figure 4. Maximum Power Derating
Input Common Mode Voltage
Table 1: Recommended R vs. C
S
L
For a given load capacitance, adjust R to optimize the
S
The common mode input range extends to 250mV below
ground and to 250mV above Vs, in single supply opera-
tion. Exceeding these values will not cause phase reversal.
However, if the input voltage exceeds the rails by more
than 0.5V, the input ESD devices will begin to conduct. The
output will stay at the rail during this overdrive condition.
If the absolute maximum input voltage (700mV beyond ei-
ther rail) is exceeded, externally limit the input current to
±5mA as shown in Figure 5.
tradeoff between settling time and bandwidth. In general,
reducing R will increase bandwidth at the expense of ad-
S
ditional overshoot and ringing.
Overdrive Recovery
An overdrive condition is defined as the point when ei-
ther one of the inputs or the output exceed their specified
voltage range. Overdrive recovery is the time needed for
the amplifier to return to its normal or linear operating
point. The recovery time varies, based on whether the
input or output is overdriven and by how much the range
is exceeded. The CLCx011 will typically recover in less
than 50ns from an overdrive condition. Figure 7 shows the
CLC1011 in an overdriven condition.
10k
Input
Output
Figure 5. Circuit for Input Current Protection
Driving Capacitive Loads
Increased phase delay at the output due to capacitive load-
ing can cause ringing, peaking in the frequency response,
©2009 CADEKA Microcircuits LLC
www.cadeka.com
10
Advance Data Sheet
Evaluation Board Schematics
Evaluation board schematics and layouts are shown in Fig-
ures 8-14. These evaluation boards are built for dual- sup-
ply operation. Follow these steps to use the board in a
single-supply application:
1. Short -Vs to ground.
2. Use C3 and C4, if the -V pin of the amplifier is not
S
directly connected to the ground plane.
Figure 7. Overdrive Recovery
Layout Considerations
General layout and supply bypassing play major roles in
high frequency performance. CaDeKa has evaluation
boards to use as a guide for high frequency layout and as
an aid in device testing and characterization. Follow the
steps below as a basis for high frequency layout:
• Include 6.8µF and 0.1µF ceramic capacitors for power
supply decoupling
• Place the 6.8µF capacitor within 0.75 inches of the power pin
• Place the 0.1µF capacitor within 0.1 inches of the power pin
• Remove the ground plane under and around the part,
especially near the input and output pins to reduce para-
sitic capacitance
Figure 8. CEB002 Schematic
• Minimize all trace lengths to reduce series inductances
Refer to the evaluation board layouts below for more in-
formation.
Evaluation Board Information
The following evaluation boards are available to aid in the
testing and layout of these devices:
Evaluation Board #
CEB011
CEB002
CEB006
CEB010
Products
CLC1011 in SC70
CLC1011 in SOT23
CLC2011 in SOIC
CLC2011 in MSOP
CLC4011 in SOIC
CLC4011 in TSSOP
CEB018
CEB017
Figure 9. CEB002 Top View
©2009 CADEKA Microcircuits LLC
www.cadeka.com
11
Advance Data Sheet
Figure 10. CEB002 Bottom View
Figure 12. CEB006 Top View
Figure 13. CEB006 Bottom View
Figure 11. CEB006 Schematic
©2009 CADEKA Microcircuits LLC
www.cadeka.com
12
Advance Data Sheet
Figure 16. CEB018 Bottom View
Figure 14. CEB018 Schematic
Figure 15. CEB018 Top View
©2009 CADEKA Microcircuits LLC
www.cadeka.com
13
Advance Data Sheet
Mechanical Dimensions
SOT23-5 Package
SOIC-8 Package
©2009 CADEKA Microcircuits LLC
www.cadeka.com
14
Advance Data Sheet
Mechanical Dimensions continued
SOIC-14 Package
©2009 CADEKA Microcircuits LLC
www.cadeka.com
15
Advance Data Sheet
For additional information regarding our products, please visit CADEKA at: cadeka.com
CADEKA Headquarters Loveland, Colorado
T: 970.663.5452
T: 877.663.5452 (toll free)
CADEKA, the CADEKA logo design, COMLINEAR, the COMLINEAR logo design, and ARCTIC are trademarks or registered trademarks of
CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.
CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any
responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in
writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,
copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.
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Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved.
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