CLC2550ISO8X_技术文档

Data Sheet

Amplify the Human Experience

Comlinear^®CLC2550, CLC4550

Low Power, Low Offset, 2V to 36V Comparators

F E A T U R E S

General Description

n

2mV input offset voltage

The COMLINEAR CLC2550 (dual) and CLC4550 (quad) are precision voltage

comparators with a typical offset of 2mV and high gain (200V/mV). These

comparators also offer an input common-mode voltage range that includes

ground.

n

25nA input bias current

±5nA input offset current

0.9mA supply current

CMIR includes ground

200mV output saturation voltage at 4mA

2V to 36V single supply voltage range

±1V to ±18V dual supply voltage range

Open collector output

The COMLINEAR CLC2550, and CLC4550 operate from a wide supply voltage

range of ±1V to ±18V, or from a single supply range of 2V to 36V. These

comparators are available in Pb-free, RoHS compliant SOIC-8 and SOIC-14

packages. They operate over the industrial temperature range of -40°C to

+85°C.

Differential input voltage range equals

the power supply voltage

n

CLC2550: improved replacement for

Typical Application - One Shot Multivibrator

industry standard LM393

n

CLC4550: Improved replacement for

V

CC

industry standard LM339

n

CLC2550: Pb-free SOIC-8

n

CLC4550: Pb-free SOIC-14

1MΩ

10kΩ

A P P L I C A T I O N S

100pF

n

Battery charger

+V

IN

–

n

1/4

CLCx550A

Cordless telephone

V

OUT

n

Switching power supply

+

n

DC-DC module

n

0.001µF

PC motherboard

n

Communication equipment

n

Widerange VCO

1MΩ

n

Squarewave and time delay generators

n

MOS clock timers

n

High voltage digital logic gates

n

Multivibrators

Ordering Information

Part Number

Package

SOIC-8

Pb-Free

Yes

RoHS Compliant

Operating Temperature Range Packaging Method

CLC2550ISO8X

CLC4550ISO14X

Yes

-40°C to +85°C

Reel

SOIC-14

Yes

Moisture sensitivity level for all parts is MSL-1.

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Data Sheet

CLC2550 Pin Conﬁguration

Pin No.

Pin Name

OUT1

-IN1

Description

1

2

3

4

5

6

7

8

Output, channel 1

Negative input, channel 1

Positive input, channel 1

Negative supply

1

2

3

4

8

7

+V

S

OUT1

-IN1

+IN1

OUT2

-IN2

-V

S

6

5

+IN1

+IN2

-IN2

Positive input, channel 2

Negative input, channel 2

Output, channel 2

Positive supply

+IN2

-V

S

OUT2

+V

S

CLC4550 Pin Conﬁguration

Pin No.

Pin Name

OUT1

-IN1

Description

1

2

Output, channel 1

Negative input, channel 1

Positive input, channel 1

Positive supply

1

2

3

4

14

13

12

11

10

9

3

+IN1

OUT1

-IN1

OUT4

-IN4

4

+V

S

5

+IN2

-IN2

Positive input, channel 2

Negative input, channel 2

Output, channel 2

+IN1

+VS

+IN4

-VS

6

7

OUT2

OUT3

-IN3

8

Output, channel 3

5

6

7

+IN2

+IN3

-IN3

9

Negative input, channel 3

Positive input, channel 3

Negative supply

-IN2

10

11

12

13

14

+IN3

8

-V

S

OUT2

OUT3

+IN4

-IN4

Positive input, channel 4

Negative input, channel 4

Output, channel 4

OUT4

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2

Data Sheet

Absolute Maximum Ratings

The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device

should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper de-

vice function. The information contained in the Electrical Characteristics tables and Typical Performance plots reﬂect the

operating conditions noted on the tables and plots.

Parameter

Min

0

Max

Unit

Supply Voltage

40

50

V

Differential Input Voltage

Input Voltage

Input Current (V_IN< -0.3V) ⁽¹⁾

Output Short Circuit Current to Ground

-0.3

V

mA

Continuous

Power Dissipation (T = 25°C) - SOIC-8

660

890

mW

A

Power Dissipation (T = 25°C) - SOIC-14

A

Notes:

1. This input current will only exist when the voltage at any of the input leads is driven negative. It is due to the collector-base junction of the input PNP transistors be-

coming forward biased and thereby acting as input diode clamps. In addition to this diode action, there is also lateral NPN parasitic transistor action on the IC chip. This

transistor action can cause the output voltages of the comparators to go to the V+ voltage level (or to ground for a large overdrive) for the time duration that an input is

driven negative. This is not destructive and normal output states will re-establish when the input voltage, which was negative, again returns to a value greater than -0.3

V_DC(at 25°C).

Reliability Information

Parameter

Min

-65

Typ

Max

Unit

Junction Temperature

Storage Temperature Range

Lead Temperature (Soldering, 10s)

Package Thermal Resistance

SOIC-8

150

260

°C

100

88

°C/W

SOIC-14

Notes:

Package thermal resistance (q ), JDEC standard, multi-layer test boards, still air.

JA

Recommended Operating Conditions

Parameter

Min

Typ

Max

Unit

Operating Temperature Range

Supply Voltage Range

-40

+85

°C

V

2 (±1)

36 (±18)

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3

Data Sheet

Electrical Characteristics

T = 25°C (if bold, T = -40 to +85°C), V = +5V, -V = GND unless otherwise noted.

A

s

Symbol

Parameter

Conditions

Min

Typ

Max

Units

DC Performance

2

25

5

mV

nA

V_IO

Input Offset Voltage

Input Bias Current

Input Offset Current

V_OUT= 1.4V, R_S= 0Ω, V_S= 5V to 30V

7

250

400

50

I_b

V_CM= 0V

I_OS

200

+V_S

- 1.5

CMIR

VG

Common Mode Input Range ⁽³⁾

Voltage Gain

+V_S= 30V

0

V

50

200

0.7

V/mV

mA

+V_S= 15V, R_L= ≥15kΩ, V_OUT= 1V to 11V

R_L= ∞, +V_S= 30V

1.7

3.0

1.0

2.0

2.5

3.0

2.0

3.0

Supply Current, CLC2550

Supply Current, CLC4550

0.6

1.2

0.9

R_L= ∞, +V_S= 5V

R_L= ∞, +V_S= 30V

R_L= ∞, +V_S= 5V

I_S

Time Domain Response

t_RLSLarge Signal Response Time

V_IN= TTL logic swing, V_REF= 1.4V, V_RL= 5V,

R_L= 5.1kΩ

200

ns

1.3

0.9

0.8

μs

V_RL= 5V, R_L= 5.1kΩ, 5mV overdrive

V_RL= 5V, R_L= 5.1kΩ, 10mV overdrive

V_RL= 5V, R_L= 5.1kΩ, 15mV overdrive

t_R

Response Time

Output Characteristics

I_SINKOutput Sink Current

6.0

V_IN+= 0V, V_IN-= 1V, V_OUT= 1.5V

V_IN+= 1V, V_IN-= 0V, V_OUT= 5V

V_IN+= 1V, V_IN-= 0V, V_OUT= 30V

16

mA

nA

0.1

I_LEAK

Output Leakage Current

Saturation Voltage

1

μA

200

400

500

mV

V_SAT

V_IN+= 0V, V_IN-= 1V, I_SINK≤ 4mA

Notes:

1. 100% tested at 25°C

2. Limits over the full temperature range are guaranteed by design.

3. The input common mode voltage of either input signal voltage should be kept > 0.3V at 25°C. The upper end of the common-mode voltage range is +V - 1.5V at

S

25°C, but either or both inputs can go to +18V without damages, independent of the magnitude of V .

S

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4

Data Sheet

Typical Performance Characteristics

T = 25°C, V = +5V, -V = GND unless otherwise noted.

A

s

Supply Current vs. Supply Voltage (CLC2550)

Supply Current vs. Supply Voltage (CLC4550)

1

1.6

1.5

0.9

0.8

1.4

-40°C

1.3

1.2

0.7

25°C

0.6

1.1

1

25°C

85°C

0.5

85°C

0.4

0.9

0.8

0.7

0.6

0.5

0.3

0.2

0.1

0

4

8

12

16

20

24

28

32

0

4

8

12

16

20

24

28

32

36

Supply Voltage (V)

Supply Voltage vs. Input Bias Current (CLC2550)

Supply Voltage vs. Input Bias Current (CLC4550)

80

70

60

70

60

-40°C

50

25°C

85°C

40

30

20

10

0

-40°C

50

25°C

40

85°C

30

20

0

4

8

12

16

20

24

28

32

0

4

8

12

16

20

24

28

32

36

Supply Voltage (V)

Output Sink Current vs. Saturation Voltage (CLC2550)

Output Sink Current vs. Saturation Voltage (CLC4550)

1

85°C

0.1

0.01

85°C

25°C

0.01

-40°C

1

0.001

0.01

0.1

1

10

0.01

0.1

10

Output Sink Current (mA)

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5

Data Sheet

Typical Performance Characteristics

T = 25°C, V = +5V, -V = GND unless otherwise noted.

A

s

Response Time vs. Input Overdrive - Positive (CLC2550)

Response Time vs. Input Overdrive - Positive (CLC4550)

0.2

0.15

0.1

7

0.2

0.15

0.1

7

5.5

4

5.5

4

20mV Overdrive

50mV Overdrive

20mV Overdrive

50mV Overdrive

Input

0.05

0

2.5

1

0.05

0

2.5

1

5mV Overdrive

10mV Overdrive

5mV Overdrive

10mV Overdrive

Input

-0.05

-0.5

-0.05

-0.5

0

0.4

0.8

1.2

1.6

2

0

0.4

0.8

1.2

1.6

2

Time (us)

Response Time vs. Input Overdrive - Negative (CLC2550)

Response Time vs. Input Overdrive - Negative (CLC4550)

0.05

7

0.05

7

Input

0

5.5

4

0

5.5

4

5mV Overdrive

10mV Overdrive

5mV Overdrive

10mV Overdrive

-0.05

-0.1

-0.15

-0.2

-0.05

-0.1

-0.15

-0.2

20mV Overdrive

50mV Overdrive

20mV Overdrive

50mV Overdrive

2.5

1

2.5

1

-0.5

0

0.4

0.8

1.2

1.6

2

0

0.4

0.8

1.2

1.6

2

Time (us)

LS Response Time vs. Input Overdrive - Pos. (CLC2550)

LS Response Time vs. Input Overdrive - Pos. (CLC4550)

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

Input

Output

0

0.2

0.4

0.6

0.8

1

0

0.2

0.4

0.6

0.8

1

Time (us)

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6

Data Sheet

Typical Performance Characteristics - Continued

T = 25°C, V = +5V, -V = GND unless otherwise noted.

A

s

LS Response Time vs. Input Overdrive - Neg. (CLC2550)

LS Response Time vs. Input Overdrive - Neg. (CLC4550)

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

5.5

4.5

3.5

2.5

1.5

0.5

-0.5

Output

Input

0

0.2

0.4

0.6

0.8

1

0

0.2

0.4

0.6

0.8

1

Time (us)

Functional Block Diagram

V

CC

Q2

Q3

Q1

Q4

+Input

-Input

Output

Q8

Q7

Q5

Q6

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7

Data Sheet

proximately 60Ω RSAT of the output transistor. The low

offset voltage of the output transistor (1 mV) allows the

output to clamp essentially to ground level for small load

currents.

Application Information

The CLCx550 series are high gain, wide bandwidth de-

vices which, like most comparators, can easily oscillate

if the output lead is inadvertently allowed to capacitively

couple to the inputs via stray capacitance. This shows up

only during the output voltage transition intervals as the

comparator changes states. Power supply bypassing is not

required to solve this problem. Standard PC board layout

is helpful as it reduces stray input-output coupling. Reduc-

ing this input resistors to < 10kΩ reduces the feedback

signal levels and ﬁnally, adding even a small amount (1

to 10mV) of positive feedback (hysteresis) causes such a

rapid transition that oscillations due to stray feedback are

not possible. Simply socketing the IC and attaching resis-

tors to the pins will cause input-output oscillations during

the small transition intervals unless hysteresis is used. If

the input signal is a pulse waveform, with relatively fast

rise and fall times, hysteresis is not required.

Layout Considerations

General layout and supply bypassing play major roles

in high frequency performance. CaDeKa has evaluation

boards to use as a guide for high frequency layout and as

an aid in device testing and characterization. Follow the

steps below as a basis for high frequency layout:

• Include 6.8µF and 0.1µF ceramic capacitors for power

supply decoupling

• Place the 6.8µF capacitor within 0.75 inches of the power pin

• Place the 0.1µF capacitor within 0.1 inches of the power pin

• Remove the ground plane under and around the part,

especially near the input and output pins to reduce para-

sitic capacitance

All pins of any unused comparators should be tied to the

negative supply. The bias network of the CLCx550 series

establishes a drain current which is independent of the

magnitude of the power supply voltage over the range

of 2V DC to 30V DC. It is usually unnecessary to use a

bypass capacitor across the power supply line.

• Minimize all trace lengths to reduce series inductances

Refer to the evaluation board layouts below for more in-

formation.

Evaluation Board Information

The differential input voltage may be larger than V+ with-

out damaging the device. Protection should be provided

to prevent the input voltages from going negative more

than −0.3V DC (at 25°C). An input clamp diode can be

used as shown in the applications section.

The following evaluation boards are available to aid in the

testing and layout of these devices:

Evaluation Board #

CEB006

CEB018

Products

The output of the CLCx550 series is the uncommitted

collector of a grounded-emitter NPN output transistor.

Many collectors can be tied together to provide an output

OR’ing function. An output pull-up resistor can be con-

nected to any available power supply voltage within the

permitted supply voltage range and there is no restriction

on this voltage due to the magnitude of the voltage which

is applied to the V+ terminal of the CLCx550 package.

The output can also be used as a simple SPST switch to

ground (when a pull-up resistor is not used). The amount

of current which the output device can sink is limited by

the drive available (which is independent of V+) and the β

of this device. When the maximum current limit is reached

(approximately 16 mA), the output transistor will come

out of saturation and the output voltage will rise very rap-

idly. The output saturation voltage is limited by the ap-

CLC2550

CLC4550

Evaluation Board Schematics

Evaluation board schematics and layouts are shown in

Figures 9-14. These evaluation boards are built for dual-

supply operation. Follow these steps to use the board in a

single-supply application:

1. Short -Vs to ground.

2. Use C3 and C4, if the -V pin of the ampliﬁer is not

directly connected to the ground plane.

S

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8

Data Sheet

Figure 11. CEB006 Bottom View

Figure 9. CEB006 Schematic

Figure 10. CEB006 Top View

Figure 12. CEB018 Schematic

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9

Data Sheet

5V

3

+V

IN

+

100kΩ

V

1/4

CLCx550A

OUT

+V

REF

–

12

Figure 16. Driving CMOS

V

CC

Figure 13. CEB018 Top View

1MΩ

10kΩ

100pF

+V

IN

–

1/4

CLCx550A

V

OUT

+

0.001µF

1MΩ

Figure 17. One Shot Multivibrator

Figure 14. CEB018 Bottom View

V

CC

Typical Applications

4.3kΩ

100kΩ

V

CC

75pF

–

3kΩ

1/4

CLCx550A

+V

IN

V

OUT

+

1/4

CLCx550

+

V

OUT

+V

REF

–

100kΩ

V

IN

100kΩ

Figure 15. Basic Comparator

Figure 18. Squarewave Oscillator

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10

Data Sheet

Mechanical Dimensions

SOIC-8 Package

SOIC-14 Package

For additional information regarding our products, please visit CADEKA at: cadeka.com

CADEKA Headquarters Loveland, Colorado

T: 970.663.5452

T: 877.663.5452 (toll free)

CADEKA, the CADEKA logo design, COMLINEAR, the COMLINEAR logo design, and ARCTIC are trademarks or registered trademarks of

CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies.

CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any

responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in

writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights,

copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties.

Amplify the Human Experience


型号：	CLC2550ISO8X
厂家：	CADEKA MICROCIRCUITS LLC.
描述：	Low Power, Low Offset, 2V to 36V Comparators 低功耗，低失调， 2V至36V比较器比较器
文件：	总11页 (文件大小：1534K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CLC2550ISO8X [CADEKA]

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