SPT7734SCT [CADEKA]
8-BIT, 40 MSPS,175 mW A/D CONVERTER; 8位， 40 MSPS ， 175 mW的A / D转换器
| 型号： | SPT7734SCT |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 8-BIT, 40 MSPS,175 mW A/D CONVERTER |
| 文件： | 总9页 (文件大小：191K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7734
8-BIT, 40 MSPS,175 mW A/D CONVERTER
APPLICATIONS
FEATURES
• Monolithic 40 MSPS Converter
• 175 mW Power Dissipation
• On-Chip Track-and-Hold
• Single +5 V Power Supply
• TTL/CMOS Outputs
• All High-Speed Applications Where
Low Power Dissipation is Required
• Video Imaging
• Medical Imaging
• Radar Receivers
• 5 pF Input Capacitance
• Low Cost
• IR Imaging
• Digital Communications
• Tri-State Output Buffers
• High ESD Protection: 3,500 V Minimum
• Selectable +3 V or +5 V Logic I/O
GENERAL DESCRIPTION
are +3 V or +5 V, and are user selectable. The SPT7734 has
incorporated proprietary circuit design and CMOS process-
ing technologies to achieve its advanced performance. In-
putsandoutputsareTTL/CMOScompatibletointerfacewith
TTL/CMOS logic systems. Output data format is straight
binary.
The SPT7734 is a 8-bit monolithic, low cost, ultralow power
analog-to-digital converter capable of minimum word rates
of 40 MSPS. The on-chip track-and-hold function assures
very good dynamic performance without the need for exter-
nal components. The input drive requirements are mini-
mized due to the SPT7734's low input capacitance of only
5 pF.
TheSPT7734isavailablein28-leadSOICand32-leadsmall
(7 mm square) TQFP packages over the commercial tem-
perature range.
Power dissipation is extremely low at only 175 mW typical at
40 MSPS with a power supply of +5.0 V. The digital outputs
BLOCK DIAGRAM
ADC Section 1
Auto-
1:16
Mux
9-Bit
SAR
9
Zero
T/H
A
IN
CMP
D8 Overrange
9
D7 (MSB)
DAC
P1
P2
D6
9
ADC Section 2
.
.
.
.
.
.
CLK In
Enable
.
.
.
.
.
.
D5
Timing
and
Control
9-Bit
16:1
Mux/
Error
Correction
P15
9
ADC Section 15
D4
P16
ADC Section 16
9
D3
Auto-
Zero
CMP
9-Bit
SAR
T/H
Data
Vali
d
D2
9
D1
DAC
DØ (LSB)
Ref
In
Reference Ladder
V
REF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
AV .........................................................................+6 V
Output
Digital Outputs .......................................................10 mA
DD
DV
........................................................................+6 V
DD
Temperature
Input Voltages
Analog Input.................................. -0.5 V to AV
Operating Temperature ................................. 0 to +70 °C
Junction Temperature ......................................... +175 °C
Lead Temperature, (soldering 10 seconds) ........ +300 °C
Storage Temperature................................ -65 to +150 °C
+0.5 V
DD
V
REF
............................................................................0 to AV
DD
CLK Input .................................................................. V
DD
AV - DV ............................................................... ±100 mV
DD DD
AGND - DGND ...................................................±100 mV
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T =T
A
to T
, AV =DV =+5.0 V, V =0 to 4 V, f =40 MSPS, V
=4.0 V, V =0.0 V, unless otherwise specified.
RLS
MAX
MAX
DD
DD
IN
S
RHS
TEST
TEST
SPT7734
PARAMETERS
Resolution
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
8
Bits
DC Accuracy
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
IV
IV
VI
±1.0
±0.5
Guaranteed
LSB
LSB
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
VI
IV
V
V
V
V
V
RHS
V
kΩ
pF
MHz
LSB
LSB
RLS
50
5.0
(Small Signal)
250
±2.0
±2.0
Gain Error
V
Reference Input
Resistance
Bandwidth
Voltage Range
VI
V
300
100
500
150
600
2.0
Ω
MHz
V
RLS
V
RHS
V
RHS
IV
IV
V
V
V
0
3.0
1.0
-
-
V
V
V
mV
mV
AV
DD
- V
4.0
90
75
5.0
RLS
)
)
∆(V
∆(V
- V
RHF
RLS
RHS
- V
RLF
Reference Settling Time
V
RHS
V
RLS
V
V
15
20
Clock Cycles
Clock Cycles
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
VI
IV
IV
V
40
2
MHz
MHz
12
Clock Cycles
4.0
30
ns
ps(p-p)
Aperture Jitter Time
V
Dynamic Performance
Effective Number of Bits
f
f
=3.58 MHz
IN
=10.3 MHz
IN
VI
VI
7.3
7.2
7.8
7.7
Bits
Bits
SPT7734
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1/27/98
ELECTRICAL SPECIFICATIONS
T =T
to T
, AV =DV =+5.0 V, V =0 to 4 V, f =40 MSPS, V
=4.0 V, V =0.0 V, unless otherwise specified.
RLS
A
MAX
MAX
DD
DD
IN
S
RHS
TEST
CONDITIONS
TEST
LEVEL
SPT7734
PARAMETERS
MIN
TYP
MAX
UNITS
Dynamic Performance
Signal-to-Noise Ratio
(without Harmonics)
f
f
=3.58 MHz
=10.3 MHz
VI
VI
46
45
49
48
dB
dB
IN
IN
Harmonic Distortion
9 Distortion bins from
1024 pt FFT
f
f
=3.58 MHz
=10.3 MHz
VI
VI
53
53
57
56
dB
dB
IN
IN
Signal-to-Noise and Distortion
(SINAD)
f
f
=3.58 MHz
IN
=10.3 MHz
IN
VI
VI
46
45
49
48
dB
dB
Spurious Free Dynamic Range
Differential Phase
Differential Gain
f
=1.0 MHz
IN
V
V
V
63
±0.3
±0.3
TBD
dB
Degree
%
Intermodulation Distortion
dB
Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
VI
VI
VI
VI
V
2.0
V
V
µA
µA
pF
0.8
+10
+10
-10
-10
+5
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
I
I
= 0.5 mA
= 1.6 mA
VI
VI
V
V
V
3.5
V
V
ns
ns
ns
ns
OH
OL
0.4
t
t
15 pF load
15 pF load
10
10
10
22
RISE
FALL
Output Enable to Data Output Delay 20 pF load, T = +25 °C
A
50 pF load over temp.
V
Power Supply Requirements
Voltages
OV
DV
IV
IV
IV
VI
VI
VI
3.0
4.75
4.75
5.0
5.25
5.25
22
23
225
V
V
V
mA
mA
mW
DD
DD
DD
5.0
5.0
17
18
175
AV
AI
Currents
DD
DI
DD
Power Dissipation
TEST LEVEL
TEST PROCEDURE
100% production tested at the specified temperature.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
II
100% production tested at T =25 °C, and sample
A
tested at the specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = 25 °C. Parameter is
A
guaranteed over specified temperature range.
SPT7734
3
1/27/98
Figure 1A: Timing Diagram 1
1
11
13
9
3
17
ANALOG IN
CLOCK IN
7
15
5
SAMPLING
CLOCK
(Internal)
INVALID
VALID
DATA OUTPUT
DATA VALID
1
2
3
4
5
Figure 1B: Timing Diagram 2
tCLK
tC
tCH
tCL
CLOCK IN
Data Ø
Data 1
Data 2
Data 3
DATA
OUTPUT
tOD
tS
tCH
tCL
DATA
VALID
tS
Table I - Timing Parameters
DESCRIPTION
PARAMETERS
MIN
TYP
MAX
UNITS
Conversion Time
Clock Period
tC
t
ns
ns
%
CLK
t
25
40
40
CLK
Clock High Duty Cycle
Clock Low Duty Cycle
tCH
50
50
17
10
60
60
tCL
tOD
tS
%
Clock to Output Delay (15 pF Load)
Clock to DAV
ns
ns
SPT7734
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1/27/98
TYPICAL INTERFACE CIRCUIT
The high sample rate is achieved by using multiple SAR ADC
sections in parallel, each of which samples the input signal in
sequence. Each ADC uses 16 clock cycles to complete a
conversion. The clock cycles are allocated as follows:
Very few external components are required to achieve the
stated device performance. Figure 1 shows the typical inter-
face requirements when using the SPT7734 in normal circuit
operation. The following sections provide descriptions of the
major functions and outline critical performance criteria to
consider for achieving the optimal device performance.
Table II - Clock Cycles
Clock
Operation
1
2
3
4
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
Figure 1 - Typical Interface Circuit
Ref In
(+4 V)
V
V
RHF
D8
5-15
16
9-bit SAR conversion
Data transfer
RHS
V
V
V
V
RLS
RLF
IN
The 16 phase clock, which is derived from the input clock,
synchronizes these events. The timing signals for adjacent
ADCsectionsareshiftedbyoneclockcyclesothattheanalog
input is sampled on every cycle of the input clock by exactly
one ADC section. After 16 clock periods, the timing cycle
repeats. The latency from analog input sample to the corre-
sponding digital output is 12 clock cycles.
Interfacing
Logics
SPT7734
V
IN
D0
EN
CAL
CLK
CLK IN
DAV
AV
DV
AGND DGND*
DD
DD
• Sinceonly16comparatorsareused, ahugepowersavings
is realized.
FB1
FB2
+D5
• The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparators
response to a reference zero.
Enable/Tri-State
(Enable = Active Low)
+A5
FB3
AGND
DGND
+D5
• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of the
gain error are integratedtoproduceacalibrationvoltagefor
each ADC section.
+A5
+
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
+
10 µF
10 µF
+5 V
Analog
+5 V
Analog
RTN
+5 V
Digital
RTN
+5 V
Digital
• Capacitive displacement currents, which can induce sam-
pling error, are minimized since only one comparator
samples the input during a clock cycle.
NOTES: 1) FB3 is to be located as closely to the device as possible.
2) There should be no additional connections to the right of FB1 and FB2.
3) All capacitors are 0.1 µF surface-mount unless otherwise specified.
4) FB1, FB2 and FB3 are 10 µH inductors or ferrite beads.
• The total input capacitance is very low since sections of the
converter which are not sampling the signal are isolated
from the input by transmission gates.
POWER SUPPLIES AND GROUNDING
CADEKA suggests that both the digital and the analog supply
voltages on the SPT7734 be derived from a single analog
supply as shown in figure 1. A separate digital supply should
be used for all interface circuitry. CADEKA suggests using
this power supply configuration to prevent a possible latch-
up condition on power up.
VOLTAGE REFERENCE
The SPT7734 requires the use of a single external voltage
reference for driving the high side of the reference ladder. It
must be within the range of 3 V to 5 V. The lower side of the
ladder is typically tied to AGND (0.0 V), but can be run up to
2.0 V with a second reference. The analog input voltage
range will track the total voltage difference measured be-
OPERATING DESCRIPTION
tween the ladder sense lines, V
and V
.
RLS
RHS
The general architecture for the CMOS ADC is shown in the
block diagram. The design contains 16 identical successive
approximation ADC sections, all operating in parallel, a 16-
phase clock generator, an 9-bit 16:1 digital output multi-
plexer, correction logic, and a voltage reference generator
whichprovidescommonreferencelevelsforeachADCsection.
Force and sense taps are provided to ensure accurate and
stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations. By
using the configuration shown in figure 2, offset and gain
errors of less than ±2 LSB can be obtained.
SPT7734
5
1/27/98
Figure 2 - Ladder Force/Sense Circuit
Figure 3 - Simplified Reference Ladder Drive Circuit
Without Force/Sense Circuit
1
AGND
+4.0 V
External
Reference
90 mV
R/2
+
-
2
3
V
V
V
RHF
RHS
(+3.91 V)
R
RHS
R
R
4
5
N/C
V
R=30 Ω (typ)
All capacitors are 0.01 µF
R
RLS
-
+
R
R
6
7
V
RLF
V
RLS
(0.075 V)
75 mV
R/2
V
IN
V
(AGND)
RLF
0.0 V
All capacitors are 0.01 µF
In cases where wider variations in offset and gain can be
tolerated, V can be tied directly to V and AGND can be
Thedriverequirementsfortheanaloginputsareveryminimal
whencomparedtomostotherconvertersduetotheSPT7734's
extremely low input capacitance of only 5 pF and very high
input resistance in excess of 50 kΩ.
Ref
RHF
tied directly to V
as shown in figure 3. Decouple force and
RLF
sense lines to AGND with a .01 µF capacitor (chip cap
preferred) to minimize high-frequency noise injection. If this
simplified configuration is used, the following considerations
should be taken into account:
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 4.
The reference ladder circuit shown in figure 3 is a simplified
representation of the actual reference ladder with force and
sense taps shown. Due to the actual internal structure of the
CALIBRATION
The SPT7734 uses an auto calibration scheme to en-
sure 8-bit accuracy over time and temperature. Gain and
offseterrorsarecontinuallyadjustedto8-bitaccuracyduring
device operation. This process is completely transparent to
the user.
ladder, the voltage drop from V
to V
is not equivalent
RHF
RHS
to the voltage drop from V
to V
.
RLF
RLS
Typically, the top side voltage drop for V
equal:
to V
will
RHS
RHF
Upon power-up, the SPT7734 begins its calibration algo-
rithm. In order to achieve the calibration accuracy required,
the offset and gain adjustment step size is a fraction of a 8-
bit LSB. Since the calibration algorithm is an oversampling
process, a minimum of 10,000 clock cycles are required.
This results in a minimum calibration time upon power-up
of 250 µsec (for a 40 MHz clock). Once calibrated, the
SPT7734 remains calibrated over time and temperature.
V
RHF
- V
= 2.25 % of (V
- V
) (typical),
RHS
RHF
RLF
and the bottom side voltage drop for V
- V = 1.9 % of (V - V
to V
will equal:
RLF
RLS
V
) (typical).
RLS
RLF
RHF
RLF
Figure 3 shows an example of expected voltage drops for a
specific case. Vref of 4.0 V is applied to V and V is tied
RHF
RLF
to AGND. A 90 mV drop is seen at V
(= 3.91 V) and a
RHS
Since the calibration cycles are initiated on the rising edge of
the clock, the clock must be continuously applied for the
SPT7734 to remain in calibration.
75 mV increase is seen at V
(= 0.075 V).
RLS
ANALOG INPUT
VIN is the analog input. The input voltage range is from VRLS
to VRHS (typically 4.0 V) and will scale proportionally with
respect to the voltage reference. (See voltage reference
section.)
INPUT PROTECTION
All I/O pads are protected with an on-chip protection circuit
shown in figure 5. This circuit provides ESD robustness to
3.5 kV and prevents latch-up under severe discharge condi-
tions without degrading analog transition times.
SPT7734
6
1/27/98
Figure 4 - Recommended Input Protection Circuit
CLOCK INPUT
The SPT7734 is driven from a single-ended TTL-input clock.
Because the pipelined architecture operates on the rising edge of
the clock input, the device can operate over a wide range of input
clock duty cycles without degrading the dynamic performance.
+V
AV
DD
DIGITAL OUTPUTS
D1
D2
The digital outputs (D0-D8) are driven by a separate supply
(OVDD) ranging from +3 V to +5 V. This feature makes it
possible to drive the SPT7734's TTL/CMOS-compatible out-
puts with the user's logic system supply. The format of the
output data (D0-D7) is straight binary. (See table III.) The
outputs are latched on the rising edge of CLK. These outputs
Buffer
ADC
47 Ω
can be switched into a tri-state mode by bringing
high.
EN
-V
Table III - Output Data Information
D1 = D2 = Hewlett Packard HP5712 or equivalent
ANALOG INPUT
OVERRANGE
D8
OUTPUT CODE
D7-D0
+F.S. + 1/2 LSB
+F.S. -1/2 LSB
+1/2 F.S.
1
1111 1111
1111 111Ø
ØØØØ ØØØØ
OOOO OOOØ
OOOO OOOO
O
O
O
O
Figure 5 - On-Chip Protection Circuit
+1/2 LSB
V
DD
0.0 V
(Ø indicates the flickering bit between logic 0 and 1).
Analog
120 Ω
120 Ω
DO NOT CONNECT PINS (DNC)
There are two pins designated as Do Not Connect (DNC).
These pins must be left floating for proper operation of the
device.
Pad
OVERRANGE OUTPUT
The OVERRANGE OUTPUT (D8) is an indication that the
analog input signal has exceeded the positive full scale input
voltage by 1 LSB. When this condition occurs, D8 will switch
to logic 1. All other data outputs (D0 to D7) will remain at
logic 1 as long as D8 remains at logic 1. This feature makes
it possible to include the SPT7734 into higher resolution
systems.
SPT7734
7
1/27/98
PACKAGE OUTLINES
32-Lead TQFP
INCHES
MIN
MILLIMETERS
MIN MAX
8.90
A
B
SYMBOL
MAX
0.355
G H
A
B
C
D
E
F
G
H
I
0.347
0.269
0.347
0.269
0.027
0.012
0.053
0.002
0.039 typ
0.004
0°
9.10
7.10
9.10
7.10
0.89
0.45
1.45
0.15
0.277
0.355
0.277
0.035
0.018
0.057
0.006
6.90
8.90
6.90
0.68
0.30
C
D
1.35
0.05
1.00 typ
0.09
J
0.008
7°
0.20
7°
K
L
0°
I
0.018
0.029
0.45
0.75
J
E
F
K
L
28-Lead SOIC
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
MAX
A
B
C
D
E
F
G
H
I
0.696
0.004
0.712
0.012
.050 typ
0.019
0.012
0.100
0.050
0.419
0.299
17.68
0.10
0.00
0.36
0.23
2.03
0.41
10.01
7.39
18.08
0.30
1.27
0.48
0.30
2.54
1.27
10.64
7.59
28
0.014
0.009
0.080
0.016
0.394
0.291
I
H
1
A
H
F
B
C
D
G
E
SPT7734
8
1/27/98
PIN ASSIGNMENTS
PIN FUNCTIONS
Name
Function
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
D8
D7
D6
D5
D4
D3
OV
AGND
2
V
RHF
AGND
Analog Ground
3
4
V
RHS
N/C
V
V
V
V
V
V
Reference High Force
Reference High Sense
Reference Low Sense
Reference Low Force
Calibration Reference
Analog Input
RHF
RHS
RLS
RLF
CAL
IN
5
V
RLS
6
V
RLF
7
V
IN
DD
SOIC
AGND
8
OGND
D2
V
9
CAL
10
AV
D1
DD
1
1
DV
DD
D0
AV
DV
Analog V
DD
DD
DD
DGND 12
DNC
CLK
13
Digital V
DNC
EN
DD
DAV 14
DGND
CLK
Digital Ground
Input Clock f
=fs (TTL)
CLK
Output Enable
EN
D0-7
Tri-State Data Output, (DØ=LSB)
Tri-State Output Overrange
Data Valid Output
V
RLF
1
2
3
4
5
6
7
8
24 D5
23 D4
22 D3
21 OV
D8
V
IN
DAV
AGND
AGND
OV
DD
Digital Output Supply
Digital Output Ground
Do Not Connect
DD
TQFP
V
CAL
20 OGND
19 D2
OGND
DNC
AV
D
D
AV
D
18 D1
D
DV
DD
17 D0
ORDERING INFORMATION
PART NUMBER
SPT7734SCS
SPT7734SCT
TEMPERATURE RANGE
0 to +70 °C
PACKAGE TYPE
28L SOIC
0 to +70 °C
32L TQFP
SPT7734
9
1/27/98
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