SPT7824ACN [CADEKA]
10-BIT, 40 MSPS, TTL OUTPUT A/D CONVERTER; 10位， 40 MSPS ， TTL输出A / D转换器
| 型号： | SPT7824ACN |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 10-BIT, 40 MSPS, TTL OUTPUT A/D CONVERTER |
| 文件： | 总11页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7824
10-BIT, 40 MSPS, TTL OUTPUT A/D CONVERTER
APPLICATIONS
FEATURES
• Medical Imaging
• Monolithic 40 MSPS Converter
• On-Chip Track/Hold
• Professional Video
• Radar Receivers
• Instrumentation
• Electronic Warfare
• Digital Communications
• Bipolar ±2.0 V Analog Input
• 57 dB SNR @ 3.58 MHz Input
• Low Power (1.0 W Typical)
• 5 pF Input Capacitance
• TTL Outputs
GENERAL DESCRIPTION
The SPT7824 A/D converter is a 10-bit monolithic converter
capable of word rates a minimum of 40 MSPS. On board
track/hold function assures excellent dynamic performance
without the need for external components. Drive require-
ment problems are minimized with an input capacitance of
only 5 pF.
indicate overflow conditions. Output data format is straight
binary. Power dissipation is very low at only 1.0 watt with
power supply voltages of +5.0 and -5.2 volts. The SPT7824
also provides a wide input voltage swing of ±2.0 volts.
The SPT7824 is available in 28-lead ceramic sidebrazed DIP,
PDIP andSOIC packages over the commercial,industrialand
military temperature ranges. Consult the factory for availabil-
ity of die and /833 versions.
Inputs and outputs are TTL compatible to interface with TTL
logic systems. An overrange output signal is provided to
BLOCK DIAGRAM
Analog
Coarse
Input
4
A/D
Analog
Prescaler
T/H Amplifier
Bank
Digital
Output
10
Successive Interpolation
Stage i
Successive Interpolation
Stage i+1
Successive Interpolation
Stage N
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Output
Digital Outputs .......................................... +30 to -30 mA
V
CC
V
EE
...........................................................................+6 V
........................................................................... -6 V
Temperature
Input Voltages
Analog Input............................................... V ≤V ≤V
Operating Temperature ............................ -55 to +125 °C
Junction Temperature .............................................. +175 °C
Lead Temperature, (soldering 10 seconds) ........ +300 °C
Storage Temperature................................ -65 to +150 °C
1
FB IN FT
, V ..............................................................+3.0 V, -3.0 V
V
FT FB
Reference Ladder Current .....................................12 mA
CLK Input .................................................................. V
CC
Note: 1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T =T
A
- T
, V =+5.0 V, V =-5.2 V, DV =+5.0 V, V =±2.0 V, V =-2.0 V, V =+2.0 V, f
=40 MHz, 50% clock duty cycle, unless otherwise
CLK
MIN
MAX CC
EE
CC
IN
SB
ST
specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7824A
TYP
SPT7824B
TYP MAX UNITS
PARAMETERS
MIN
MAX
MIN
Resolution
10
10
Bits
±
DC Accuracy (+25 °C)
Integral Nonlinearity
Differential Nonlinearity
No Missing Codes
Full Scale
100 kHz Sample Rate
V
V
±1.0
±0.5
±1.5
±0.75
LSB
LSB
VI
Guaranteed
Guaranteed
Analog Input
f
=1 MHz
=0 V
CLK
Input Voltage Range
Input Bias Current
Input Bias Current
Input Resistance
Input Resistance
Input Capacitance
Input Bandwidth
+FS Error
V
VI
IV
VI
IV
V
±2.0
30
±2.0
V
V
60
75
30
60 µA
75 µA
kΩ
IN
T =-55 to +125 °C
A
100
75
300
300
5
100
75
300
300
5
T =-55 to +125 °C
kΩ
pF
A
3 dB Small Signal
V
V
V
120
±2.0
±2.0
120
±2.0
±2.0
MHz
LSB
LSB
-FS Error
Reference Input
f
=1 MHz
CLK
Reference Ladder Resistance
Reference Ladder Tempco
VI
V
500
40
800
0.8
500
800
0.8
Ω
Ω/°C
Timing Characteristics
Maximum Conversion Rate
Overvoltage Recovery Time
Pipeline Delay (Latency)
Output Delay
VI
V
IV
V
V
V
40
14
MHz
ns
20
20
1
18
1
Clock Cycle
T =+25 °C
14
1
5
18 ns
ns
A
Aperture Delay Time
Aperture Jitter Time
Acquisition Time
T =+25 °C
1
5
12
A
T =+25 °C
ps-RMS
ns
A
T =+25 °C
A
V
12
Dynamic Performance
Effective Number of Bits
f
f
f
=1 MHz
=3.58 MHz
=10.0 MHz
8.7
8.7
7.3
8.2
8.2
6.9
Bits
Bits
Bits
IN
IN
IN
Typical thermal impedances (unsoldered, in free air): 28L sidebrazed DIP: θ = 50 °C/W, 28L plastic DIP: θ = 50°C/W,
ja
ja
28L SOIC: θ = 100 °C/W.
ja
SPT7824
2
3/11/97
ELECTRICAL SPECIFICATIONS
T =T -T
, V =+5.0 V, V =-5.2 V, DV =+5.0 V, V =±2.0 V, V =-2.0 V, V =+2.0 V, f
=40 MHz, 50% clock duty cycle unless otherwise specified.
CLK
A
MIN MAX CC
EE
CC
IN
SB
ST
TEST
CONDITIONS
TEST
LEVEL
SPT7824A
SPT7824B
TYP
PARAMETERS
MIN
TYP
MAX
MIN
MAX UNITS
Dynamic Performance
Signal-To-Noise Ratio
(without Harmonics)
f
f
f
=1 MHz
T =+25 °C
I
55
53
49
55
53
49
48
45
41
57
55
51
57
55
51
50
47
43
52
50
46
52
50
46
46
43
39
54
52
48
54
52
48
48
45
41
dB
dB
dB
dB
dB
dB
dB
dB
dB
IN
IN
IN
A
T =0 to +70, -25 to +85 °C
IV
IV
I
IV
IV
I
A
T =-55 to +125 °C*
A
=3.58 MHz
=10.0 MHz
T =+25 °C
A
T =0 to 70, -25 to +85 °C
A
T =-55 to +125 °C*
A
T =+25 °C
A
T =0 to 70, -25 to +85 °C
IV
IV
A
T =-55 to +125 °C*
A
Harmonic Distortion
f
f
f
=1 MHz
T =+25 °C
I
54
51
50
54
51
50
46
45
44
56
53
52
56
53
52
48
47
46
52
49
48
52
49
48
43
41
40
54
51
50
54
51
50
45
44
42
dB
dB
dB
dB
dB
dB
dB
dB
dB
IN
IN
IN
A
T =0 to 70, -25 to +85 °C
IV
IV
I
IV
IV
I
A
T =-55 to +125 °C*
A
=3.58 MHz
=10.0 MHz
T =+25 °C
A
T =0 to 70, -25 to +85 °C
A
T =-55 to +125 °C*
A
T =+25 °C
A
T =0 to 70, -25 to +85 °C
IV
IV
A
T =-55 to +125 °C*
A
Signal-to-Noise and Distortion
f
f
f
=1 MHz
T =+25 °C
I
52
49
48
52
49
48
44
43
40
54
54
46
49
46
45
49
46
45
41
40
37
51
51
43
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Degree
%
IN
IN
IN
A
T =0 to 70, -25 to +85 °C
IV
IV
I
IV
IV
I
IV
IV
V
A
T =-55 to +125 °C*
A
=3.58 MHz
=10.0 MHz
T =+25 °C
A
T =0 to 70, -25 to +85 °C
A
T =-55 to +125 °C*
A
T =+25 °C
A
T =0 to 70, -25 to +85 °C
A
T =-55 to +125 °C*
A
Spurious Free Dynamic Range T =+25 °C, f =1 MHz
Differential Phase
Differential Gain
67
0.2
0.5
67
0.2
0.7
A
IN
T =+25 °C, f = 3.58 & 4.35 MHz
V
V
A
IN
T =+25 °C, f = 3.58 & 4.35 MHz
A
IN
Digital Inputs
f
=1 MHz
CLK
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low T =+25 °C
Maximum Input Current High T =+25 °C
Pulse Width Low (CLK)
Pulse Width High (CLK)
VI
VI
I
I
IV
IV
2.4
4.5
0.8
+20
+20
2.4
4.5
0.8
+20 µA
+20 µA
ns
V
V
0
0
10
10
+5
+5
0
0
10
10
+5
+5
A
A
300
300 ns
Digital Outputs
Logic "1" Voltage
f
=1 MHz
CLK
VI
VI
2.4
2.4
V
V
Logic "0" Voltage
0.6
0.6
Power Supply Requirements
VoltagesV
IV
IV
IV
I
I
I
4.75
4.75
-4.95
5.25
5.25
-5.45 -4.95
145
55
57
4.75
4.75
5.25
5.25
-5.45
145 mA
55 mA
57 mA
V
V
V
CC
DV
-V
5.0
-5.2
118
40
5.0
-5.2
118
40
CC
EE
Currents I
T =+25 °C
CC
A
DI
T =+25 °C
CC
A
-I
T =+25 °C
A
40
40
EE
Power Dissipation
Power Supply Rejection
T =+25 °C
+5 V ±0.25 V, -5.2 V ±0.25 V
I
V
1.0
1.0
1.3
1.0
1.0
1.3
W
LSB
A
*Temperature tested /883 only.
SPT7824
3
3/11/97
TEST LEVEL CODES
TEST LEVEL
TEST PROCEDURE
All electrical characteristics are subject to the
following conditions:
I
100% production tested at the specified temperature.
II
100% production tested at T = +25 °C, and sample
A
tested at the specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = +25 °C. Parameter is
A
guaranteed over specified temperature range.
Figure 1A - Timing Diagram
N+1
N
N+2
t
t
pwH
pwL
CLK
t
d
Output
N-2
N-1
Data Valid
N
Data Valid
N+1
Data
Figure 1B - Single Event Clock
CLK
t
d
Output
Data
Data Valid
Table I - Timing Parameters
PARAMETERS
DESCRIPTION
MIN
-
TYP
MAX
18
UNITS
ns
t
t
CLK to Data Valid Prop Delay
CLK High Pulse Width
14
-
d
10
300
ns
pwH
t
CLK Low Pulse Width
10
-
-
ns
pwL
SPT7824
4
3/11/97
TYPICAL PERFORMANCE CHARACTERISTICS
THD vs Input Frequency
SNR vs Input Frequency
80
70
60
50
40
80
70
f
= 40 MSPS
s
fs = 40 MSPS
60
50
40
30
20
30
20
0
0
1
2
10
1
2
10
10
10
10
10
Input Frequency (MHz)
Input Frequency (MHz)
SNR, THD, SINAD vs Sample Rate
SINAD vs Input Frequency
80
70
80
70
fs =40 MSPS
SNR
60
50
60
50
SINAD
f
= 1 MHz
IN
THD
40
40
30
20
30
20
0
1
2
10
10
10
0
1
2
10
10
10
Input Frequency (MHz)
Sample Rate (MSPS)
Spectral Response
SNR, THD, SINAD vs Temperature
65
0
f
f
= 40 MSPS
= 1 MHz
S
IN
60
55
-30
-60
-90
SNR
THD
SINAD
50
f
f
= 40 MSPS
= 1 MHz
S
IN
45
40
-120
-25
0
+25
Temperature (°C)
+50
+75
0
1
2
3
4
5
6
7
8
9
10
Input Frequency (MHz)
SPT7824
5
3/11/97
AGND and DGND are the two grounds available on the
SPT7824. These two internal grounds are isolated on the
device.Theuseofgroundplanesisrecommendedtoachieve
TYPICAL INTERFACE CIRCUIT
The SPT7824 requires few external components to achieve
the stated operation and performance. Figure 2 shows the
typical interface requirements when using the SPT7824 in
normal circuit operation. The following section provides a
description of the pin functions and outlines critical perfor-
mance criteria to consider for achieving the optimal device
performance.
optimumdeviceperformance. DGNDisneededfortheDV
CC
returnpath(40mAtypical)andforthereturnpathforalldigital
output logic interfaces. AGND and DGND should be sepa-
rated from each other and connected together only at the
device through a ferrite bead.
A Schottky or hot carrier diode connected between AGND
and V
is required. The use of separate power supplies
EE
POWER SUPPLIES AND GROUNDING
betweenV andDV isnotrecommendedduetopotential
CC
CC
power supply sequencing latch-up conditions. Using the
recommended interface circuit shown in figure 2 will provide
optimum device performance for the SPT7824.
The SPT7824 requires -5.2 V and +5 V analog supply
voltages. The +5 V supply is common to analog V
and
CC
digital DV . A ferrite bead in series with each supply line is
CC
intendedtoreducethetransientnoiseinjectedintotheanalog
V
CC
. These beads should be connected as closely as pos-
sible to the device. The connection between the beads and
the SPT7824 should not be shared with any other device.
Each power supply pin should be bypassed as closely as
possible to the device. Use 0.1 µF for V
and V , and
EE
CC
0.01 µF for DV
(chip caps are preferred).
CC
Figure 2 - Typical Interface Circuit
R1
CLK
CLK
(TTL)
100 Ω
V
4
± 2.5 V Max
IN
D10 (Overrange)
D9 (MSB)
COARSE
A/D
V
(±2 V)
IN
2
6
V
D8
D7
D6
D5
V
FT
ST
+2.5 V
C1
.01 µF
+ 5 V
IC1
V
IN
+
OUT
(REF-03)
C19
5
+
ANALOG
PRESCALER
1 µF
4
C2
R
Trim
10 kΩ
V
GND
.01 µF
1 µF
30 kΩ
2R
2R
2R
2R
D4
D3
C3
.01 µF
SUCCESSIVE
INTERPOLATION
STAGE # 1
V
RM
3
2
- 5.2 V
D2
D1
1
+
-
IC2
4
10 kΩ
OP-07
30 kΩ
C4
.01 µF
.01 µF
V
V
D0 (LSB)
8
SB
FB
+5 V
SUCCESSIVE
INTERPOLATION
STAGE # N
7
R
.01 µF
6
-2.5 V
C5
.01 µF
1 µF
+
C10
.01 µF
C6
.1 µF
C8
C9
C7
C11
.1 µF
.01 µF
Notes to prevent latch-up due to power sequencing:
FB
1)
2)
D1 = Schottky or hot carrier diode, P/N IN5817.
FB = Ferrite bead, Fair Rite P/N 2743001111
D1
10 µF
10 µF
to be mounted as close to the device as possible. The ferrite bead to the
ADC connection should not be shared with any other device.
+
+
3)
C1-C11 = Chip cap (recommended) mounted as close to the device's pin
as possible.
+5 V
(Analog)
4)
5)
6)
7)
Use of a separate supply for V
CC
R1 provides current limiting to 45 mA.
and DV is not recommended.
CC
-5.2 V
(Analog)
AGND
DGND
C6, C7, C8 and C9 should be ten times larger than C10 and C11.
C8 = C9 = a 0.1 µF cap in parallel with a 4.7 µF cap.
SPT7824
6
3/11/97
VOLTAGE REFERENCE
ever, because the device is laser trimmed to optimize perfor-
mancewith ± 2.5Vreferences, theaccuracyofthedevicewill
degrade if operated beyond a ± 2% range.
The SPT7824 requires the use of two voltage references:
VFT and VFB. VFT is the force for the top of the voltage
reference ladder (+2.5 V typ), VFB (-2.5 V typ) is the force for
thebottomofthevoltagereferenceladder. Bothvoltagesare
applied across an internal reference ladder resistance of
The following errors are defined:
+FS error = top of ladder offset voltage = ∆(+FS -V +1LSB)
ST
-FSerror=bottomofladderoffsetvoltage=∆(-FS-V -1LSB)
SB
800 ohms. The +2.5 V voltage source for reference V must
FT
where the +FS (full scale) input voltage is defined as the
output transition between 1-10 and 1-11 and the -FS input
voltage is defined as the output transition between 0-00 and
0-01.
be current limited to 20 mA maximum if a different driving
circuit is used in place of the recommended reference circuit
shown in figures 2 and 3. In addition, there are three
referenceladdertaps(VST, VRM andVSB). VST isthesensefor
the top of the reference ladder (+2.0 V), VRM is the midpoint
of the ladder (0.0 V typ) and VSB is the sense for the bottom
ofthereferenceladder(-2.0V).ThevoltagesseenatVST and
VSB are the true full scale input voltages of the device when
VFT and VFB are driven to the recommended voltages (+2.5 V
and-2.5Vtypicalrespectively). Thesepointsshouldbeused
to monitor the actual full scale input voltage of the device and
should not be driven to the expected ideal values as is
commonly done with standard flash converters. When not
being used, a decoupling capacitor of .01 uF (chip carrier
preferred) connected to AGND from each tap is recommended
to minimize high frequency noise injection.
ANALOG INPUT
VIN is the analog input. The full scale input range will be 80% of
the reference voltage or ±2 V with VFB=-2.5 V and VFT=+2.5 V.
The drive requirements for the analog inputs are minimal
when compared to conventional Flash converters due to the
SPT7824’s extremely low input capacitance of only 5 pF and
veryhighinputresistanceof300kΩ.Forexample,foraninput
signalof±2Vp-pwithaninputfrequencyof10MHz, thepeak
output current required for the driving circuit is only 628 µA.
CLOCK INPUT
Figure 3 - Analog Equivalent Input Circuit
TheSPT7824isdrivenfromasingle-endedTTLinput(CLK).
TheCLKpulsewidth(tpwH)mustbekeptbetween10nsand
300 ns to ensure proper operation of the internal track-and-
hold amplifier. (See timing diagram.) When operating the
SPT7824 at sampling rates above 3 MSPS, it is recom-
mended that the clock input duty cycle be kept at 50% to
optimize performance. (See figure 4.) The analog input
signal is latched on the rising edge of the CLK.
V
CC
V
V
IN
FT
TheclockinputmustbedrivenfromfastTTLlogic(V ≤4.5V,
IH
T
<6 ns). In the event the clock is driven from a high
RISE
current source, use a 100 Ω resistor in series to current limit
to approximately 45 mA.
V
EE
Figure 4 - SNR vs Clock Duty Cycle
An example of a reference driver circuit recommended is
shown in figure 2. IC1 is REF-03, the +2.5 V reference with a
tolerance of 0.6% or +/- 0.015 V. The potentiometer R1 is
10 kΩ and supports a minimum adjustable range of up to
150 mV. IC2 is recommended to be an OP-07 or equivalent
device. R2 and R3 must be matched to within 0.1% with good
59
57
55
53
TCtrackingtomaintaina0.3LSBmatchingbetweenV and
FT
Duty
Cycle
t
t
pwH
pwL
51
49
47
45
43
=
V
FB
. If 0.1% matching is not met, then potentiometer R4 can
beusedtoadjusttheV voltagetothedesiredlevel.V and
FB
FT
tpwH
tpwL
V
FB
should be adjusted such that V and V are exactly
ST SB
+2.0 V and -2.0 V respectively.
The analog input range will scale proportionally with respect
to the reference voltage if a different input range is required.
The maximum scaling factor for device operation is ± 20% of
the recommended reference voltages of V and V . How-
30
35
40
45
50
55
60
65
70
75
Duty Cycle of Positive Clock Pulse (%)
FT
FB
SPT7824
7
3/11/97
DIGITAL OUTPUTS
OVERRANGE OUTPUT
The format of the output data (D0-D9) is straight binary. (See
table II.) The outputs are latched on the rising edge of CLK
with a propagation delay of 14 ns (typ). There is a one clock
cycle latency between CLK and the valid output data. (See
timing diagram.)
The OVERRANGE OUTPUT (D10) is an indication that the
analog input signal has exceeded the positive full scale input
voltageby1LSB.Whenthisconditionoccurs,D10willswitch
to logic 1. All other data outputs (D0 to D9) will remain at
logic 1 as long as D10 remains at logic 1. This feature makes
it possible to include the SPT7824 into higher resolution
systems.
Table II - Output Data Information
ANALOG INPUT
OVERRANGE
D1O
OUTPUT CODE
D9-DO
EVALUATION BOARD
>+2.0 V + 1/2 LSB
+2.0 V -1 LSB
0.0 V
1
11 1111 1111
11 1111 111Ø
ØØ ØØØØ ØØØØ
OO OOOO OOOØ
OO OOOO OOOO
The EB7824 Evaluation Board is available to aid designers in
demonstrating the full performance of the SPT7824. This
board includes a reference circuit, clock driver circuit, output
data latches and an on-board reconstruction of the digital
data. An application note describing the operation of this
board as well as information on the testing of the SPT7824 is
also available. Contact the factory for price and availability.
O
O
O
O
-2.0 V +1 LSB
<-2.0 V
(Ø indicates the flickering bit between logic 0 and 1).
The rise times and fall times of the digital outputs are not
symmetrical. The propagation delay of the rise time is typi-
cally 14 ns and the fall time is typically 6 ns. (See figure 5.)
The nonsymmetrical rise and fall times create approximately
8 ns of invalid data.
Figure 5 - Digital Output Characteristics
N
N+1
CLK In
2.4 V
Rise Time
6 nsec
6 ns
typ.
3.5 V
Invalid
Data
Invalid
Data
Data Out
(Actual)
2.4 V
(N)
(N-1)
(N-2)
0.8 V
0.5 V
tpd1
(14 ns typ.)
Invalid
Data
Data Out
(Equivalent)
Invalid
Data
(N-1)
(N-2)
(N-1)
SPT7824
8
3/11/97
PACKAGE OUTLINES
28-Lead Sidebrazed
INCHES
MIN
0.077
MILLIMETERS
MIN MAX
1.96
SYMBOL
MAX
0.093
28
1
H
A
B
C
D
E
F
G
H
I
2.36
0.51
0.016
0.095
0.020
0.105
.050 typ
0.060
0.235
1.412
0.605
0.012
0.620
0.41
2.41
2.67
0.00
1.27
I
0.040
0.215
1.388
0.585
0.009
0.600
1.02
1.52
5.46
5.97
J
35.26
14.86
0.23
35.86
15.37
0.30
G
J
15.24
15.75
A
E
F
C
B
D
28-Lead Plastic DIP
INCHES
MIN
MILLIMETERS
MIN MAX
SYMBOL
MAX
A
B
C
D
E
F
G
H
I
0.200
0.135
0.020
0.100
0.067
0.013
0.180
0.622
0.555
1.460
0.085
5.08
3.43
K
0.120
3.05
0.51
2.54
28
1.70
0.33
I
0.170
4.32
4.57
15.80
14.10
37.08
2.16
1
J
K
J
H
G
A
B
F
C
D
E
SPT7824
9
3/11/97
PACKAGE OUTLINES
28-Lead SOIC
INCHES
MIN
0.696
MILLIMETERS
MIN MAX
17.68
SYMBOL
MAX
0.712
A
B
C
D
E
F
G
H
I
18.08
0.30
1.27
0.48
0.30
2.54
1.27
10.64
7.59
0.004
0.012
.050 typ
0.019
0.10
0.00
0.36
0.23
2.03
0.41
10.01
7.39
28
0.014
0.009
0.080
0.016
0.394
0.291
0.012
I
H
0.100
0.050
0.419
1
0.299
A
F
B
C
D
G
E
SPT7824
10
3/11/97
PIN ASSIGNMENTS
PIN FUNCTIONS
Name
DGND
D0-D9
D10
Function
DGND
D0
1
28
DV
CC
Digital Ground
V
2
3
27
26
EE
TTL Outputs (D0=LSB)
TTL Output Overrange
Clock
D1
AGND
D2
V
4
5
25
24
CC
CLK
D3
V
FB
V
-5.2 V Supply (Analog)
Analog Ground
D4
V
EE
6
7
23
22
SB
D5
V
AGND
DIP/PDIP/SOIC
RM
D6
V
8
9
21
20
V
V
+5.0 V Supply (Analog)
Analog Input
CC
IN
IN
D7
V
ST
D8
10
11
19
18
V
DV
Digital +5.0 V Supply
CC
FT
D9
V
V
V
V
V
V
Middle of Voltage Reference Ladder
Force for Top of Reference Ladder
Sense for Top of Reference Ladder
Force for Bottom of Reference Ladder
Sense for Bottom of Reference Ladder
RM
CC
D10
DGND
12
13
14
17
16
15
AGND
FT
ST
FB
SB
V
EE
DV
CC
CLK
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
PACKAGE TYPE
SPT7824AIJ
SPT7824BIJ
SPT7824ACN
SPT7824BCN
SPT7824ACS
SPT7824BCS
SPT7824AMJ
SPT7824BMJ
-25 to +85 °C
-25 to +85 °C
0 to +70 °C
28L Sidebrazed DIP
28L Sidebrazed DIP
28L Plastic DIP
28L Plastic DIP
28L SOIC
0 to +70 °C
0 to +70 °C
0 to +70 °C
28L SOIC
-55 to +125 °C
-55 to +125 °C
28L Sidebrazed DIP
28L Sidebrazed DIP
SPT7824
11
3/11/97
相关型号：
SPT7824AIC
ADC, Successive Approximation, 10-Bit, 1 Func, Parallel, Word Access, CQCC28, LCC-28
FAIRCHILD
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