SPT7830SCS [CADEKA]
10-BIT, 2.5 MSPS, SERIAL OUTPUT A/D CONVERTER; 10位， 2.5 MSPS ，串行输出A / D转换器
| 型号： | SPT7830SCS |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 10-BIT, 2.5 MSPS, SERIAL OUTPUT A/D CONVERTER |
| 文件： | 总8页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7830
10-BIT, 2.5 MSPS, SERIAL OUTPUT A/D CONVERTER
FEATURES
APPLICATIONS
• 10-Bit, 1 kHz to 2.5 MSPS Analog-to-Digital Converter
• Monolithic CMOS
• Serial Output
• Handheld and Desktop Scanners
• DSP Interface Applications
• Portable Digital Radios
• Internal Sample-and-Hold
• Portable and Handheld Applications
• Automotive Applications
• Remote Sensing
• Analog Input Range: 0 to 2 V Nominal; 3.3 V Max
• Power Dissipation (Excluding Reference Ladder)
45 mW at +5 V
16 mW at +3.0 V
• Single Power Supply: +3 V to +5 V Range
• High ESD Protection: 3,000 V Minimum
GENERAL DESCRIPTION
The SPT7830 10-bit, 2.5 MSPS, serial analog-to-digital
converter delivers excellent high speed conversion perfor-
mance with low cost and low power. The serial port protocol
is compatible with the serial peripheral interface (SPI) or
MICROWIRE™industry standard, high-speed synchronous
MPUinterfaces. Thelargeinputbandwidthandfasttransient
response time allow for CCD applications operating up to
2.5 MSPS.
The device can operate with a power supply range from
+3 V to +5 V with very low power dissipation. The small
package size makes this part excellent for hand-held appli-
cations where board space is at a premium. The SPT7830 is
available in an 8-lead SOIC package over the commercial
and industrial temperature ranges. Contact the factory for
availability of die.
V
BLOCK DIAGRAM
Ground
DD
Track-and-Hold
SAR
Serial
Output
Logic
Analog Input
Data Out
10-Bit
A/D
Clock
Timing And Control
Start Convert
V
V
REF+
REF-
1
ABSOLUTE MAXIMUM RATING (Beyond which damage may occur)
Output
Supply Voltages
...........................................................................+6 V
Data Out ................................................................10 mA
V
DD
Temperature
Input Voltages
Operating,
ambient ...............................–40 to +85 °C
junction......................................... +175 °C
Analog Input ................................................ –0.7 to +6 V
V
V
+ .......................................................... –0.7 to +6 V
– .......................................................... –0.7 to +6 V
REF
REF
Lead, Soldering (10 seconds) ............................ +300 °C
Storage ....................................................–65 to +150 °C
Clock and
.............................................. –0.7 to +6 V
SC
Note: 1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications.
ELECTRICAL SPECIFICATIONS
T
= +25 °C, V
= +5.0 V, V = 0 to +3 V, f
= 35 MHz, f = 2.5 MSPS, V
+ = +3.0 V, V – = 0.0 V, unless otherwise specified.
REF
A
DD
IN
CLK
S
REF
TEST
CONDITIONS
TEST
PARAMETERS
LEVEL
MIN
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
DC Performance
Resolution
10
±0.5
Bits
LSB
LSB
Differential Linearity
Integral Linearity
No Missing Codes
VI
VI
VI
±1.0
±1.5
±1.0
Guaranteed
Analog Input
1
Input Voltage Range
IV
VI
IV
IV
IV
IV
V
REF
– +4%
5
V
REF
+ –6%
V
Input Resistance
Input Capacitance
Input Bandwidth (Small Signal)
Offset
MΩ
5
pF
30
MHz
–2
–2
+2
+2
% of FSR
% of FSR
Gain Error
Reference Input
Resistance
IV
250
280
0
350
Ω
1
Voltage Range
2
V
REF
V
REF
V
REF
–
+
IV
IV
IV
IV
–4%
– +∆
V
+ –∆
REF
V
V
V
ns
2
V
2/3 V
REF
DD
+ – V
– (∆)
1/10 V
REF
DD
Reference Settling Time
90
Timing Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Maximum External Clock Rate
Minimum External Clock Rate
Aperture Delay Time
VI
IV
VI
IV
IV
IV
IV
2.5
1
1.0
14
MSPS
kSPS
MHz
kHz
ns
35
14
5
5
8
Aperture Jitter Time
ps
Data Output LSB Hold Time
T
MIN
to T
6
ns
MAX
1
Percentages refer to percent of [(V
+) – (V –)]
REF
REF
2
∆ = Minimum (V + – V
REF
–)
REF
SPT7830
2
12/29/99
ELECTRICAL SPECIFICATIONS
T
= +25 °C, V
= +5.0 V, V = 0 to +3 V, f
= 35 MHz, f = 2.5 MSPS, V
+ = +3.0 V, V – = 0.0 V, unless otherwise specified.
REF
A
DD
IN
CLK
S
REF
TEST
TEST
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
Dynamic Performance
Effective Number of Bits
f
f
= 500 kHz
= 1 MHz
IV
IV
8.9
8.5
Bits
Bits
IN
IN
Signal-to-Noise Ratio
f
f
= 500 kHz
= 1 MHz
IV
IV
56
55
dB
dB
IN
IN
Harmonic Distortion
f
f
= 500 kHz
= 1 MHz
IV
IV
63
58
dB
dB
IN
IN
Power Supply Requirements
+V Supply Voltage
+V Supply Current
DD
IV
IV
3
5.5
7
V
mA
DD
V
DD
V
DD
V
DD
V
DD
= +3.0 V
= +5.0 V
= +3.0 V
= +5.0 V
5.4
9
VI
IV
VI
10
22
50
mA
3
Power Dissipation
16
45
mW
mW
3
Excluding reference ladder.
TEST LEVEL
TEST PROCEDURE
100% production tested at the specified temperature.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
II
100% production tested at T =+25 °C, and sample
A
tested at the specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = +25 °C. Parameter is
A
guaranteed over specified temperature range.
SPT7830
3
12/29/99
should be taken to ensure that the LSB is latched into an
external latch with the proper amount of set and hold time.
GENERAL DESCRIPTION AND OPERATION
The SPT7830 is a 10-bit analog-to-digital converter that
uses a successive approximation architecture to perform
data conversion. Each conversion cycle is 14 clocks in
DATA OUTPUT CODING
The coding of the output is straight binary. (See table I.)
Table I - Data Output Coding
length. When the Not Start Convert ( ) line is held low,
SC
conversion begins on the next rising edge of the input clock.
When the conversion cycle begins, the data output pin is
forced low until valid data output begins.
ANALOG INPUT
+FS -1/2 LSB
+1/2 FS
OUTPUT CODE D9 - DO
1 1
ØX
OO
OO
1 1 1 1
XXXX
OOOO
OOOO
1 1 1 Ø
XXXX
OOOØ
OOOO
The first two clock cycles are used to perform internal offset
calibrations and tracking of the analog input. The analog input
is then sampled using an internal track-and-hold amplifier on
the falling edge of the third clock cycle. On clock cycles 4
through 14, a 10-bit successive approximation conversion is
performed, and the data is output starting with the MSB.
+1/2 LSB
V
REF-
Ø indicates the flickering bit between logic O and 1.
X indicates the flickering bit between logic 1 and O.
ANALOG INPUT AND REFERENCE SETTLING TRACK
AND HOLD TIMING
Serial data output begins with output of the MSB. See the
Data Output Timing section for details. Each bit of the data
conversion is sequentially determined and placed on the
data output pin at the clock rate. This process continues until
the LSB has been determined and output. At this point, if the
Figure 9 shows the timing relationship between the input
clock and
versus the analog input tracking and reference
SC
settling.Theanaloginputistrackedfromthefourteenthclock
cycleofthepreviousconversiontothethirdclockcycleofthe
current conversion. On the falling edge of the third clock
cycle, the analog input is held by the internal sample-and-
hold. After this sample, the analog input may vary without
affecting data conversion.
line is high, the data output pin will be forced into a high
SC
impedance state, and the converter will go into an idle state
waiting for the line to go low. This is referred to as Single
SC
Shot Mode. See Modes of Operation for details.
If the is either held low through the entire 14 clock
SC
conversion cycle (free run mode) or is brought low prior to
the trailing edge of the fourteenth clock cycle (synchronous
mode), the data output pin goes low and stays low until valid
data output begins. Because the chip has either remained
selected in the free run mode or has been immediately
selected again in the synchronous mode, the next conversion
cycle begins immediately after the fourteenth clock cycle of
the previous conversion. See Modes of Operation for details.
The reference ladder inputs (V
+ and V
-) may be
REF
REF
changed starting on the falling edge of the thirteenth clock
cycle of the previous conversion and must be settled by the
falling edge of the third clock cycle of the current conversion.
VOLTAGE REFERENCE AND ANALOG INPUT
The SPT7830 requires the use of a single external voltage
reference for driving the high side of the reference ladder.
The V
+ can be a maximum of 2/3 V . For example, if
REF
DD
TYPICAL INTERFACE CIRCUIT
V
= +5 V, then V
+ max = (2/3) 5 V = +3.3 V. The lower
REF *
DD
CLOCK INPUT
side of the ladder is typically tied to AGND (0.0 V), but can be
run up to a voltage that is 1/10th of V below V +:
DD
REF
The SPT7830 requires a 50% ±10% duty cycle clock running
at 14 times the desired sample rate. The clock may be
stopped in between conversion cycles without degradation
of operation (single shot type of operation); however, the
clock should remain running during a conversion cycle.
V
- max. = V
+ - (1/10) V
.
DD
REF
REF
*
For example,
if V = +5 V and V
+ = 3 V, then
REF
DD
V
- max = 3 V - (1/10) 5 V = 2.5 V.
REF
*
POWER SUPPLY
The+FullScale(+FS)oftheanaloginputisexpectedtobe6%
of [(V +) - (V -)] below V + and the -Full Scale (-FS)
The SPT7830 requires only a single supply and operates
from3.0Vto5.0V. CADEKArecommendsthata0.01µFchip
capacitor be placed as close as possible to the supply pin.
REF
REF
REF
of the analog input is expected to be 4% of [(V
above V
+) - (V -)]
REF REF
-. (See figure 1.)
REF
Therefore,
Analog +FS = V
DATA OUTPUT SET UP AND HOLD TIMING
+ - 0.06 * [(V
+) - (V
-)], and
-)].
As figure 8 shows, all of the data output bits (except the LSB)
remainvalidforadurationequivalenttooneclockperiodand
delayed by 8 ns after the falling edge of clock. Because the
data converter enters into a next conversion ready state at
the leading edge of clock 14, the LSB bit is valid for a
duration equivalent to only the clock pulse width low
and delayed by 8 ns after the falling edge of clock. Care
REF
REF
REF
Analog -FS = V
- +0.04 * [(V
+) - (V
REF
REF
REF
For example,
if V
+ = 3 V and V
- = 0 V, then
REF
REF
Analog +FS = 3 V - 0.06 * [3 V- 0 V ] = 2.82 V, and
Analog -FS = 0 V + 0.04 * [3 V - 0 V] = 0.12 V.
SPT7830
4
12/29/99
Figure 1 - Analog Input Full-Scale Range
MODES OF OPERATION
The SPT7830 has three modes of operation.The mode of
V
+
+FS
REF
operation is based strictly on how the
is used.
SC
SINGLE SHOT MODE
6% of [(V
REF
+) - (V
REF
-)]
When
goes low, conversion starts on the next rising edge
SC
of the clock (defined as the first conversion clock). The MSB
of data is valid 8 ns after the falling edge of the fourth
conversion clock. (See figure 8, Data Output Timing.)
4% of [(V
+) - (V -)]
REF
REF
-FS
-
The conversion is complete after 14 clock cycles. At the
V
REF
falling edge of the fourteenth clock cycle, if
is high (not
SC
selected), the data output goes to a high impedance state,
The drive requirements for the analog input are minimal
when compared to most other converters due to the
SPT7830’s extremely low input capacitance of only 5 pF and
very high input resistance of greater than 5 MΩ.
and no more conversions will take place until the next low
SC
event. (See the single shot mode timing diagram in figure 4.)
SYNCHRONIZED MODE
If the input buffer amplifier supply voltages are greater than
When
goes low, conversion will start on the next rising
SC
V
+ 0.7 V or less than Ground - 0.7 V, the analog input
DD
edge of the clock (defined as the first conversion clock). The
MSB is valid 8 ns after the falling edge of the fourth conver-
sion clock.
should be protected through a series resistor and a diode
clamping circuit as shown in figure 2.
Figure 2 - Recommended Input Protection Circuit
AV
The first conversion is complete after 14 clock cycles. At any
+V
DD
time after the falling edge of the fourteenth clock cycle,
SC
may go low again to initiate the next conversion. When the
goes low, the conversion starts on the rising edge of the
next clock. (See the synchronized mode timing diagram in
figure 5.)
SC
D1
D2
Buffer
ADC
47 Ω
The data output will go to a high impedance state until the
next conversion is initiated.
-V
FREE RUN MODE
D1 = D2 = Hewlett Packard HP5712 or equivalent
When
goes low, conversion starts on the next rising edge
SC
INPUT PROTECTION
of the clock (defined as the first conversion clock). The MSB
data is valid 8 ns after the falling edge of the fourth conver-
sion clock.
All I/O pads are protected with an on-chip protection circuit
shown in figure 3. This circuit provides ESD robustness to
>3.0 kV and prevents latch-up under severe discharge
conditions without degrading analog transition times.
As long as
is held low, the device operates in the free run
SC
mode. New conversions start after every fourteenth cycle
with valid data available 8 ns after the falling edge of the
fourth clock within each new conversion cycle.
Figure 3 - On-Chip Protection Circuit
V
DD
The data output remains low between conversion cycles.
(See the free run mode timing diagram in figure 6.)
Analog
120 Ω
120 Ω
Pad
SPT7830
5
12/29/99
Figure 4 - Single Shot Mode Timing Diagram
t
SC
Start Convert
Latch
MSB
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
Clock
High Z State
Serial Data Out
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
LSB
MSB
Start
Conversion
Sample
Analog Input
Figure 5 - Synchronous Mode Timing Diagram
t
t
SC
SC
Latch
MSB
Latch
MSB
Start Convert
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
13
A
14
A
15
A
16
A
1
B
2
B
3
B
4
B
5
B
Clock
High Z State
Serial Data Out
A9
A8
A7
A6
A1
A0
LSB
B9
MSB
MSB
Start
Sample
Analog Input
A
Sample
Analog Input
B
Figure 6 - Free Run Mode Timing Diagram
Latch
MSB
Start Convert
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
1
3
A
1
4
A
1
B
2
B
3
B
4
B
5
B
6
B
7
B
Clock
Serial Data Out
A9
A8
A7
A6
A1
A0
LSB
B9
B8
B7
MSB
MSB
Start
Sample
Analog Input
A
Sample
Analog Input
B
Figure 8 - Data Output Timing
Figure 7 - Typical Interface Circuit
t =8 ns
t =8 ns
t =8 ns
d
t =8 ns
d
d
d
V
+
V
DD
REF
REF IN
+V
DD
.01 µF
.01 µF
V
+V
REF+
0 V
DD
0 V
Analog In
Data Out
Clock
SC
V
1
3
A
1
4
A
IN
4
A
5
A
Clock
+V
V
-
DD
0 V
REF
Data Out
A9
MSB
A1
A0
+V
DD
Ground
LSB
0 V
SPT7830
6
12/29/99
Figure 9 - Analog Input Track-and-Hold Timing and Reference Settling-and-Hold Timing
Single Shot Mode
SC high, no B cycle)
Synchronous Mode
*
(
SC
Free Run Mode (SC always Ø)
Clock
1
A
2
A
3
A
4
A
13
A
14
A
1
B
2
B
3
B
4
B
V
REF+
Ref Hold
Ref Settling Window**
A
IN
Sample
Input
Sample
Input
*
The rising edge of the SC line can occur any time between the
rising edge of clock 1A and the falling edge of clock 14A.
**The reference settling window can be extended in the
synchronous mode by adding extra clocks between conversion
cycles. The example shown is the minimum number of clocks
required (14) per conversion cycle.
PACKAGE OUTLINE
8-Lead SOIC
INCHES
MILLIMETERS
MIN MAX
4.98
A
SYMBOL
MIN
MAX
0.194
0.242
A
B
C
D
E
F
G
H
I
0.187
0.228
0.050 typ
0.014
0.005
0.060
0.055
0.149
0°
4.80
5.84
1.27 typ
0.35
0.13
1.55
1.40
3.81
0°
6.20
0.019
0.010
0.067
0.060
0.156
8°
0.49
0.25
1.73
1.55
3.99
8°
B
J
0.007
0.016
0.010
0.035
0.19
0.41
0.25
0.89
K
H
G
I
J
F
K
C
D
E
SPT7830
7
12/29/99
PIN FUNCTIONS
PIN ASSIGNMENTS
Name
Function
External V
+
1
2
3
4
8
7
6
5
V
REF
Analog In
External V
Analog In
Analog Signal Input
DD
Start Convert
Start Convert. A high-to-low transition on
this input begins the conversion cycle and
enables serial data output.
Data Out
Clock
-
REF
Ground
Clock
Clock that drives A/D conversion cycle and
the synchronous serial data output
Start Convert
Data Out
Serial Data. Tri-state serial data output for
the A/D result driven by the CLOCK input
External V
External V
+
-
External voltage reference for top of refer-
ence ladder
REF
REF
External voltage reference for bottom of
reference ladder
V
Analog and Digital +3 V to +5 V
Power Supply Input
DD
GND
Analog and Digital Ground
ORDERING INFORMATION
PART NUMBER
TEMPERATURE RANGE
0 to +70 °C
PACKAGE
8L SOIC
8L SOIC
Die*
SPT7830SCS
SPT7830SIS
–40 to +85 °C
SPT7830SCU
+25 °C
*Please see the die specification for guaranteed electrical performance.
SPT7830
8
12/29/99
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