SPT7835 [CADEKA]
10-BIT, 5 MSPS, 75 mW A/D CONVERTER; 10位, 5 MSPS , 75 mW的A / D转换器型号: | SPT7835 |
厂家: | CADEKA MICROCIRCUITS LLC. |
描述: | 10-BIT, 5 MSPS, 75 mW A/D CONVERTER |
文件: | 总12页 (文件大小:186K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SPT7835
10-BIT, 5 MSPS, 75 mW A/D CONVERTER
TECHNICAL DATA
JUNE 27, 2001
FEATURES
APPLICATIONS
• Monolithic 5 MSPS converter
• 75 mW power dissipation
• On-chip track-and-hold
• Single +5 V power supply
• TTL/CMOS outputs
• All high-speed applications where low power
dissipation is required
• Video imaging
• Medical imaging
• IR imaging
• 5 pF input capacitance
• Low cost
•Scanners
• Digital communications
• Tri-state output buffers
• High ESD protection: 3,500 V minimum
• Selectable +3 V or +5 V logic I/O
GENERAL DESCRIPTION
SPT7835 is pin-compatible with an entire family of 10-bit,
CMOS converters (SPT7835/40/50/55/60/61), which sim-
plifies upgrades. The SPT7835 has incorporated propri-
etary circuit design* and CMOS processing technologies
to achieve its advanced performance. Inputs and outputs
are TTL/CMOS-compatible to interface with TTL/CMOS
logic systems. Output data format is straight binary.
The SPT7835 is a 10-bit monolithic, low-cost, ultralow-
power analog-to-digital converter capable of minimum
word rates of 5 MSPS. The on-chip track-and-hold func-
tion assures very good dynamic performance without the
need for external components. The input drive require-
ments are minimized due to the SPT7835’s low input
capacitance of only 5 pF.
The SPT7835 is available in a 28-lead SOIC package over
the industrial temperature range, and a 32-lead small
(7 mm square) TQFP package over the commercial
temperature range.
Power dissipation is extremely low at only 75 mW typical
at 5 MSPS with a power supply of +5.0 V. The digital out-
puts are +3 V or +5 V, and are user selectable. The
*Patent pending
BLOCK DIAGRAM
ADC Section 1
D10 Overrange
Auto-
1:8
Mux
11-Bit
SAR
11
Zero
AIN
T/H
CMP
D9 (MSB)
D8
11
DAC
P1
D7
P2
.
11
11
ADC Section 2
.
CLK In
Enable
.
.
.
.
.
.
.
D6
.
.
Timing
and
Control
11-Bit
8:1
.
P7
ADC Section 7
Mux/
D5
Error
Correction
P8
ADC Section 8
11
D4
Auto-
Zero
CMP
11-Bit
SAR
T/H
Data
Valid
D3
11
D2
DAC
D1
Ref
In
D0 (LSB)
Reference Ladder
VREF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Output
AVDD...................................................................... +6 V
DVDD ..................................................................... +6 V
Digital Outputs ................................................... 10 mA
Temperature
Input Voltages
Operating Temperature ............................ –40 to 85 °C
Junction Temperature ........................................ 175 °C
Lead Temperature, (soldering 10 seconds) ....... 300 °C
Storage Temperature............................ –65 to +150 °C
Analog Input .............................. –0.5 V to AVDD +0.5 V
VREF .............................................................. 0 to AVDD
CLK Input ............................................................... VDD
AVDD – DVDD .................................................. ±100 mV
AGND – DGND .............................................. ±100 mV
Note: 1. Operation at any Absolute Maximum Rating is not implied.See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒCLK=10 MHz, ƒS=5 MSPS, VRHS=4.0 V, VRLS=0.0V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7835
TYP
PARAMETERS
Resolution
MIN
MAX
UNITS
10
Bits
DC Accuracy
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
No Missing Codes
VI
VI
VI
±1.0
±0.5
Guaranteed
LSB
LSB
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
VI
IV
V
V
V
VRLS
50
VRHS
V
kΩ
pF
MHz
LSB
LSB
5.0
100
±2.0
±2.0
(Small Signal)
Gain Error
V
Reference Input
Resistance
Bandwidth
Voltage Range
VRLS
VI
V
400
100
500
150
600
Ω
MHz
IV
IV
V
V
V
0
3.0
1.0
2.0
AVDD
5.0
V
V
V
mV
VRHS
VRHS – VRLS
4.0
90
75
∆(VRHF – VRHS
)
∆(VRLS – VRLF
)
mV
Reference Settling Time
VRHS
VRLS
V
V
15
20
Clock Cycles
Clock Cycles
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
VI
IV
IV
V
5
2
MHz
MHz
Clock Cycles
ns
12
5
10
Aperture Jitter Time
V
ps (p-p)
Dynamic Performance
Effective Number of Bits (ENOB)
ƒIN = 1 MHz
VI
VI
9.2
59
Bits
dB
Signal-to-Noise Ratio (SNR)
(without Harmonics)
ƒIN = 1 MHz
54
SPT7835
2
6/27/01
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0 V, VIN=0 to 4 V, ƒCLK=10 MHz, ƒS=5 MSPS, VRHS=4.0 V, VRLS=0.0V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7835
TYP
PARAMETERS
MIN
MAX
UNITS
Dynamic Performance
Total Harmonic Distortion (THD)
ƒIN = 1 MHz
VI
59
52
63
dB
Signal-to-Noise and Distortion
(SINAD)
ƒIN = 1 MHz
Spurious Free Dynamic Range
VI
V
57
63
dB
dB
Digital Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
VI
VI
VI
VI
V
2.0
V
V
µA
µA
pF
0.8
+10
+10
–10
–10
5
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
tRISE
IOH = 0.5 mA
IOL = 1.6 mA
15 pF load
VI
VI
V
V
V
3.5
V
V
ns
ns
ns
ns
0.4
10
10
10
22
tFALL
15 pF load
Output Enable to Data Output Delay 20 pF load, TA = +25 °C
50 pF load over temp.
V
Power Supply Requirements
Voltages
OVDD
DVDD
AVDD
AIDD
IV
IV
IV
VI
VI
VI
3.0
4.75
4.75
5.0
5.25
5.25
12
10
110
V
V
V
mA
mA
mW
5.0
5.0
9
6
75
Currents
DIDD
Power Dissipation
ƒIN = 1 MHz
TEST LEVEL CODES
LEVEL TEST PROCEDURE
All electrical characteristics are subject to the
following conditions:
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
IV
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT7835
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SPECIFICATION DEFINITIONS
APERTURE DELAY
INTEGRAL LINEARITY ERROR (ILE)
Aperture delay represents the point in time, relative to the Linearity error refers to the deviation of each individual
rising edge of the CLOCK input, that the analog input is code (normalized) from a straight line drawn from –FS
sampled.
through +FS. The deviation is measured from the edge of
each particular code to the true straight line.
APERTURE JITTER
OUTPUT DELAY
The variations in aperture delay for successive samples.
Time between the clock’s triggering edge and output data
valid.
DIFFERENTIAL GAIN (DG)
A signal consisting of a sine wave superimposed on vari-
ous DC levels is applied to the input. Differential gain is the
OVERVOLTAGE RECOVERY TIME
maximum variation in the sampled sine wave amplitudes The time required for the ADC to recover to full accuracy
at these DC levels.
after an analog input signal 125% of full scale is reduced
to 50% of the full-scale value.
DIFFERENTIAL PHASE (DP)
SIGNAL-TO-NOISE RATIO (SNR)
A signal consisting of a sine wave superimposed on vari-
ous DC levels is applied to the input. Differential phase is The ratio of the fundamental sinusoid power to the total
the maximum variation in the sampled sine wave phases noise power. Harmonics are excluded.
at these DC levels.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
EFFECTIVE NUMBER OF BITS (ENOB)
The ratio of the fundamental sinusoid power to the total
SINAD = 6.02N + 1.76, where N is equal to the effective noise and distortion power.
number of bits.
SINAD – 1.76
TOTAL HARMONIC DISTORTION (THD)
N =
6.02
The ratio of the total power of the first 9 harmonics to the
power of the measured sinusoidal signal.
INPUT BANDWIDTH
Small signal (50 mV) bandwidth (3 dB) of analog input
stage.
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
DIFFERENTIAL LINEARITY ERROR (DLE)
Error in the width of each code from its theoretical value.
(Theoretical = VFS/2N)
SPT7835
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Figure 1A – Timing Diagram 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
ANALOG IN
CLOCK IN
SAMPLING CLOCK
(Internal)
INVALID
VALID
1
2
3
4
5
6
7
8
9
10
11
DIGITAL OUT
DATA VALID
Figure 1B – Timing Diagram 2
t
C
t
t
CL
CH
t
CLK
CLOCK
IN
t
OD
DATA
OUTPUT
Data 1
Data 2
Data 0
t
t
DAV
DAV
DATA
VALID
t
S
Table I – Timing Parameters
DESCRIPTION
PARAMETERS
MIN
TYP
MAX UNITS
Conversion Time
tC
2*tCLK
ns
Clock Period
tCLK
tCH
tCL
tOD
tDAV
tS
100
40
ns
Clock High Duty Cycle
Clock Low Duty Cycle
50
50
60
60
25
%
%
40
Clock to Output Delay (15 pF Load)
DAV Pulse Width
15
20
ns
ns
ns
tCLK
21
Clock to DAV
16
26
SPT7835
5
6/27/01
TYPICAL PERFORMANCE CHARACTERISTICS
SNR vs Input Frequency
THD vs Input Frequency
80
70
60
80
70
60
S
= 5 MSPS
S
= 5 MSPS
50
40
50
40
30
20
30
20
1
1
100
100
10
10
Input Frequency (MHz)
Input Frequency (MHz)
Total Power Dissipation vs Sample Rate
Reference is excluded = 30 mW Typ
SINAD vs Input Frequency
110
90
70
50
30
10
80
70
60
= 5 MSPS
S
50
40
30
20
1
100
10
Input Frequency (MHz)
0
5
Sample Rate (CLK/2) MHz
SPT7835
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Figure 2 – Typical Interface Circuit
Ref In
(+4 V)
V
V
V
V
RHF
RHS
RLS
RLF
D10
D9
D8
D7
D6
D5
OV
3.3/5
DD
Interfacing
Logics
SPT7835
V
V
IN
IN
OGND
D4
V
CAL
D3
D2
D1
D0
CLK IN
CLK
DAV
EN
DD
AV
AGND DGND* DV
DD
3.3/5
Enable/Tri-State
(Enable = Active Low)
+A5
L1
AGND
+A5
DGND
3.3/5
+
10 µF
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
+
10 µF
+5 V
+5 V
Analog
RTN
+5 V
Digital
RTN
+5 V
Digital
Analog
NOTES: 1) L1 is to be located as closely to the device as possible.
2) All capacitors are 0.1 µF surface-mount unless otherwise specified.
3) L1 is a 10 µH inductor or a ferrite bead.
TYPICAL INTERFACE CIRCUIT
OPERATING DESCRIPTION
Very few external components are required to achieve the The general architecture for the CMOS ADC is shown in
stated device performance. Figure 2 shows the typical in- the block diagram. The design contains eight identical
terface requirements when using the SPT7835 in normal successive approximation ADC sections, all operating in
circuit operation. The following sections provide descrip- parallel, a 16-phase clock generator, an 11-bit 8:1 digital
tions of the major functions and outline critical perfor- output multiplexer, correction logic, and a voltage refer-
mance criteria to consider for achieving the optimal device ence generator that provides common reference levels for
performance.
each ADC section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
shown in table II.
POWER SUPPLIES AND GROUNDING
CADEKA suggests that both the digital and the analog sup-
ply voltages on the SPT7835 be derived from a single ana-
log supply as shown in figure 2. A separate digital supply
should be used for all interface circuitry.CADEKA suggests
using this power supply configuration to prevent a possible
latch-up condition on powerup.
SPT7835
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6/27/01
Table II – Clock Cycles
Figure 3 – Ladder Force/Sense Circuit
Clock
1
2
3
4
Operation
AGND
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
+
VRHF
5-15
16
11-bit SAR conversion
Data transfer
VRHS
The 16-phase clock, which is derived from the input clock,
synchronizes these events.The timing signals for adjacent
ADC sections are shifted by two clock cycles so that the
analog input is sampled on every other cycle of the input
clock by exactly one ADC section. After 16 clock periods,
the timing cycle repeats. The sample rate for the configu-
ration is one-half of the clock rate; e.g., for a 10 MHz clock
rate, the input sample rate is 5 MHz. The latency from
analog input sample to the corresponding digital output is
12 clock cycles.
VRLS
+
VRLF
VIN
All capacitors are 0.01 µF
• Since only eight comparators are used, a huge power
savings is realized.
• The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparators’
response to a reference zero.
• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of the
gain error are integrated to produce a calibration volt-
age for each ADC section.
Figure 4 – Reference Ladder
+4.0 V
External
Reference
90 mV
R/2
R
VRHS
(+3.91 V)
R
• Capacitive displacement currents, which can induce
sampling error, are minimized since only one compara-
tor samples the input during a clock cycle.
• The total input capacitance is very low since sections of
the converter that are not sampling the signal are iso-
lated from the input by transmission gates.
R
R
R=30 W (typ)
All capacitors are 0.01 µF
R
R
VOLTAGE REFERENCE
The SPT7835 requires the use of a single external voltage
reference for driving the high side of the reference ladder.
It must be within the range of 3 V to 5 V. The lower side of
the ladder is typically tied to AGND (0.0 V), but can be run
up to 2.0 V with a second reference.The analog input volt-
age range will track the total voltage difference measured
VRLS
(0.075 V)
75 mV
R/2
VRLF
(AGND)
0.0 V
between the ladder sense lines, VRHS and VRLS
.
force and sense lines to AGND with a .01 µF capacitor
(chip cap preferred) to minimize high-frequency noise in-
jection. If this simplified configuration is used, the following
considerations should be taken into account.
Force and sense taps are provided to ensure accurate
and stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations.
By using the configuration shown in figure 3, offset and
gain errors of less than ±2 LSB can be obtained.
The reference ladder circuit shown in figure 4 is a simpli-
fied representation of the actual reference ladder with
force and sense taps shown. Due to the actual internal
structure of the ladder, the voltage drop from VRHF to VRHS
In cases where wider variations in offset and gain can be
tolerated, VREF can be tied directly toVRHF, and AGND can
be tied directly to VRLF as shown in figure 4. Decouple
is not equivalent to the voltage drop from VRLF to VRLS
.
SPT7835
8
6/27/01
Typically, the top side voltage drop for VRHF to VRHS will Upon powerup, the SPT7835 begins its calibration algo-
equal:
rithm. In order to achieve the calibration accuracy re-
quired, the offset and gain adjustment step size is a frac-
tion of a 10-bit LSB. Since the calibration algorithm is an
VRHF – VRHS = 2.25 % of (VRHF – VRLF) (typical),
and the bottom side voltage drop for VRLS to VRLF will oversampling process, a minimum of 10,000 clock cycles
equal:
are required. This results in a minimum calibration time
upon powerup of 1 msec for a 5 MHz sample rate. Once
calibrated, the SPT7835 remains calibrated over time and
VRLS – VRLF = 1.9 % of (VRHF – VRLF) (typical).
Figure 4 shows an example of expected voltage drops for temperature.
a specific case. VREF of 4.0 V is applied to VRHF, and VRLF
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7835 to remain in calibration.
is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V),
and a 75 mV increase is seen at VRLS (= 0.075 V).
ANALOG INPUT
INPUT PROTECTION
VIN is the analog input. The input voltage range is from
VRLS to VRHS (typically 4.0 V) and will scale proportionally
with respect to the voltage reference. (See voltage refer-
ence section.)
All I/O pads are protected with an on-chip protection
circuit shown in figure 6.This circuit provides ESD robust-
ness to 3.5 kV and prevents latch-up under severe dis-
charge conditions without degrading analog transition
The drive requirements for the analog inputs are very times.
minimal when compared to most other converters due to
Figure 6 – On-Chip Protection Circuit
the SPT7835’s extremely low input capacitance of only
5 pF and very high input resistance of 50 kΩ.
VDD
Analog
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 5.
120 W
120 W
Figure 5 – Recommended Input Protection Circuit
+V
Buffer
V
AV
DD
Pad
D1
D2
ADC
47 W
POWER SUPPLY SEQUENCING CONSIDERATIONS
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decou-
pling networks with large time constants that could delay
VDD power to the device.
D1 = D2 = Hewlett-Packard HP5712 or equivalent
CALIBRATION
CLOCK INPUT
The SPT7835 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and off-
set errors are continually adjusted to 10-bit accuracy
during device operation.This process is completely trans-
parent to the user.
The SPT7835 is driven from a single-ended TTL-input
clock. Because the pipelined architecture operates on the
rising edge of the clock input, the device can operate over
a wide range of input clock duty cycles without degrading
the dynamic performance. The device’s sample rate is
1/2 of the input clock frequency. (See figure 1A timing
diagram.)
SPT7835
9
6/27/01
DIGITAL OUTPUTS
OVERRANGE OUTPUT
The digital outputs (D0–D10) are driven by a separate The OVERRANGE OUTPUT (D10) is an indication that
supply (OVDD) ranging from +3 V to +5 V. This feature the analog input signal has exceeded the positive full-
makes it possible to drive the SPT7835’s TTL/CMOS- scale input voltage by 1 LSB. When this condition occurs,
compatible outputs with the user’s logic system supply. D10 will switch to logic 1. All other data outputs (D0 to D9)
The format of the output data (D0–D9) is straight binary. will remain at logic 1 as long as D10 remains at logic 1.
(See table III.) The outputs are latched on the rising edge This feature makes it possible to include the SPT7835 in
of CLK. These outputs can be switched into a tri-state higher resolution systems.
mode by bringing EN high.
EVALUATION BOARD
Table III – Output Data Information
The EB7835 evaluation board is available to aid designers
ANALOG INPUT
OVERRANGE
D10
OUTPUT CODE
in demonstrating the full performance of the SPT7835.
This board includes a reference circuit, clock driver circuit,
output data latches, and an on-board reconstruction of the
digital data. An application note describing the operation
of this board, as well as information on the testing of the
SPT7835, is also available. Contact the factory for price
and availability.
D9–D0
+F.S. + 1/2 LSB
+F.S. –1/2 LSB
+1/2 F.S.
+1/2 LSB
0.0 V
1
0
0
0
0
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1Ø
ØØ ØØØØ ØØØØ
0 0 0 0 0 0 0 0 0 Ø
0 0 0 0 0 0 0 0 0 0
(Ø indicates the flickering bit between logic 0 and 1.)
SPT7835
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6/27/01
PACKAGE OUTLINES
28-Lead SOIC
INCHES
MILLIMETERS
28
SYMBOL
MIN
0.699
0.005
MAX
0.709
0.011
MIN
17.75
0.13
MAX
18.01
0.28
A
B
I
H
C
D
E
F
G
H
I
0.050 typ
0.018 typ
1.27 typ
0.46 typ
0.20
0.0077
0.0083
0.096
0.039
0.416
0.292
0.21
2.44
0.99
10.57
7.42
1
0.090
0.031
0.396
0.286
2.29
0.79
10.06
7.26
A
F
B
C
D
H
G
E
32-Lead TQFP
G
H
INCHES
MILLIMETERS
A
SYMBOL
MIN
MAX
0.362
0.280
0.362
0.280
MIN
MAX
9.20
7.10
9.20
7.10
B
A
B
C
D
E
F
G
H
I
0.346
0.272
0.346
0.272
8.80
6.90
8.80
6.90
0.031 typ
0.80 BSC
0.012
0.053
0.002
0.037
0.016
0.057
0.006
0.041
0.007
7°
0.30
1.35
0.05
0.95
0.40
1.45
0.15
1.05
0.17
7°
C
D
J
K
L
0°
0.020
0°
0.50
I
0.030
0.75
J
E
F
K
L
SPT7835
11
6/27/01
PIN ASSIGNMENTS
PIN FUNCTIONS
Name
AGND
VRHF
VRHS
VRLS
VRLF
VCAL
VIN
Function
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
D10
D9
AGND
VRHF
Analog Ground
Reference High Force
Reference High Sense
Reference Low Sense
Reference Low Force
Calibration Reference
Analog Input
VRHS
D8
N/C
VRLS
VRLF
D7
D6
D5
VIN
AGND
VCAL
OVDD
OGND
SOIC
AVDD
DVDD
DGND
CLK
Analog VDD
Digital VDD
20 D4
19 D3
18 D2
17 D1
Digital Ground
AVDD 10
DVDD 11
Input Clock ƒCLK = FS (TTL)
Output Enable
EN
DGND
CLK
12
13
14
D0–9
D10
Tri-State Data Output, (D0=LSB)
Tri-State Output Overrange
Data Valid Output
Digital Output Supply
Digital Output Ground
No Connect
D0
EN
16
15
DAV
DAV
OVDD
OGND
N/C
VRLF
VIN
1
2
3
4
5
6
7
8
24 D7
23 D6
22 D5
AGND
AGND
VCAL
OVDD
21
TQFP
20 OGND
19 D4
18 D3
17 D2
AVDD
AVDD
DVDD
ORDERING INFORMATION
PART NUMBER
SPT7835SIS
TEMPERATURE RANGE
–40 to +85 °C
PACKAGE TYPE
28L SOIC
32L TQFP
SPT7835SCT
0 to +70 °C
SPT7835
12
6/27/01
相关型号:
SPT7835SCD
ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, CDIP28, 0.300 INCH, CERDIP-28
FAIRCHILD
SPT7835SCN
ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDIP28, 0.300 INCH, SKINNY, PLASTIC, DIP-28
FAIRCHILD
SPT7835SCS
ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO28, SOIC-28
FAIRCHILD
SPT7840SCD
ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, CDIP28, 0.300 INCH, CERDIP-28
FAIRCHILD
SPT7840SCS
ADC, Successive Approximation, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO28, SOIC-28
FAIRCHILD
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