SPT7863SCT [CADEKA]
10-BIT, 40 MSPS, 160 mW A/D CONVERTER; 10位， 40 MSPS ， 160 mW的A / D转换器
| 型号： | SPT7863SCT |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | 10-BIT, 40 MSPS, 160 mW A/D CONVERTER |
| 文件： | 总11页 (文件大小：183K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT7863
10-BIT, 40 MSPS, 160 mW A/D CONVERTER
TECHNICAL DATA
AUGUST 21, 2001
FEATURES
APPLICATIONS
• Monolithic 40 MSPS converter
• 160 mW power dissipation
• On-chip track-and-hold
• Single +5 V power supply
• TTL/CMOS outputs
• All high-speed applications where low power
dissipation is required
• Video imaging
• Medical imaging
•Radar receivers
• 5 pF input capacitance
• Low cost
• IR imaging
• Digital communications
• Tri-state output buffers
• High ESD protection: 3,500 V minimum
• Selectable +3 V or +5 V logic I/O
GENERAL DESCRIPTION
SPT7863 is pin-compatible with an entire family of 10-bit,
CMOS converters (SPT7835/40/50/55/60/61), which sim-
plifies upgrades. The SPT7863 has incorporated propri-
etary circuit design and CMOS processing technologies to
achieve its advanced performance. Inputs and outputs are
TTL/CMOS-compatible to interface with TTL/CMOS logic
systems. Output data format is straight binary.
The SPT7863 is a 10-bit monolithic, low-cost, ultralow-
power analog-to-digital converter capable of minimum
word rates of 40 MSPS. The on-chip track-and-hold func-
tion assures very good dynamic performance without the
need for external components. The input drive require-
ments are minimized due to the SPT7863’s low input
capacitance of only 5 pF.
The SPT7863 is available in 28-lead SOIC and 32-lead
small (7 mm square) TQFP packages over the commer-
cial temperature range.
Power dissipation is extremely low at only 160 mW typical
at 40 MSPS with a power supply of +5.0 V.The digital out-
puts are +3 V or +5 V, and are user selectable. The
BLOCK DIAGRAM
ADC Section 1
D10 Overrange
Auto-
1:16
Mux
11-Bit
SAR
11
Zero
AIN
T/H
CMP
D9 (MSB)
D8
11
DAC
P1
D7
P2
.
11
11
ADC Section 2
.
CLK In
Enable
.
.
.
.
.
.
.
D6
.
.
Timing
and
Control
11-Bit
16:1
.
P15
ADC Section 15
Mux/
D5
Error
Correction
P16
ADC Section 16
11
D4
Auto-
Zero
CMP
11-Bit
SAR
T/H
Data
Valid
D3
11
D2
DAC
D1
Ref
In
D0 (LSB)
Reference Ladder
VREF
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25 °C
Supply Voltages
Output
AVDD...................................................................... +6 V
DVDD ..................................................................... +6 V
Digital Outputs ................................................... 10 mA
Temperature
Input Voltages
Operating Temperature ................................ 0 to 70 °C
Junction Temperature ........................................ 175 °C
Lead Temperature, (soldering 10 seconds) ....... 300 °C
Storage Temperature............................ –65 to +150 °C
Analog Input .............................. –0.5 V to AVDD +0.5 V
VREF .............................................................. 0 to AVDD
CLK Input ............................................................... VDD
AVDD – DVDD .................................................. ±100 mV
AGND – DGND .............................................. ±100 mV
Note: 1. Operation at any Absolute Maximum Rating is not implied.See
Electrical Specifications for proper nominal applied conditions
in typical applications.
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0V, VIN=0 to 4V, ƒS=40 MSPS, VRHS=4.0 V, VRLS=0.0V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7863
TYP
PARAMETERS
Resolution
MIN
MAX
UNITS
10
Bits
DC Accuracy
51% duty cycle
Integral Linearity Error (ILE)
Differential Linearity Error (DLE)
No Missing Codes
VI
VI
VI
±1.0
±0.5
Guaranteed
LSB
LSB
Analog Input
Input Voltage Range
Input Resistance
Input Capacitance
Input Bandwidth
Offset
VI
IV
V
V
V
VRLS
50
VRHS
V
kΩ
pF
MHz
LSB
%
5.0
(Small Signal)
250
±2.0
±0.2
Gain Error
V
Reference Input
Resistance
Bandwidth
Voltage Range
VRLS
VI
V
300
100
500
150
600
Ω
MHz
IV
IV
V
V
V
0
3.0
1.0
2.0
AVDD
5.0
V
V
V
mV
VRHS
VRHS – VRLS
4.0
90
75
∆(VRHF – VRHS
)
∆(VRLS – VRLF
)
mV
Reference Settling Time
VRHS
VRLS
V
V
15
20
Clock Cycles
Clock Cycles
Conversion Characteristics
Maximum Conversion Rate
Minimum Conversion Rate
Pipeline Delay (Latency)
Aperture Delay Time
VI
IV
IV
V
40
2
MHz
MHz
Clock Cycles
ns
12
4.0
30
Aperture Jitter Time
V
ps (p-p)
Dynamic Performance
Effective Number of Bits (ENOB)
ƒIN = 3.58 MHz
VI
V
9.2
8.7
Bits
Bits
ƒIN = 10 MHz
Signal-to-Noise Ratio (SNR)
(without Harmonics)
ƒIN = 3.58 MHz
VI
V
55
57
54
dB
dB
ƒIN = 10 MHz
SPT7863
2
8/21/01
ELECTRICAL SPECIFICATIONS
TA=TMIN to TMAX, AVDD=DVDD=OVDD=+5.0V, VIN=0 to 4V, ƒS=40 MSPS, VRHS=4.0 V, VRLS=0.0V, unless otherwise specified.
TEST
CONDITIONS
TEST
LEVEL
SPT7863
TYP
PARAMETERS
MIN
MAX
UNITS
Dynamic Performance
Total Harmonic Distortion (THD)
ƒIN = 3.58 MHz
VI
V
64
67
62
dB
dB
ƒIN = 10 MHz
Signal-to-Noise and Distortion
(SINAD)
ƒIN = 3.58 MHz
VI
V
V
V
V
54
57
54
70
±0.3
±0.3
dB
dB
dB
Degree
%
ƒ
IN = 10 MHz
Spurious Free Dynamic Range
Differential Phase
Differential Gain
ƒIN = 3.580 MHz
Inputs
Logic 1 Voltage
Logic 0 Voltage
Maximum Input Current Low
Maximum Input Current High
Input Capacitance
VI
VI
VI
VI
VI
2.0
V
V
µA
µA
pF
0.8
+10
+10
–10
–10
+5
Digital Outputs
Logic 1 Voltage
Logic 0 Voltage
tRISE
IOH = 0.5 mA
IOL = 1.6 mA
15 pF load
VI
VI
V
V
V
3.5
V
V
ns
ns
ns
ns
0.4
10
10
10
22
tFALL
15 pF load
Output Enable to Data Output Delay 20 pF load, TA = +25 °C
50 pF load over temp.
V
Power Supply Requirements
Voltages
OVDD
DVDD
AVDD
AIDD
IV
IV
IV
VI
VI
VI
3.0
4.75
4.75
5.0
5.25
5.25
21
21
210
V
V
V
mA
mA
mW
5.0
5.0
17
16
160
Currents
DIDD
Power Dissipation
TEST LEVEL CODES
LEVEL TEST PROCEDURE
All electrical characteristics are subject to the
following conditions:
I
100% production tested at the specified temperature.
II
100% production tested at TA = +25 °C, and sample tested at the
specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
IV
QA sample tested only at the specified temperatures.
Parameter is guaranteed (but not tested) by design and characteri-
zation data.
V
Parameter is a typical value for information purposes only.
VI
100% production tested at TA = +25 °C. Parameter is guaranteed
over specified temperature range.
SPT7863
3
8/21/01
SPECIFICATION DEFINITIONS
APERTURE DELAY
DIFFERENTIAL LINEARITY ERROR (DLE)
Aperture delay represents the point in time, relative to the Error in the width of each code from its theoretical value.
rising edge of the CLOCK input, that the analog input is (Theoretical = VFS/2N)
sampled.
INTEGRAL LINEARITY ERROR (ILE)
APERTURE JITTER
Linearity error refers to the deviation of each individual
The variations in aperture delay for successive samples.
code (normalized) from a straight line drawn from –FS
through +FS. The deviation is measured from the edge of
each particular code to the true straight line.
CLOCK DUTY CYCLE
Ratio of positive clock time (tCH) to total clock period (tCLK
)
OUTPUT DELAY
times 100%.
tCH
Time between the clock’s triggering edge and output data
valid.
Duty Cycle =
X 100%
tCLK
OVERVOLTAGE RECOVERY TIME
DIFFERENTIAL GAIN (DG)
The time required for the ADC to recover to full accuracy
after an analog input signal 125% of full scale is reduced
to 50% of the full-scale value.
A signal consisting of a sine wave superimposed on vari-
ous DC levels is applied to the input. Differential gain is the
maximum variation in the sampled sine wave amplitudes
at these DC levels.
SIGNAL-TO-NOISE RATIO (SNR)
DIFFERENTIAL PHASE (DP)
The ratio of the fundamental sinusoid power to the total
noise power. Harmonics are excluded.
A signal consisting of a sine wave superimposed on vari-
ous DC levels is applied to the input. Differential phase is
the maximum variation in the sampled sine wave phases
at these DC levels.
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
The ratio of the fundamental sinusoid power to the total
noise and distortion power.
EFFECTIVE NUMBER OF BITS (ENOB)
TOTAL HARMONIC DISTORTION (THD)
SINAD = 6.02N + 1.76, where N is equal to the effective
number of bits.
The ratio of the total power of the first 9 harmonics to the
power of the measured sinusoidal signal.
SINAD – 1.76
N =
SPURIOUS FREE DYNAMIC RANGE (SFDR)
6.02
The ratio of the fundamental sinusoidal amplitude to the
single largest harmonic or spurious signal.
INPUT BANDWIDTH
Small signal (50 mV) bandwidth (3 dB) of analog input
stage.
SPT7863
4
8/21/01
Figure 1A – Timing Diagram 1
1
11
13
9
3
17
ANALOG IN
CLOCK IN
7
5
15
SAMPLING
CLOCK
(Internal)
INVALID
VALID
DATA OUTPUT
DATA VALID
1
2
3
4
5
Figure 1B – Timing Diagram 2
tCLK
tC
tCH
tCL
CLOCK IN
DATA
OUTPUT
Data 3
Data 0
Data 1
Data 2
tOD
tS
tCH
tCL
DATA VALID
tS
Table I – Timing Parameters
DESCRIPTION
PARAMETERS
MIN
TYP
MAX UNITS
Conversion Time
tC
tCLK
25
ns
Clock Period
tCLK
tOD
tS
ns
ns
ns
Clock to Output Delay (15 pF Load)
Clock to DAV
17
10
SPT7863
5
8/21/01
Figure 2 – Typical Interface Circuit
DAV
D10
D9
Ref In
(+4 V)
V
V
V
V
RHF
RHS
RLS
RLF
D8
D7
D6
D5
DV
3.3/5
DD
Interfacing
Logics
SPT7863
V
V
IN
IN
DGND
D4
V
CAL
D3
D2
D1
D0
CLK IN
CLK
EN
DD
AV
AGND DGND* DV
DD
3.3/5
Enable/Tri-State
(Enable = Active Low)
+A5
L1
AGND
+A5
DGND
3.3/5
+
10 µF
*To reduce the possibility of latch-up, avoid
connecting the DGND pins of the ADC to the
digital ground of the system.
+
10 µF
+5 V
+5 V
Analog
RTN
+5 V
Digital
RTN
+5 V
Digital
Analog
NOTES: 1) L1 is to be located as closely to the device as possible.
2) All capacitors are 0.1 µF surface-mount unless otherwise specified.
3) L1 is a 10 µH inductor or a ferrite bead.
TYPICAL INTERFACE CIRCUIT
OPERATING DESCRIPTION
Very few external components are required to achieve the The general architecture for the CMOS ADC is shown in
stated device performance. Figure 2 shows the typical in- the block diagram. The design contains 16 identical suc-
terface requirements when using the SPT7863 in normal cessive approximation ADC sections, all operating in par-
circuit operation. The following sections provide descrip- allel, a 16-phase clock generator, an 11-bit 16:1 digital
tions of the major functions and outline critical perfor- output multiplexer, correction logic, and a voltage refer-
mance criteria to consider for achieving the optimal device ence generator that provides common reference levels for
performance.
each ADC section.
The high sample rate is achieved by using multiple SAR
ADC sections in parallel, each of which samples the input
signal in sequence. Each ADC uses 16 clock cycles to
complete a conversion. The clock cycles are allocated as
shown in table II.
POWER SUPPLIES AND GROUNDING
CADEKA suggests that both the digital and the analog sup-
ply voltages on the SPT7863 be derived from a single ana-
log supply as shown in figure 2. A separate digital supply
should be used for all interface circuitry.Fairchild suggests
using this power supply configuration to prevent a possible
latch-up condition on powerup.
SPT7863
6
8/21/01
Table II – Clock Cycles
Figure 3 – Ladder Force/Sense Circuit
Clock
1
2
3
4
Operation
AGND
Reference zero sampling
Auto-zero comparison
Auto-calibrate comparison
Input sample
+
VRHF
5-15
16
11-bit SAR conversion
Data transfer
VRHS
The 16-phase clock, which is derived from the input clock,
synchronizes these events.The timing signals for adjacent
ADC sections are shifted by one clock cycle so that the
analog input is sampled on every cycle of the input clock
by exactly one ADC section. After 16 clock periods, the
timing cycle repeats. The latency from analog input
sample to the corresponding digital output is 12 clock
cycles.
VRLS
+
VRLF
VIN
• Since only 16 comparators are used, a huge power
savings is realized.
All capacitors are 0.01 µF
• The auto-zero operation is done using a closed loop
system that uses multiple samples of the comparator’s
response to a reference zero.
Figure 4 – Reference Ladder
• The auto-calibrate operation, which calibrates the gain
of the MSB reference and the LSB reference, is also
done with a closed loop system. Multiple samples of the
gain error are integrated to produce a calibration volt-
age for each ADC section.
+4.0 V
External
Reference
90 mV
R/2
R
VRHS
(+3.91 V)
• Capacitive displacement currents, which can induce
sampling error, are minimized since only one compara-
tor samples the input during a clock cycle.
R
• The total input capacitance is very low since sections of
the converter that are not sampling the signal are iso-
lated from the input by transmission gates.
R
R
R=30 W (typ)
All capacitors are 0.01 µF
VOLTAGE REFERENCE
R
R
The SPT7863 requires the use of a single external voltage
reference for driving the high side of the reference ladder.
It must be within the range of 3 V to 5 V. The lower side of
the ladder is typically tied to AGND (0.0 V), but can be run
up to 2.0 V with a second reference.The analog input volt-
age range will track the total voltage difference measured
VRLS
(0.075 V)
75 mV
R/2
VRLF
(AGND)
0.0 V
between the ladder sense lines, VRHS and VRLS
.
Force and sense taps are provided to ensure accurate
and stable setting of the upper and lower ladder sense line
voltages across part-to-part and temperature variations.
By using the configuration shown in figure 3, offset and
gain errors of less than ±2 LSB can be obtained.
(chip cap preferred) to minimize high-frequency noise in-
jection. If this simplified configuration is used, the following
considerations should be taken into account.
The reference ladder circuit shown in figure 4 is a simpli-
fied representation of the actual reference ladder with
force and sense taps shown. Due to the actual internal
structure of the ladder, the voltage drop from VRHF to VRHS
In cases where wider variations in offset and gain can be
tolerated, VREF can be tied directly toVRHF, and AGND can
be tied directly to VRLF as shown in figure 4. Decouple
force and sense lines to AGND with a .01 µF capacitor
is not equivalent to the voltage drop from VRLF to VRLS
.
SPT7863
7
8/21/01
Typically, the top side voltage drop for VRHF to VRHS will Upon powerup, the SPT7863 begins its calibration algo-
equal:
rithm. In order to achieve the calibration accuracy re-
quired, the offset and gain adjustment step size is a frac-
tion of a 10-bit LSB. Since the calibration algorithm is an
VRHF – VRHS = 2.25 % of (VRHF – VRLF) (typical),
and the bottom side voltage drop for VRLS to VRLF will oversampling process, a minimum of 10,000 clock cycles
equal:
are required. This results in a minimum calibration time
upon powerup of 250 µsec (for a 40 MHz clock). Once
calibrated, the SPT7863 remains calibrated over time and
VRLS – VRLF = 1.9 % of (VRHF – VRLF) (typical).
Figure 4 shows an example of expected voltage drops for temperature.
a specific case. VREF of 4.0 V is applied to VRHF, and VRLF
Since the calibration cycles are initiated on the rising edge
of the clock, the clock must be continuously applied for the
SPT7863 to remain in calibration.
is tied to AGND. A 90 mV drop is seen at VRHS (= 3.91 V),
and a 75 mV increase is seen at VRLS (= 0.075 V).
ANALOG INPUT
INPUT PROTECTION
VIN is the analog input. The input voltage range is from
VRLS to VRHS (typically 4.0 V) and will scale proportionally
with respect to the voltage reference. (See voltage refer-
ence section.)
All I/O pads are protected with an on-chip protection
circuit shown in figure 6.This circuit provides ESD robust-
ness to 3.5 kV and prevents latch-up under severe dis-
charge conditions without degrading analog transition
The drive requirements for the analog inputs are very times.
minimal when compared to most other converters due to
Figure 6 – On-Chip Protection Circuit
the SPT7863’s extremely low input capacitance of only
5 pF and very high input resistance in excess of 50 kΩ.
VDD
Analog
The analog input should be protected through a series
resistor and diode clamping circuit as shown in figure 5.
120 W
120 W
Figure 5 – Recommended Input Protection Circuit
+V
Buffer
V
AV
DD
Pad
D1
D2
ADC
47 W
POWER SUPPLY SEQUENCING CONSIDERATIONS
All logic inputs should be held low until power to the device
has settled to the specific tolerances. Avoid power decou-
pling networks with large time constants that could delay
VDD power to the device.
D1 = D2 = Hewlett-Packard HP5712 or equivalent
CALIBRATION
The SPT7863 uses an auto-calibration scheme to ensure
10-bit accuracy over time and temperature. Gain and off-
set errors are continually adjusted to 10-bit accuracy
during device operation.This process is completely trans-
parent to the user.
SPT7863
8
8/21/01
CLOCK INPUT
DIGITAL OUTPUTS
The SPT7863 is driven from a single-ended TTL-input The digital outputs (D0–D10) are driven by a separate
clock. Because of the aggressive design of the SPT7863, supply (OVDD) ranging from +3 V to +5 V. This feature
its clock duty cycle ranges from 40% to 51% (see figure 7 makes it possible to drive the SPT7863’s TTL/CMOS-
– DLE vs Clock Duty Cycle). Operation beyond 51% duty compatible outputs with the user’s logic system supply.
cycle may result in missing codes.
The format of the output data (D0–D9) is straight binary.
(See table III.) The outputs are latched on the rising edge
of CLK. These outputs can be switched into a tri-state
mode by bringing EN high.
Figure 7 – DLE vs Clock Duty Cycle
2.0
1.8
1.6
1.4
Table III – Output Data Information
ANALOG INPUT
OVERRANGE
D10
OUTPUT CODE
D9–D0
1.2
1.0
+F.S. + 1/2 LSB
+F.S. –1/2 LSB
+1/2 F.S.
+1/2 LSB
0.0 V
1
0
0
0
0
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1Ø
ØØ ØØØØ ØØØØ
0 0 0 0 0 0 0 0 0 Ø
0 0 0 0 0 0 0 0 0 0
0.8
0.6
0.4
(Ø indicates the flickering bit between logic 0 and 1.)
0.2
0.0
OVERRANGE OUTPUT
0.2
The OVERRANGE OUTPUT (D10) is an indication that
the analog input signal has exceeded the positive full-
scale input voltage by 1 LSB. When this condition occurs,
D10 will switch to logic 1. All other data outputs (D0 to D9)
will remain at logic 1 as long as D10 remains at logic 1.
This feature makes it possible to include the SPT7863 in
higher resolution systems.
0.4
0.6
0.8
1.0
1.2
40
44 46 48 50
38
52
56
54
42
Clock Duty Cycle (%)
EVALUATION BOARD
Figure 8 – ILE vs Clock Duty Cycle
The EB7863 evaluation board is available to aid designers
in demonstrating the full performance of the SPT7863.
This board includes a reference circuit, clock driver circuit,
output data latches, and an on-board reconstruction of the
digital data. An application note describing the operation
of this board, as well as information on the testing of the
SPT7863, is also available. Contact the factory for price
and availability.
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
40
44 46 48 50
38
52
56
54
42
Clock Duty Cycle (%)
SPT7863
9
8/21/01
PACKAGE OUTLINES
28-Lead SOIC
INCHES
MILLIMETERS
SYMBOL
MIN
0.699
0.005
0.050 typ
0.018 typ
0.0077
0.090
0.031
0.396
0.286
MAX
0.709
0.011
MIN
17.75
0.13
1.27 typ
0.46 typ
0.20
2.29
0.79
MAX
18.01
0.28
28
A
B
I
H
C
D
E
F
G
H
I
0.0083
0.096
0.039
0.416
0.292
0.21
2.44
0.99
10.57
7.42
1
10.06
7.26
A
F
B
C
D
H
G
E
32-Lead TQFP
G
H
A
INCHES
MILLIMETERS
B
SYMBOL
MIN
MAX
0.362
0.280
0.362
0.280
MIN
MAX
9.20
7.10
9.20
7.10
A
B
C
D
E
F
G
H
I
0.346
0.272
0.346
0.272
8.80
6.90
8.80
6.90
0.031 typ
0.80 BSC
0.012
0.053
0.002
0.037
0.016
0.057
0.006
0.041
0.007
7°
0.30
1.35
0.05
0.95
0.40
1.45
0.15
1.05
0.17
7°
C
D
J
K
L
I
0°
0.020
0°
0.50
J
0.030
0.75
E
F
K
L
SPT7863
10
8/21/01
PIN ASSIGNMENTS
PIN FUNCTIONS
Name
AGND
VRHF
VRHS
VRLS
VRLF
VCAL
VIN
Function
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
D10
D9
AGND
Analog Ground
VRHF
Reference High Force
Reference High Sense
Reference Low Sense
Reference Low Force
Calibration Reference
Analog Input
VRHS
D8
N/C
VRLS
VRLF
D7
D6
D5
VIN
AGND
VCAL
OVDD
OGND
SOIC
AVDD
DVDD
DGND
CLK
Analog VDD
Digital VDD
20 D4
19 D3
18 D2
17 D1
Digital Ground
Input Clock ƒCLK = FS (TTL)
Output Enable
AVDD 10
DVDD 11
EN
D0–9
D10
Tri-State Data Output, (D0=LSB)
Tri-State Output Overrange
Data Valid Output
Digital Output Supply
Digital Output Ground
No Connect
DGND
CLK
12
13
14
D0
EN
16
15
DAV
DAV
OVDD
OGND
N/C
VRLF
VIN
1
2
3
4
5
6
7
8
24 D7
23 D6
22 D5
AGND
AGND
VCAL
OVDD
21
TQFP
20 OGND
19 D4
18 D3
17 D2
AVDD
AVDD
DVDD
ORDERING INFORMATION
PART NUMBER
SPT7863SCS
SPT7863SCT
TEMPERATURE RANGE
0 to +70 °C
PACKAGE TYPE
28L SOIC
32L TQFP
0 to +70 °C
SPT7863
11
8/21/01
相关型号：
SPT7866SIR
ADC, Proprietary Method, 10-Bit, 1 Func, 1 Channel, Parallel, Word Access, CMOS, PDSO28, SSOP-28
FAIRCHILD
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