SPT9691SCN [CADEKA]
WIDE INPUT VOLTAGE, JFET COMPARATOR; 宽广的输入电压，比较器JFET
| 型号： | SPT9691SCN |
| 厂家： | 
CADEKA MICROCIRCUITS LLC. |
| 描述： | WIDE INPUT VOLTAGE, JFET COMPARATOR |
| 文件： | 总10页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPT9691
WIDE INPUT VOLTAGE, JFET COMPARATOR
FEATURES
APPLICATIONS
•
•
•
•
•
•
Common Mode Range -4.0 to +8.0 V
•
•
•
•
•
•
•
•
Automated Test Equipment
High-Speed Instrumentation
Window Comparators
High-Speed Timing
Line Receivers
High-Speed Triggers
Threshold Detection
Peak Detection
Low Input Bias Current <100 pA
Propagation Delay 2.5 ns (max)
Low Offset ±25 mV
Low Feedthrough and Crosstalk
Differential Latch Control
GENERAL DESCRIPTION
The SPT9691 is a high-speed, wide common mode voltage,
JFET input, dual comparator. It is designed for applications
that measure critical timing parameters in which wide com-
mon mode input voltages of -4.0 to +8.0 V are required.
Propagation delays are constant for overdrives greater than
200 mV.
most applications. The device has differential analog inputs
and complementary logic outputs compatible with ECL sys-
tems. Each comparator has a complementary latch enable
control that can be driven by standard ECL logic.
The SPT9691 is available in 20-lead PLCC, 20-lead plastic
DIP and 20-contact LCC packages over the commercial
temperature range. It is also available in die form.
JFET inputs reduce the input bias currents to the nanoamp
level, eliminating the need for input drivers and buffers in
BLOCK DIAGRAM
QA
QB
QA
QB
GND
A
A
A
GNDB
LEB
LEB
LE
LE
A
B
DVEE(A)
DVEE(B)
AVEE(A)
AVCC(A)
AVEE(B)
AVCC (B)
-INB
-INA
+INA
+INB
ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25°C
Supply Voltages (Measured to GND)
Positive Supply Voltage (AV ).............. -0.5 to +11.0 V
Output
Output Current .......................................................30 mA
CC
Negative Supply Voltage (AV ) ............ -11.0 to +0.5 V
EE
Negative Supply Voltage (DV ) .............. -6.0 to +0.5 V
Temperature
EE
Operating Temperature, ambient.................. 0 to +70 °C
junction ....................... +150 °C
Input Voltages
Input Common Mode Voltage ........ DV -1 to +AV +1
Lead Temperature, (soldering 60 seconds) ........ +300 °C
Storage Temperature................................ -65 to +150 °C
EE
CC
Differential Input Voltage ...................... -12.0 to +12.0 V
Input Voltage, Latch Controls .................. DV to 0.5 V
EE
V
V
to AV Differential Voltage ................ -16 to +1.0 V
IN
IN
CC
to AV Differential Voltage................ +4 to +21.0 V
EE
Note: 1. OperationatanyAbsoluteMaximumRatingisnotimplied. SeeElectricalSpecificationsforpropernominalapplied
conditionsintypicalapplications. Applicationofmultiplemaximumratingconditionsatthesametimemaydamage
the device.
ELECTRICAL SPECIFICATIONS
T
= +25 °C, AV = +10 V, AV =-10.0 V, DV =-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified.
CC EE EE
A
TEST
TEST
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Input Offset Voltage
V
=0
I
IV
V
I
-25
-25
0.0
0.0
+25
+25
mV
mV
µV/°C
nA
nA
nA
nA
mA
mA
mA
V
IN,CM
T
< T <T
A MAX
MIN
Offset Voltage Tempco
Input Bias Current
50
±0.1
±2.0
±1.0
±10
25
±10
Input Bias Current
T
T
<T <T
IV
V
V
I
±100
MIN
MIN
A
MAX
Input Offset Current
Input Offset Current
<T <T
A
MAX
Positive Supply Current (Dual)
Negative Supply Current (Dual)
Negative Supply Current (Dual)
AVcc=10 V
AV =-10.0 V
33
20
I
15
EE
DV =-5.2 V
EE
I
55
70
Positive Supply Voltage, AV
IV
IV
IV
I
9.75
-9.75
-4.95
-4.0
10.0
-10.0
-5.2
10.25
-10.25
-5.45
+8.0
CC
Negative Supply Voltage, AV
Negative Supply Voltage, DV
Input Common Mode Range
Latch Enable
V
EE
V
EE
V
Common Mode Range
Differential Voltage Range
Open Loop Gain
IV
I
-2.0
0
V
±10
V
V
V
60
2
dB
GΩ
pF
pF
pF
dB
dB
dB
Differential Input Resistance
Input Capacitance
LCC Package
PLCC Package
PDIP
1.0
1.0
2.9
60
60
55
Power Supply Sensitivity
V
I
Common Mode Rejection Ratio
50
45
T
< T <T
MAX
IV
MIN
A
SPT9691
10/6/97
2
ELECTRICAL SPECIFICATIONS
T
= +25 °C, AV
= +10 V, AV =-10.0 V, DV =-5.2 V, RL = 50 Ohm to -2V, unless otherwise specified.
CC EE EE
A
TEST
TEST
PARAMETERS
CONDITIONS
LEVEL
MIN
TYP
MAX
UNITS
DC ELECTRICAL CHARACTERISTICS
Power Dissipation
Dual
I
I
I
700
895
-.70
mW
V
Output High Level
ECL 50 Ohms to -2V
ECL 50 Ohms to -2V
-.98
Output Low Level
-1.95
-1.65
V
AC ELECTRICAL CHARACTERISTICS
1
Propagation Delay
150 mV O.D.
IV
V
V
V
V
V
V
V
V
V
V
1.5
2.0
2
2.5
ns
Propagation Delay TEMPCO
ps/ °C
ps
Propagation Delay Skew (A vs B)
100
200
1.7
0.8
2
2
Propagation Delay Dispersion
150 mV Overdrive Min.
150 mV O.D.
ps
Latch Set-up Time
Latch to Output Delay
Latch Pulse Width
Latch Hold Time
Rise Time
ns
ns
ns
-1.9
0.4
0.4
3
ns
20% to 80%
20% to 80%
ns
Fall Time
ns
Slew Rate
V/ns
NOTES:
1
Valid for both high-to-low and low-to-high transitions.
2
Dispersion is the change in propagation delay due to changes in slew rate, overdrive, and common mode level.
TEST LEVEL
TEST PROCEDURE
100% production tested at the specified temperature.
TEST LEVEL CODES
All electrical characteristics are subject to the
following conditions:
I
II
100% production tested at T =25 °C, and sample
A
tested at the specified temperatures.
All parameters having min/max specifications
are guaranteed. The Test Level column indi-
cates the specific device testing actually per-
formed during production and Quality Assur-
ance inspection. Any blank section in the data
column indicates that the specification is not
tested at the specified condition.
III
QA sample tested only at the specified temperatures.
IV
Parameter is guaranteed (but not tested) by design
and characterization data.
V
Parameter is a typical value for information purposes
only.
VI
100% production tested at T = 25 °C. Parameter is
A
guaranteed over specified temperature range.
SPT9691
10/6/97
3
TIMING INFORMATION
The leading edge of the input signal (which consists of a
150 mV overdrive voltage) changes the comparator output
after a time of t
or t
(Q or ). The input signal must be
Q
pdH
s
The timing diagram for the comparator is shown in figure 1.
If LE is high and LE low in the SPT9691, the comparator
tracks the input difference voltage. When LE is driven low
and LE high, the comparator outputs are latched into their
existing logic states.
pdL
maintained for a time t (set-up time) before the LE falling
edge and
rising edge and held for time t after the falling
LE
H
edge for the comparator to accept data. After t , the output
H
ignores the input status until the latch is strobed again. A
minimum latch pulse width of t is needed for strobe opera-
pL
tion, and the output transitions occur after a time of t
or
pLOH
t
.
pLOL
Figure 1 - Timing Diagram
Latch Enable
50%
Latch Enable
tpL
tH
tS
Differential
Input Voltage
V
V
Ref ± OS
V
OD
tpLOH
tpdL
Output Q
50%
50%
Output Q
tpLOL
tpdH
V
+=300 mV,
=150 mV
V
OD
IN
The set-up and hold times are a measure of the time required for an input signal to propagate through the
first stage of the comparator to reach the latching circuitry. Input signals occurring before t will be detected
s
and held; those occurring after t will not be detected. Changes between t and t may not be detected.
H
S
H
SWITCHING TERMS (Refer to figure 1)
t
t
t
t
INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output LOW to HIGH transition.
t
MINIMUM HOLD TIME - The minimum time after the
negative transition of the Latch Enable signal that the
input signal must remain unchanged in order to be
acquired and held at the outputs.
pdH
H
INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the input signal crosses
the reference voltage (± the input offset voltage) to the
50% point of an output HIGH to LOW transition.
t
t
MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire an input signal change.
pdL
pL
MINIMUM SET-UP TIME - The minimum time before
the negative transition of the Latch Enable signal that
an input signal change must be present in order to be
acquired and held at the outputs.
S
LATCH ENABLE TO OUTPUT HIGH DELAY - The
propagation delay measured from the 50% point of the
Latch Enable signal LOW to HIGH transition to 50%
point of an output LOW to HIGH transition.
pLOH
pLOL
V
VOLTAGE OVERDRIVE - The difference between the
differential input and reference input voltages.
OD
LATCH ENABLE TO OUTPUT LOW DELAY - The
propagation delay measured from the 50% point of the
LatchEnablesignalLOWtoHIGHtransitiontothe50%
point of an output HIGH to LOW transition.
SPT9691
10/6/97
4
TYPICAL PERFORMANCE CURVES
INPUT BIAS CURRENT VS COMMON MODE VOLTAGE
(+25 °C)
INPUT OFFSET VOLTAGE VS COMMON MODE VOLTAGE
(T=+25 °C)
100
+10.0
+6.0
10
+2.0
-2.0
1.0
0.1
0.01
-6.0
0.001
-10.0
-4.0
-1.6
+0.8
+3.2
+5.6
+8.0
-4.0
-1.6
+0.8
+3.2
+5.6
+8.0
COMMON MODE VOLTAGE (V)
COMMON MODE VOLTAGE (V)
PROPOGATION DELAY TIME VS TEMPERATURE
PROPAGATION DELAY TIME VS OVERDRIVE (mV)
(V
=150 mV)
OD
3.0
2.8
2.6
2.4
2.2
2.0
1.8
2.4
2.2
2.0
1.8
1.6
1.4
0
50
100
150
200
250
300
350
0
+25
+50
+75
+100
OVERDRIVE (mV)
TEMPERATURE (°C)
RISE AND FALL OF OUTPUTS VS TIME CROSSOVER
HYSTERESIS VS ∆LATCH
-.90
20
15
-1.10
VIN (CM) = 0.0 V
-1.30
10
-1.50
-1.70
5
0
-1.90
-20
0
20
40
60
1.1
1.5
1.9
TIME (ns)
2.3
2.7
3.5
∆LATCH = (VLE - VLE) mV
SPT9691
10/6/97
5
GENERAL INFORMATION
A common mode voltage range of -4 V to +8 V is achieved by
a proprietary JFET input design which requires a separate
The SPT9691 is an ultrahigh-speed dual voltage compara-
tor. It offers tight absolute characteristics. The device has
differential analog inputs and complementary logic outputs
compatible with ECL systems. The output stage is adequate
for driving terminated 50 ohm transmission lines.
negative power supply (AV ).
EE
The dual comparators have separate AV
AV DV and
EE, EE,
CC,
grounds for each comparator to achieve high crosstalk rejec-
tion. Single channel operation can be accomplished by float-
ing all pins (including the ground and supply pins) of the
unused comparator. Power dissipation during single channel
operation is 50% of the dissipation during dual channel
operation.
The SPT9691 has a complementary latch enable control for
each comparator. Both should be driven by standard ECL
logic levels.
Figure 2 - Internal Function Diagram
Q
+IN
- IN
+
-
PRE
AMP
ECL
OUT
LATCH
Q
REF
1
REF
2
CLK
BUF
LE
LE
AV
DV
V
CC
GND
EE
EE
SPT9691
10/6/97
6
-2 V. All outputs on the active comparator, whether used or
unused, should have identical terminations to minimize
ground current switching transients.
TYPICAL INTERFACE CIRCUIT
The typical interface circuit using the comparator is shown in
figure 3. Although it needs few external components and is
easy to apply, there are several conditions that should be
noted to achieve optimal performance. The very high operat-
ing speeds of the comparator require careful layout, decou-
pling of supplies, and proper design of transmission lines.
Diode D1 connected between AV
and GND is recom-
CC
mended to prevent possible damage to the device in case
the AV supply is disconnected. The diode should be a
CC
1N914 or equivalent. If AV is disconnected with this diode
CC
in place, there will be approximately a 6 mA current draw
from both AV and DV . Diode D2 connected between
EE
EE
Since the SPT9691 comparator is a very high frequency and
high gain device, certain layout rules must be followed to
avoid oscillations. The comparator should be soldered to the
board with component lead lengths kept as short as possible.
A ground plane should be used, while the input impedance to
the part is kept as low as possible, to decrease parasitic
feedback. If the output board traces are longer than approxi-
mately half an inch, microstripline techniques must be em-
ployed to prevent ringing on the output waveform. Also, the
microstriplines must be terminated at the far end with the
characteristic impedance of the line to prevent reflections. All
supply voltage pins should be decoupled with high frequency
capacitors as close to the device as possible. All ground pins
should be connected to the same ground plane to further
improve noise immunity and shielding. If using the SPT9691
as a single comparator, the outputs of the inactive compara-
tor can be grounded, left open or terminated with 50 Ohms to
AV
and DV
is necessary to avoid power supply se-
EE
EE
quencelatch-up. ThisdiodekeepsAV (alsothesubstrate)
EE
less than a silicon diode drop away from the most negative
circuitpotentialifDV ispoweredupfirst. Thisdiodeshould
EE
be a 1N5817 (Schottky) or equivalent.
Note: At no time should both inputs be allowed to float with
power applied to the device. At least one of the inputs should
be tied to a voltage within the common mode range (-4.0 to
+8.0 V) to prevent possible damage to the device. To prevent
possible latch-up during initial power up, the input voltages
should not exceed ±1 V. Additional protection diodes D3-D6
should be used on the inputs if there is the possibility of
exceeding the absolute maximum ratings of the inputs with
respecttoAV andDV (1N914orequivalent). NOTE:For
CC
EE
ease of implementation, all diodes (D1 - D6) can be 1N5817
(Schottky) or equivalent.
Figure 3 - SPT9691 Typical Interface Circuit
Figure 4 - SPT9691 Typical Interface Circuit With
Hysteresis
D1
D1
D2
D2
.1 µF
.1 µF
.1 µF
.1 µF
.1 µF
.1 µF
D3
D3
D6
D5
D6
D4
D4
D5
Noninverting Input
Noninverting Input
V
Q Output
Q Output
IN
+
Q Output
Q Output
V
V
IN
+
-
LE
V
LE
REF
Inverting Input
-
LE
REF
Inverting Input
LE
R
R
L
50 Ω
L
R
R
L
L
50 Ω
50 Ω
50 Ω
-1.3 V
.1 µF
.1 µF
100 Ω
ECL
-2 V
-2 V
.1 µF
-2 V
= Represents line termination.
GND
AV
DV
AV
EE CC
= Represents line termination.
EE
AV
DV
AV
EE CC
GND
EE
SPT9691
10/6/97
7
PACKAGE OUTLINES
20-Lead Plastic DIP
INCHES
MIN
MILLIMETERS
MIN MAX
SYMBOL
MAX
0.300
A
B
C
D
E
F
7.62
0.66
0.014
0.026
.100 typ
.010 typ
1.20 typ
0.330
0.36
2.54
20
0.25
30.48
8.38
G
0.290
0.246
1.010
7.37
6.25
G
H
0.254
6.45
1
1.030
25.65
26.16
H
F
E
A
D
B
C
20-Lead Plastic Leaded Chip Carrier (PLCC)
A
G
B
INCHES
MIN
MILLIMETERS
MIN MAX
SYMBOL
MAX
Pin 1
N
A
B
C
D
E
F
G
H
I
.045 typ
1.14
TOP
VIEW
M
O
F
0.350
0.356
0.395
0.356
0.395
0.056
0.180
0.110
0.040
0.025
0.032
0.021
0.050
0.330
8.89
9.04
10.03
9.04
10.03
1.42
4.57
2.79
1.02
0.64
0.81
0.53
1.27
8.38
E
0.385
0.350
0.385
0.042
0.165
0.085
0.025
0.015
0.026
0.013
9.78
8.89
9.78
1.07
4.19
2.16
0.64
0.38
0.66
0.33
L
K
C
D
J
I
H
J
K
L
Pin 1
M
N
O
BOTTOM
VIEW
0.290
7.37
SPT9691
10/6/97
8
PACKAGE OUTLINES
20-Contact Leadless Chip Carrier (LCC)
A
H
INCHES
MIN
MILLIMETERS
MIN MAX
SYMBOL
MAX
G
A
B
C
D
E
F
.040 typ
.050 typ
0.055
1.02
1.27
1.40
9.14
1.68
0.51
0.71
1.91
Bottom
View
0.045
1.14
Pin 1
0.345
0.054
0.360
8.76
1.37
B
C
0.066
.020 typ
0.028
G
H
0.022
0.56
0.075
F
D
E
SPT9691
10/6/97
9
PIN ASSIGNMENTS
PIN FUNCTIONS
NAME
FUNCTION
1
2
QA
QA
20 QB
Q
Output A
A
A
19 QB
Inverted Output A
Ground A
Q
3
GND
A
A
A
18 GNDB
17 LEB
GND
A
4
LE
LE
Inverted Latch Enable A
LE
A
5
16
LEB
LE
Latch Enable A
A
DIP/PDIP
AV (A)
Positive Supply Voltage (+10 V)
Negative Supply Voltage (-10 V)
Negative Supply Voltage (-5.2 V)
Positive Supply Voltage (+10 V)
Negative Supply Voltage (-10 V)
Negative Supply Voltage (-5.2 V)
Inverting Input A
6
15
DVEE(A)
AVEE(A)
AVCC(A)
DVEE(B)
CC
AV (A)
EE
7
14
13
12
11
AVEE(B)
AVCC (B)
-INB
DV (A)
EE
8
AV (B)
CC
-INA
9
AV (B)
EE
+INA
10
+INB
DV (B)
EE
-IN
A
+IN
+IN
Noninverting Input A
A
B
Noninverting Input B
Q
3
A
Q
2
A
Q
1
B
Q
20
B
GND
19
B
-IN
Inverting Input B
B
Inverted Latch Enabled B
LE
LE
B
B
LE
B
GND
LE
LE
A
4
18
17
LE
Latch Enable B
Ground B
B
A
A
5
6
TOP VIEW
LCC/PLCC
GND
B
16 DVEE(B)
15 AVEE(B)
Inverted Output B
Q
B
B
DVEE(A)
AVEE(A)
7
8
Q
Output B
14
AVCC(B)
9
10
11
+IN
13
12
+IN
AVCC(A) -IN
A
A
B
-INB
ORDERING INFORMATION
PART NUMBER
SPT9691SCC
SPT9691SCN
SPT9691SCP
SPT9691SCU
TEMPERATURE RANGE
0 to +70 °C
PACKAGE TYPE
20C LCC
0 to +70 °C
20L Plastic DIP
0 to +70 °C
20L Plastic Leaded Chip Carrier (PLCC)
Die*
+25 °C
*Please see the die specification for guaranteed electrical performance.
SPT9691
10/6/97
10
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