CMM8870SI [CALMIRCO]
DTMF Signaling Circuit, CMOS, PDSO18, SOIC-18;
| 型号： | CMM8870SI |
| 厂家： | 
CALIFORNIA MICRO DEVICES CORP |
| 描述： | DTMF Signaling Circuit, CMOS, PDSO18, SOIC-18 电信 光电二极管 电信集成电路 |
| 文件： | 总8页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CALIFORNIA MICRO DEVICES
CM8870/70C
CMOS Integrated DTMF Receiver
Features
Applications
• Full DTMF receiver
• PABX
• Less than 35mW power consumption
• Industrial temperature range
• Central office
• Mobile radio
• Uses quartz crystal or ceramic resonators
• Adjustable acquisition and release times
• Remote control
• Remote data entry
• Call limiting
• 18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin
PLCC
• Telephone answering systems
• Paging systems
• CM8870C
—
—
—
Power down mode
Inhibit mode
Buffered OSC3 output (PLCC package only)
• CM8870C is fully compatible with CM8870 for 18-pin
devices by grounding pins 5 and 6
Product Description
The CAMD CM8870/70C provides full DTMF receiver capability by integrating both the bandsplit filter and digital
decoder functions into a single 18-pin DIP, SOIC, or 20-pin PLCC package. The CM8870/70C is manufactured using
state-of-the-art CMOS process technology for low power consumption (35mW, max.) and precise data handling. The
filter section uses a switched capacitor technique for both high and low group filters and dial tone rejection. The
CM8870/70C decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a
4-bit code. This DTMF receiver minimizes external component count by providing an on-chip differential input ampli-
fier, clock generator, and a latched three-state interface bus. The on-chip clock generator requires only a low cost TV
crystal or ceramic resonator as an external component.
C1550900
www.calmicro.com
© 2000 California Micro Devices Corp. All rights reserved.
9/28/2000 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
1
CM8870/70C
CALIFORNIA MICRO DEVICES
Absolute Maximum Ratings: (Note 1)
This device contains input protection
against damage due to high static
voltages or electric fields; however,
precautions should be taken to avoid
application of voltages higher than the
maximum rating.
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Power Supply Voltage (VDD
-
VDD
6.0V Max
VSS
)
Notes:
Voltage on any Pin
Current on any Pin
Operating Temperature
Storage Temperature
Vdc
IDD
TA
VSS-0.3V to VDD+0.3V
10mA Max
1. Exceeding these ratings may cause
permanent damage, functional
operation under these conditions is
not implied.
-40°C to +85°C
-65°C to +150°C
TS
DC Characteristics: All voltages referenced to VSS, VDD = 5.0V 5ꢀ, TA = -40°C to +85°C unless otherwise noted.
DC CHARACTERISTICS
Parameter
Symbol
VDD
IDD
Min
4.75
Typ
3.0
15
Max
5.25
7.0
25
Units
V
Test Conditions
Operating Supply Voltage
Operating Supply Current
Standby Supply Current
Power Consumption
mA
µA
mW
V
IDDQ
PO
PD=VDD
f=3.579 MHz; VDD=5.0V
VDD=5.0V
35
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
VIL
1.5
VIH
3.5
V
VDD=5.0V
IIH/LIL
Iso
0.1
6.5
10
µA
µA
MΩ
V
VIN = VSS = VDD (Note 1)
TOE=0V, VDD=5.0V
@ 1KHz
Pull Up (Source) Current on TOE
Input Impedance, (IN+, IN-)
Steering Threshold Voltage
Low Level Output Voltage
High Level Output Voltage
Output Low (Sink) Current
Output High (Source) Current
20
RIN
8
VTst
VOL
VOH
IOL
2.2
2.5
VDD = 5.0V
0.03
V
VDD = 5.0V, No Load
VDD = 5.0V, No Load
VOUT = 0.4V
4.97
1.0
V
2.5
0.8
mA
mA
V
IOH
0.4
VOUT = 4.6V
Output Voltage
VREF
VREF
ROR
2.4
2.7
VDD = 5.0V, No Load
Output Resistance
10
ΚΩ
Operating Characteristics: All voltages referenced to VSS, VDD = 5.0V 5ꢀ, TA = -40°C to +85°C unless otherwise noted.
Gain Setting Amplifier
OPERATING CHARACTERISTICS
Parameter
Input Leakage Current
Symbol
Min
Typ
Max
Units
nA
Test Conditions
VSS < VIN < VDD
IIN
±100
Input Resistance
RIN
10
MΩ
mV
dB
Input Offset Voltage
VOS
PSRR
CMRR
AVOL
fc
±25
Power Supply Rejection
Common Mode Rejection
DC Open Loop Voltage Gain
Open Loop Unity Gain Bandwidth
Output Voltage Swing
50
40
1KHz (Note 12)
dB
-3.0V < VIN < 3.0V
32
dB
0.3
4.0
MHz
VP-P
pF
VO
RL ≥ 100KW to VSS
Maximum Capacitive Load (GS)
Maximum Resistive Load (GS)
Common Mode Range (No Load)
CL
100
50
RL
KΩ
Vcm
2.5
VP-P
No Load
©2000 California Micro Devices Corp. All rights reserved.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com 9/28/2000
2
CALIFORNIA MICRO DEVICES
CM8870/70C
AC Characteristics: All voltages referenced to VSS, VDD=5.0V 5ꢀ, TA=-40°C to +85°C, fCLK=3.579545 MHz using
test circuit (Fig. 1) unless otherwise noted.
AC CHARACTERISTICS
Parameter
Symbol
Min
-29
Typ
Max
+1
Units
dBm
mVRMS
dB
Notes
Valid Input Signal Levels
(each tone of composite signal)
1,2,3,4,5,8
27.5
869
Positive Twist Accept
10
2,3,4,8
Negative Twist Accept
10
dB
Freq. Deviation Accept Limit
Freq. Deviation Reject Limit
1.5%±2Hz
Nom.
Nom.
2,3,5,8,10
2,3,5
±3.5%
Third Tone Tolerance
Noise Tolerance
-16
-12
dB
dB
2,3,4,5,8,9,13,14
2,3,4,5,6,8,9
2,3,4,5,7,8,9
Dial Tone Tolerance
+22
8
dB
mS
mS
mS
mS
mS
µS
Tone Present Detection Time
Tone Absent Detection Time
Min Tone Duration Accept
Max Tone Duration Reject
Min. Interdigit Pause Accept
Max. Interdigit Pause Reject
Propagation Delay (St to Q)
Propagation Delay (St to StD)
Output Data Set Up (Q to StD)
tDP
tDA
tREC
tREC
tID
5
14
8.5
40
Refer to
Timing Diagram
0.5
3
(User Adjustable)
Times shown are
obtained with
20
20
40
circuit in Fig. 1)
tDO
tPQ
tPS D
QStD
6
9
11
16
µS
t
µS
TOE = VDD
t
3.4
µS
Enable
Disable
tPTE
tPTD
fCLK
50
nS
RL = 10KΩ
CL = 50pF
Propagation Delay (TOE to Q)
300
3.5795
nS
Crystal/Clock Frequency
Clock Output (OSC 2)
3.5759
3.5831
30
MHz
Capacitive
Load
CLO
pF
Notes:
1.
dBm = decibels above or below a reference power
of 1 mW into a 600 ohm load.
9.
Referenced to lowest level frequency component
in DTMF signal.
Minimum signal acceptance level is measured with
specified maximum frequency deviation.
Input pins defined as IN+, IN-, and TOE.
2.
3.
4.
5.
Digit sequence consists of all 16 DTMF tones.
Tone duration = 40mS. Tone pause = 40 mS.
Nominal DTMF frequencies are used.
Both tones in the composite signal have
an equal amplitude.
Bandwidth limited (0 to 3 KHz) Gaussian Noise.
The precise dial tone frequencies are
(350 Hz and 440 Hz) 2ꢀ.
10.
11.
12.
13.
External voltage source used to bias VREF
.
This parameter also applies to a third tone injected onto
the power supply.
Referenced to Figure 1. Input DTMF tone level
at -28 dBm.
6.
7.
14.
8.
For an error rate of better than 1 in 10,000
© 2000 California Micro Devices Corp. All rights reserved.
9/28/2000 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
3
CM8870/70C
CALIFORNIA MICRO DEVICES
Explanation of Events
A) Tone bursts detected, tone duration invalid, outputs not
updated.
B) Tone #n detected, tone duration valid, tone decoded
and latched in outputs.
C) End of tone #n detected, tone absent duration valid,
outputs remain latched until next valid tone.
D) Outputs switched to high impedance state.
E) Tone #n + 1 detected, tone duration valid, tone decoded
and latched in outputs (currently high impedance).
F) Acceptable dropout of tone #n + 1, tone absent duration
invalid, outputs remain latched.
Q1-Q4 4-bit decoded tone output.
StD
Delayed Steering Output. Indicates that
valid frequencies have been present/absent
for the required guard time, thus constituting
a valid signal.
TOE
tREC
Tone Output Enable (input). A low level
shifts Q1-Q4 to its high impedance state.
Maximum DTMF signal duration not
detected as valid.
tREC
Minimum DTMF signal duration required
for valid recognition.
G) End of tone #n + 1 detected, tone absent duration valid,
outputs remain latched until next valid tone.
tID
tDO
Minimum time between valid DTMF signals.
Maximum allowable drop-out during valid
DTMF signal.
Explanation of Symbols
tDP
tDA
Time to detect the presence of valid
DTMF signals.
Time to detect the absence of valid
DTMF signals.
Guard time, tone present.
Guard time, tone absent.
VIN
ESt
DTMF composite input signal.
Early Steering Output. Indicates detection
of valid tone frequencies.
tGTP
tGTA
St/GT Steering input/guard time output. Drives
external RC timing circuit.
©2000 California Micro Devices Corp. All rights reserved.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com 9/28/2000
4
CALIFORNIA MICRO DEVICES
CM8870/70C
Functional Description
The CAMD CM8870/70C DTMF Integrated Receiver provides
the design engineer with not only low power consumption, but
high performance in a small 18-pin DIP, SOIC, or 20-pin PLCC
package configuration. The CM8870/70C’s internal architec-
ture consists of a bandsplit filter section which separates the
high and low tones of the received pair, followed by a digital
decode (counting) section which verifies both the frequency
and duration of the received tones before passing the result-
ant 4-bit code to the output bus.
considered a valid pause. This capability together with the
capability of selecting the steering time constants externally,
allows the designer to tailor performance to meet a wide
variety of system requirements.
Guard Time Adjustment
In situations which do not require independent selection of
receive and pause, the simple steering circuit of Figure 4 is
applicable. Component values are chosen according to the
following formula:
Filter Section
tREC = tDP + tGTP
tGTP » 0.67 RC
Separation of the low-group and high-group tones is achieved
by applying the dual-tone signal to the inputs of two 9th-order
switched capacitor bandpass filters. The bandwidths of these
filters correspond to the bands enclosing the low-group and
high-group tones (See Figure 3). The filter section also
incorporates notches at 350 Hz and 440 Hz which provides
excellent dial tone rejection. Each filter output is followed by a
single order switched capacitor section which smooths the
signals prior to limiting. Signal limiting is performed by high-
gain comparators. These comparators are provided with a
hysteresis to prevent detection of unwanted low-level signals
and noise. The outputs of the comparators provide full-rail
logic swings at the frequencies of the incoming tones.
The value of tDP is a parameter of the device and tREC is the
minimum signal duration to be recognized by the receiver. A
value for C of 0.1 uF is recommended for most applications,
leaving R to be selected by the designer. For example, a
suitable value of R for a tREC of 40 milliseconds would be 300K.
A typical circuit using this steering configuration is shown in
Figure 1. The timing requirements for most telecommunica-
tion applications are satisfied with this circuit. Different
steering arrangements may be used to select independently
the guardtimes for tone-present (tGTP) and tone absent (tGTA).
This may be necessary to meet system specifications which
place both accept and reject limits on both tone duration and
interdigit pause.
Decoder Section
The CM8870/70C decoder uses a digital counting technique
to determine the frequencies of the limited tones and to verify
that these tones correspond to standard DTMF frequencies.
A complex averaging algorithm is used to protect against tone
simulation by extraneous signals (such as voice) while
providing tolerance to small frequency variations. The
averaging algorithm has been developed to ensure an
optimum combination of immunity to “talk-off” and tolerance to
the presence of interfering signals (third tones) and noise.
When the detector recognizes the simultaneous presence of
two valid tones (known as “signal condition”), it raises the
“Early Steering” flag (ESt). Any subsequent loss of signal
condition will cause ESt to fall.
Guard time adjustment also allows the designer to tailor
system parameters such as talk-off and noise immunity.
Increasing tREC improves talk-off performance, since it reduces
the probability that tones simulated by speech will maintain
signal condition for long enough to be registered. On the
other hand, a relatively short tREC with a long tDO would be
appropriate for extremely noisy environments where fast
acquisition time and immunity to drop-outs would be require-
ments. Design information for guard time adjustment is shown
in Figure 5.
Input Configuration
The input arrangement of the CM8870/70C provides a
differential input operational amplifier as well as a bias source
(VREF) which is used to bias the inputs at mid-rail.
Steering Circuit
Before the registration of a decoded tone pair, the receiver
checks for a valid signal duration (referred to as “character-
recognition-condition”). This check is performed by an
external RC time constant driven by ESt. A logic high on ESt
causes VC (See Figure 4) to rise as the capacitor discharges.
Providing signal condition is maintained (ESt remains high) for
the validation period (tGTP), VC reaches the threshold (VTSt) of
the steering logic to register the tone pair, thus latching its
corresponding 4-bit code (See Figure 2) into the output latch.
At this point, the GT output is activated and drives VC to VDD.
GT continues to drive high as long as ESt remains high,
signaling that a received tone pair has been registered. The
contents of the output latch are made available on the 4-bit
output bus by raising the three-state control input (TOE) to a
logic high. The steering circuit works in reverse to validate the
interdigit pause between signals. Thus, as well as rejecting
signals too short to be considered valid, the receiver will
tolerate signal interruptions (drop outs) too short to be
Provision is made for connection of a feedback resistor to the
op-amp output (GS) for adjustment of gain.
In a single-ended configuration, the input pins are connected
as shown in Figure 1, with the op-amp connected for unity
gain and VREF biasing the input at ½ VDD. Figure 6 shows the
differential configuration, which permits the adjustment of gain
with the feedback resistor R5.
Clock Circuit
The internal clock circuit is completed with the addition of a
standard television color burst crystal or ceramic resonator
having a resonant frequency of 3.579545 MHz. The
CM8870C in a PLCC package has a buffered oscillator output
(OSC3) that can be used to drive clock inputs of other devices
such as a microprocessor or other CM887X’s as shown in
Figure 7. Multiple CM8870/70Cs can be connected as shown
in figure 8 such that only one crystal or resonator is required.
© 2000 California Micro Devices Corp. All rights reserved.
9/28/2000 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
5
CM8870/70C
CALIFORNIA MICRO DEVICES
Pin Function Table
PIN FUNCTION
Name
IN+
Description
Non-inverting Input
Inverting Input
Connection to the front-end differential amplifier
IN-
Gives access to output of front-end differential amplifier for connection of
feedback resistor.
GS
Gain Select
VREF
INH
Reference voltage output (nominally VDD/2). May be used to bias the inputs at mid-rail.
Inhibits detection of tones represents keys A, B, C, and D
OSC3
PD
Digital buffered oscillator output.
Power Down
Clock Input
Clock Output
Logic high powers down the device and inhibits the oscillator.
OSC1
OSC2
VSS
3.579545 MHz crystal connected between these pins completes internal oscillator.
Negative power supply (normally connected to OV).
TOE
Three-state output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up.
Q1
Q2
Q3
Q4
Three-state outputs. When enabled by TOE, provides the code corresponding to the last valid tone pair
received. (See Fig. 2).
Delayed steering output. Presents a logic high when a received tone pair has been registered and the output
StD
ESt
latch is updated. Returns to logic low when the voltage on St/GT falls below VTSt
.
Early steering output. Presents a logic high immediately when the digital algorithm detects a recognizable
tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low.
Steering input/guard time output (bidirectional). A voltage greater than VTSt detected a St causes the
device to register the detected tone pair . The GT output acts to reset the external steering time constant, and its
state is a function of ESt and the voltage on St. (See Fig. 2)
St/Gt
VDD
IC
Positive power supply.
Internal Connection.
Must be tied to VSS (for 8870 configuration only)
FLOW
697
697
FHIGH
1209
1336
KEY TOW Q4
Q3
0
0
Q2
0
1
Q1
1
0
1
H
0
2
H
0
697
770
770
770
852
852
852
941
941
941
697
770
852
941
-
1477
1209
1336
1477
1209
1336
1477
1209
1336
1477
1633
1633
1633
1633
-
3
4
5
6
7
8
9
0
·
#
A
B
C
D
ANY
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
0
0
0
0
0
1
1
1
1
1
1
1
1
0
Z
0
1
1
1
1
0
0
0
0
1
1
1
1
0
Z
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Z
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Z
All resistors are 1%tolerance.
All capacitors are 5% tolerance.
L = logic Low, H = Logic High, Z = High Impedance
Figure 2.
Functional Diode Table
Figure 1.
Single Ended Input Configuration
©2000 California Micro Devices Corp. All rights reserved.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com 9/28/2000
6
CALIFORNIA MICRO DEVICES
CM8870/70C
Figure 3. Typical Filter Characteristic
Figure 4. Basic Steering Circuit
Figure 5. Guard Time Adjustment
Figure 6. Differential Input Configuration
© 2000 California Micro Devices Corp. All rights reserved.
9/28/2000 215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
7
CM8870/70C
CALIFORNIA MICRO DEVICES
OSC1
OSC2
OSC1
OSC2
OSC1
OSC2
OSC1
OSC2
OSC3
OSC1 of other CM887X’s
Clock input of other devices
3.58 Mhz 30pF
30pF
30pF
Figure 7. CM8870C Crystal Connection
(PLCC Package Only)
Figure 8. CM8870/70C Crystal Connection
Pin Assignments
IN+
IN-
GS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
V
DD
IN+
IN-
GS
1
2
3
4
5
6
7
8
9
18
17
16
15
14
13
12
11
10
VDD
St/GT
ESt
StD
Q4
St/GT
ESt
StD
Q4
VREF
VREF
GS
4
5
6
7
8
18 ESt
17 StD
16 NC
15 Q4
14 Q3
V
REF
4
5
6
7
8
18 Est
17 StD
16 NC
15 Q4
14 Q3
*
IC
INH
VREF
INH
PD
CM8870
CM8870C
*
*
*
*
IC
OSC1
OSC2
Q3
IC
OSC1
OSC2
Q3
IC
Q2
Q2
IC
OSC3
OSC1
Q1
Q1
OSC1
VSS
TOE
VSS
TOE
PE — PLCC (20)
PE — PLCC (20)
* — Connect To VSS
P — Plastic DIP (18)
F — Plastic SOP
EIAJ (18)
P — Plastic DIP (18)
F — Plastic SOP
EIAJ (18)
S — SOIC (18)
S — SOIC (18)
Ordering Information
CM8870
CM8870C
Example:
P
I
Product Identification Number
Package
P
F
PE
S
—
—
—
—
Plastic DIP (18)
Plastic SOP EIAJ (18)
PLCC (20)
SOIC (18)
Temperature/Processing
None
I
—
—
0OC to +70OC, 5ꢀ P.S. Tol.
-40OC to +85OC, 5ꢀ P.S. Tol.
©2000 California Micro Devices Corp. All rights reserved.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com 9/28/2000
8
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