CMPWR160SA [CALMIRCO]
USB peripheral Power Management; USB外设的电源管理
| 型号： | CMPWR160SA |
| 厂家： | 
CALIFORNIA MICRO DEVICES CORP |
| 描述： | USB peripheral Power Management |
| 文件： | 总10页 (文件大小：125K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CALIFORNIA MICRO DEVICES
CMPWR160
USB Peripheral Power Management
Features
Applications
• 3.3V regulated output up to 500mA
• Quiescent current 35µA (typical)
• Shutdown mode current 7µA (typical)
• 30ms active LOW Power-On Reset (POR) pulse
• Thermal overload protection
• Bus-powered USB peripherals
• Self-powered USB peripherals
• Portable/battery-powered devices
• Critical power monitoring, hot-insertion devices
• Foldback current limiting protection
• Reverse-current protection
• 8 pin SOIC power package
The SmartORTM CMPWR160 combines a Low Dropout
Regulator (LDO) with a Power-On Reset (POR) pulse
generator, and is intended for Universal Serial Bus
(USB) peripherals. To meet the specification require-
ments of both USB 1.0 and USB 2.0, the CMPWR160
draws a very low quiescent current (35µA), and delivers
up to 500mA of load current at a fixed 3.3V output.
When VCC is powered down, the device will automatically
enter reverse-current protection mode and maintain
isolation between VOUT and VCC. This is useful for applica-
tions that can use power from the USB port in addition to
internal batteries or an AC adapter supply (Wired-ORed
power systems). In the event of VCC collapsing below
VOUT, the device will automatically enter shutdown mode
and fully isolate the VCC power source from the output.
The POR pulse (active LOW) has a typical duration of
30ms after the output has exceeded and stabilized
above 2.9V. Thus a new POR pulse is developed each
time the regulator power is interrupted and restored,
which occurs often on USB buses when cables are
connected (or disconnected) by the user. It is not
necessary to have a VCC supply for POR to operate,
allowing the CMPWR160 to work in Wired-ORed power
systems.
A ShutDown input (SD) forces the regulator to be
powered down on demand. While in shutdown mode the
POR circuitry will remain active, making the device
suitable for systems which contain backup or alternative
power sources.
The CMPWR160 is available in an 8-pin SOIC thermally
enhanced package, ideal for applications where space
is tight.
Block Diagram
VCC
Top View
SD
V
1
2
3
4
8
7
6
5
GND
GND
GND
GND
CC
SD
+
SD
VREF
3.3V
–
POR
VOUT
3.3V/500mA
V
OUT
+
GND
CMPWR160
8 LEAD SOIC
POR
30ms
–
Pin Diagram
2.9V
Simplified Electrical Schematic
Package
Ordering Part Number
Pin
Style
Power SOIC
Tubes
Tape & Reel
Part Marking
8
CMPWR160SA/T
CMPWR160SA/R
CMPWR160SA
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
C1571000
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
12/5/2000
1
CALIFORNIA MICRO DEVICES
CMPWR160
Parameter
ESD Protection (HBM)
VCC/VOUT Voltage
Rating
Unit
V
2000
6.0, GND –0.5
VCC + 0.5, GND –0.5
VOUT + 0.5, GND –0.5
V
SD Logic Input Voltage
POR Logic Output Voltage
Temperature: Storage
V
V
–40 to 150
0 to 70
0 to 125
Operating Ambient
Operating Junction
C
˚
Power Dissipation Note 1
Internally Limited
Range
Parameter
Unit
VCC
4.2 to 5.5
V
Temperature (Ambient)
Load Current
CEXT
0 to 70
C
˚
0 to 500
mA
µF
10 10ꢀ
Symbol
VOUT
ILIM
Parameter
Conditions
MIN
3.135
550
TYP
MAX
3.465
UNIT
V
Regulator Output Voltage
Regulator Current Limit
Short-Circuit Current Limit
Load Regulation
0mA < ILOAD < 500mA
3.30
mA
mA
mV
mV
V
IS/C
300
75
2
VR LOAD
VR LINE
VDO
VCC = 5V, ILOAD = 5mA to 500mA
VCC = 4.2V to 5.5V, ILOAD = 5mA
MIN VCC –VOUT for ILOAD = 500mA
Regulator Enabled (No Load)
Regulator Disabled
Line Regulation
Regulator Dropout Voltage
Quiescent Supply Current
Shutdown Supply Current
VCC Pin Reverse Leakage
Shutdown High Detect
Shutdown Low Detect
POR Detect Threshold
POR Pulse Duration
0.6
35
7
0.9
50
10
10
IQ
µA
µA
µA
V
ISD
IRCC
VOUT = 3.3V, VCC = 0V
VCC = 5V
1
VIH SD
VIL SD
VPOR
TPOR
RPOR
3.0
1.0
2.9
30
0.5
VCC = 5V
V
4.2V < VCC < 5.5V
2.8
20
3.0
40
2
V
ms
kΩ
POR Output Impedance
After POR Threshold Detected
0.2
Sinking to GND/Sourcing from VCC
TDISABLE Shutdown Temperature
THYST Thermal Hysteresis
160
20
C
˚
˚
C
Note 1: The SOIC package used is thermally enhanced through the use of a fused integral leadframe. The power rating is based on a printed
circuit board heat spreading capability equivalent to 2 square inches of copper connected to the GND pins. Typical multi-layer boards
using power plane construction will provide this heat spreading ability without the need for additional dedicated copper area. (Please
consult with factory for thermal evaluation assistance.)
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
2
12/5/2000
CALIFORNIA MICRO DEVICES
CMPWR160
Interface Signals
V
CC is the input power source for the Low Drop Out
ately enters reverse protection mode to prevent any
Regulator, capable of delivering 3.3V/500mA output
current even when the input is as low as 4.2V.
current flow back into the regulator pass transistor.
Under these conditions VOUT will also be used to provide
the necessary quiescent current for the internal refer-
Internal loading on this pin is typically 35µA when the
regulator is enabled, which reduces to only 7µA when-
ever the regulator is shutdown (SD taken Low). In the
event of VCC collapsing below VOUT, the loading at VCC will
immediately reduce to less than 0.1µA.
POR
ence and
circuits. This ensures excellent start-up
characteristics for the regulator.
POR
is the Power-On-Reset output pin (Active Low).
When VOUT rises above the POR threshold voltage
(typically 2.9V), the pin is forced to logic low (GND). The
pin remains logic low for 30ms then it is forced logic high
(3.3V). If VOUT falls below the POR threshold voltage
during this 30ms interval POR will remain logic low. If it
falls below the voltage threshold and then recovers the
30ms time will reset.
If the VCC pin is within a few inches of the main input
filter, a capacitor may not be necessary. Otherwise an
input filter capacitor in the range of 1µF to 10µF will
ensure adequate filtering.
is the regulator shutdown input logic signal which is
SD
Active Low. This is a true CMOS input signal referenced
to VCC supply. When the pin is tied High (VCC ) the
regulator operates fully. When the pin is taken to GND,
the device enters shutdown mode and the regulator is
fully disabled. In this mode all critical POR circuitry
remains fully powered consuming less than 7µA (typical).
POR
If VOUT falls below the POR threshold voltage
immediately forced to logic low.
is
The power-on reset circuitry is designed to remain active
under all conditions and will produce a valid output even
when VCC is not present. A very low quiescent current
(7µA typical) ensures continuous operation of the POR
circuit.
V
OUT is the regulator output voltage used to power the
load. An output capacitor of 10µF is used to provide the
necessary phase compensation, thereby preventing
oscillation. The capacitor also helps to minimize the peak
output disturbance during line or load transients. When-
ever VCC collapses below the output the device immedi-
GND is the negative reference for all voltages. This
current that flows in the ground connection is very low
(35µA typical with the regulator enabled and 7µA typical
with the regulator disabled).
Symbol
Description
VCC
SD
Positive supply input for regulator. When VCC falls below VOUT the regulator is disabled.
Shutdown control input signal (Active Low) to disable internal voltage regulator and current supply
to less than 7µA.
POR
VOUT
Power-On-Reset output signal is held Low until the output has been stable (>2.9V) for at least 30ms.
Regulator voltage ouput (3.3V) capable of delivering 500mA when device is enabled (SD is High).
Whenever the output exceeds 2.9V (TYP) the POR pulse is triggered.
GND
Negative reference for all voltages
CMPWR160
uP Reset
V
CC
POR
+
C
V
OUT
3.3V/500mA
IN
SD
V
OUT
V
CC
5V
1µF
GND
+
+
C
OUT
–
10µF
GND
Typical Application Circuit
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
12/5/2000
3
CALIFORNIA MICRO DEVICES
CMPWR160
Typical DC Characteristics
Unless stated otherwise, all DC characteristics were
measured at room temperature with a nominal VCC
supply voltage of 5V and an output capacitance of 10µF.
Resistive load conditions were used.
Line Regulation Characteristics of the regulator are
shown in Figure 1. At maximum rated load conditions
(500mA), a 100mV drop in regulation occurs when the
line voltage has collapses below 3.8V. For light load
conditions (5mA), regulation is maintained for line
voltages as low as 3.3V.
3.35
3.30
3.25
3.20
3.15
3.10
3.05
5mA Load
500mA Load
3.0
3.5
4.0
(V)
4.5
5.0
V
CC
Figure 1. Line Regulation
Load Regulation performance is shown from zero to
maximum rated load in Figure 2. A 10ꢀ to 100ꢀ change
of rated load, results in an output voltage change of less
than 10mV. This translates into an effective output
impedance of approximately 0.02Ω.
3.40
3.35
3.30
3.25
3.20
0
200
400
600
Load Current (mA)
Figure 2. Load Regulation
Ground Current is shown across the entire range of
load conditions in Figure 3. The ground current increases
by 40µA across the range of load conditions. This
increase is due to the current limiting protective circuitry
becoming active.
100
80
60
40
20
0
0
200
400
600
Load Current (mA)
Figure 3. Ground Current
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
4
12/5/2000
CALIFORNIA MICRO DEVICES
CMPWR160
Typical DC Characteristics continued
VCC Operating Current (no load,
high) is shown
SD
60
50
40
30
20
across a range of VCC supply voltages with the regulator
enabled in Figure 4. The graph shows that the operating
current is 35µA typical and changes by less than 1µA
across this range.
10
0
3.5
4.5
5.5
V
(V)
CC
Figure 4. VCC Operating Current (no load)
VCC Shutdown Current variation with the VCC supply
voltage is shown in Figure 5.
10
8
6
4
2
0
1.5
2.5
3.5
(V)
4.5
5.5
V
CC
Figure 5.VCC Shutdown Current
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
12/5/2000
5
CALIFORNIA MICRO DEVICES
CMPWR160
TypicalTransient Characteristics
The transient characterization test setup is shown in
Figure 6. It was the setup used for the transient tests
unless specified otherwise.
In the line transient characterizations the VCC supply
voltage was controlled to step between 4.5 to 5.5V.
For the response characterization VCC and SD were
POR
A maximum rated load current of 6.6Ω (500mA @ 3.3V)
was used during characterization along with a nominal
tied to ground and the VOUT voltage was directly driven
between 2.7 and 3.1V. This was done by connecting a
function generator directly to the output of the device.
These voltage values were picked because it drove VOUT
V
CC supply voltage of 5V DC, unless specified otherwise.
The load transient characterization was done by switch-
ing between 6.6 and 660Ω load resistors. This switched
the load between 500 and 5mA respectively.
directly across the typical
threshold voltage of 2.9V.
POR
VCC was tied to ground to show that the
circuitry will
POR
operate even when the VCC supply voltage is not present.
For the VCC power-up and power-down characterizations
VCC supply was ramped between 0 and 5V. Both the rise
and fall times for the VCC power-up/down pulses were
controlled to be 15ms.
The oscilloscope traces show the full bandwidth re-
SD
,
POR, VCC and VOUT pins depending on
sponse at the
the characterization.
CMPWR160
V
POR
POR
CC
SD
V
OUT
V
OUT
V
CC
+
C2
C1
GND
C4
C3
(500mA)
6.6Ω
+
0.1µF
10µF
10µF
0.1µF
GND
GND
Figure 6.Transient CharacterizationTest Setup
VCC power-up Cold Start
Tek Run 25.0kS/s Sample
Figure 7 shows the output response during an initial VCC
power up with SD tied to VCC. When VCC reaches a
particular threshold, the regulator turns on. The un-
charged output capacitor causes maximum inrush
current to flow. At this point the device sees the output
as a short circuit and the device enters a protective
current limiting mode. The output capacitor quickly
charges and VOUT rises. Once this voltage rises to just
below VCC the inrush current stops flowing and the output
rises with the input. VOUT continues to rise with the input
until it reaches 3.3V.
V
CC
V
OUT
(500mA Load)
M 2.00ms Ch2
Ch2 1.00V
280mV
1.00V
Figure 7.VCC Power-up Cold Start
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
6
12/5/2000
CALIFORNIA MICRO DEVICES
CMPWR160
Typical Transient Characteristics continued
Tek Run 25.0kS/s Sample
VCC Power down
Figure 8 shows the output response of the regulator
during a complete power down situation under full load
V
CC
SD
conditions with
tied to VCC.
V
OUT
(500mA Load)
M 2.00ms Ch2
Ch2 1.00V
3.50V
1.00V
Figure 8.VCC Power Down
Tek
25.0kS/s 3 Acqs
ShutdownTransient Response
The transient response of the output voltage to the SD
pin is shown in Figure 9. The graph shows that a rising
SD
edge on the
pin enables the regulator and a falling
SD
edge disables the regulator.
2
The rise and fall time for the output voltages are 100µs
and 200µs respectively.
(500mA Load)
V
OUT
M 200µs Ch2
3.0V
1.00V
Ch2 5.00V
Figure 9. ShutdownTransient Response
POR
Response
Tek Run 5.0kS/s Sample
The transient response of the active low POR pin to VOUT
is shown in Figure 10. When VOUT rises above the
3.1V
POR
threshold voltage (typically 2.9V), the pin is forced
to logic low (0V). The pin remains at logic low for 30ms
then it is forced to logic high (3.3V). If VOUT falls below the
POR threshold voltage during this 30ms interval POR
will remain logic low. If it falls below the voltage threshold
and then recovers the 30ms time will reset.
V
OUT
2
2.7V
POR
POR
is
When VOUT falls below the
immediately forced to logic low.
threshold voltage
V
CC is tied to ground to show that the POR circuitry will
POR
work without VCC present.
M 10.0ms Ch2
2.90V
1.00V
Ch2 200mV
POR
Figure 10.
Response
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
12/5/2000
7
CALIFORNIA MICRO DEVICES
CMPWR160
Typical Transient Characteristics continued
Load Step response
Figure 11 shows the output voltage (Ch1) response of
the regulator during a step load change between 5mA
and 500mA (represented on Ch2). For the 5mA to
500mA transition an initial transient overshoot of 60mV
occurs and then the output settles to its final voltage
within 20µs. For the 500mA to 5mA transition there is
also an initial overshoot of 60mV however it takes
approximately 250µs to settle to its final voltage.
Tek Run 250kS/s Sample
500mA
Load
5mA
The overall DC voltage disturbance on the output is
approximately 25mV, which demonstrates the regulator
output impedance of 50mΩ.
1
VOUT (offset = 3.3V)
V
OUT offset = 3.3V
M 200µs Ch2
1.60V
Ch1 50.0mV
2.00V
Figure 11. Load Step Response
Line Step Response
Tek
250kS/s
2 Acqs
Figure 12 shows the output response of the regulator to
a VCC line voltage transient between 4.5V and 5.5V
(1Vpp as shown on Ch2). The load condition during this
test is 5mA. The output response produces less than
10mV of disturbance on both edges indicating a line
rejection of better than 40dB at high frequencies.
5.5V
V
CC
2
V
OUT offset = 3.3V
4.5V
(5mA Load)
V
OUT(offset = 3.3V)
M 200µs Ch2
5.00V
20.0mV Ch2 500mV
Figure 12. Line Step Response
Reset response time with overdrive
POR
Figure 13 shows the time it takes for the
signal to
POR
1000
reset when the output voltage is driven below the
trigger threshold by varying amounts. The amount the
voltage is driven below the POR trigger threshold is the
overdrive voltage.
100
10
1
0
50
100
150
200
250
300
Overdrive (mV)
Figure 13. Reset ResponseTime with Overdrive
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
8
12/5/2000
CALIFORNIA MICRO DEVICES
CMPWR160
Typical Thermal Characteristics
Based on a maximum power dissipation of
1.0W (2Vx500mA) with an ambient of 70°C the resulting
junction temperature will be:
Thermal dissipation of junction heat consists primarily of
two paths in series. The first path is the junction to the
case (θJC) thermal resistance which is defined by the
package style, and the second path is the case to
ambient (θCA) thermal resistance, which is dependent on
board layout.
T
JUNC = TAMB + PJUNC (θJA )
= 70°C + 1.0W (50°C/W)
= 70°C + 50°C = 120°C
The overall junction to ambient (θJA) thermal resistance is
equal to:
All thermal characteristics of the CMPWR160SA were
measured using a double sided board with two square
inches of copper area connected to the GND pins for
“heat spreading”.
θJA = θJC + θCA
For a given package style and board layout, the operat-
ing junction temperature is a function of junction power
dissipation PJUNC, and the ambient temperature, resulting
in the following thermal equation:
Measurements showing performance up to junction
temperature of 125°C were performed under light load
conditions (5mA). This allows the ambient temperature to
be representative of the internal junction temperature.
T
JUNC = TAMB + PJUNC (θJC ) + PJUNC (θCA
= TAMB + PJUNC (θJA)
)
Note: The use of multi-layer board construction with
power planes will further enhance the thermal perfor-
mance of the package. In the event of no copper area
being dedicated for heat spreading, a multi-layer board
construction, using only the minimum size pad layout,
will typically provide the CMPWR160SA with an overall
θJA of 70°C/W which allows up to 780mW to be safely
dissipated.
The CMPWR160SA is housed in a thermally enhanced
package where all the GND pins (5 through 8) are
integral to the leadframe (fused leadframe). When the
device is mounted on a double sided printed circuit
board with two square inches of copper allocated for
“heat spreading”, the resulting θJA is 50°C/W.
OutputVoltage vs.Temperature
Figure 14 shows the regulator VOUT performance up to
the maximum rated junction temperature. A 125°C
variation in junction temperature from –25°C causes an
output voltage variation of about 50mV, reflecting
a voltage temperature coefficient of approximately
50ppm/°C.
3.35
3.33
3.31
3.29
3.27
3.25
–25
0
25
50
75
100
125
Temperature (˚C)
Figure 14.VOUT TemperatureVariation (5mA)
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
12/5/2000
9
CALIFORNIA MICRO DEVICES
CMPWR160
Typical Thermal Characteristics continued
OutputVoltage (Rated) vs.Temperature
3.34
3.32
3.30
3.28
Figure 15 shows the regulator steady state performance
when fully loaded (500mA) from –25°C up to the rated
maximum temperature of 70°C. The output variation at
maximum load is approximately 20mV across the shown
operating temperature. This translates to a temperature
coefficient of approximately 30ppm/°C.
3.26
3.24
–25
0
25
50
Temperature (˚C)
Figure 15.VOUT TemperatureVariation (500mA)
POR VoltageThresholdTemperatureVariation
3.00
2.95
2.90
POR
Figure 16 shows the
threshold voltage variation
from –25°C up to the maximum rated junction tempera-
ture. The overall 150°C change in junction temperature
causes less than a 5mV variation in the POR threshold
voltage. This translates to a temperature coefficient of
6ppm/°C.
The POR pulse duration does not vary with temperature.
2.85
3.24
–25
0
25
50
75
100
125
Temperature (˚C)
POR
Figure 16.
Threshold
TemperatureVariation
VCC Supply CurrentTemperatureVariation
40
Figure 17 shows the VCC supply current variation with
temperature from –25°C to the maximum rated junction
temperature with no load on the device. The supply
current changes less than 1µA over the entire 150°C
range shown in the plot.
38
36
34
32
30
–25
0
25
50
75
100
125
Temperature (˚C)
Figure 17.VCC Supply Current
vs.Temperature
©2000 California Micro Devices Corp. All rights reserved. SmartOR™ is a trademark of California Micro Devices Corporation.
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
10
12/5/2000
相关型号：
©2020 ICPDF网 联系我们和版权申明