PACDN016M/T [CALMIRCO]
Trans Voltage Suppressor Diode, Unidirectional, 12 Element, Silicon, MSOP-8;
| 型号： | PACDN016M/T |
| 厂家： | 
CALIFORNIA MICRO DEVICES CORP |
| 描述： | Trans Voltage Suppressor Diode, Unidirectional, 12 Element, Silicon, MSOP-8 局域网 光电二极管 |
| 文件： | 总3页 (文件大小：134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CALIFORNIA MICRO DEVICES
PAC DN016
6 CHANNEL ESD PROTECTION ARRAY WITH ZENER SUPPLY CLAMP
Features
Applications
Six channels of ESD protection
Integral Zener diode clamp to suppress
supply rail transient
15KV ESD protection (HBM)
8KV contact, 15KV air ESD protection
per IEC 61000-4-2
I/O port protection for cellular
phones, notebook computers, PDAs, etc.
ESD protection for VGA (Video) port in
PCs or Notebook computers.
ESD protection for sensitive
electronic equipment.
Low loading capacitance, 3pF typ
Miniature 8-pin MSOP or SOIC package
Product Description
The PAC DN016 is a diode array designed to provide 6 channels of ESD protection for electronic components or sub-
systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (VP) or
negative (VN) supply. In addition, there is an integral Zener diode between VP and VN to suppress any voltage
disturbance due to these ESD current pulses. The PAC DN016 will protect against ESD pulses up to 15KV Human
Body Model, and 8KV contact discharge per International Standard IEC 61000-4-2.
This device is particularly well-suited for portable electronics (e.g. cellular phones, PDAs, notebook computers) because of
its small package footprint, high ESD protection level, and low loading capacitance. It is also suitable for protecting video
output lines and I/O ports in computers and peripheral equipment.
SCHEMATIC CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Diode Forward DC Current (Note 1)
Storage Temperature
20mA
-65°C to 150°C
-20°C to 85°C
Operating Temperature Range
DC Voltage at any Channel Input VN-0.5V to VP+0.5V
Note 1: Only one diode conducting at a time.
S TA N D A R D S P E C IF IC A TIO N S
Param eter
Operating Supply Voltage (V -V )
Min.
Typ.
Max.
5.5V
P
N
Supply Current @ V -V = 5.5V
20µA
0.95V
P
N
Diode Forward Voltage, I = 20mA, T = 25°C
0.65V
F
Zener clamp reverse breakdown voltage @ 1mA, T = 25°C
ESD Protection
6.6V
Peak Discharge Voltage at any Channel Input, in-system (Note 2)
000Human Body Model, Method 3015 (Note 3, 4)
000Contact Discharge per IEC 61000-4-2 (Note 5)
±
±
15KV
8KV
Channel Clamp Voltage @ 15KV ESD HBM, T = 25°C
(Notes 3, 4)
000Positive transients
V + 13.0V
P
000Negative transients
V - 13.0V
N
Channel Leakage Current, T = 25°C
± 0.1µA
3pF
± 1.0 µA
Channel Input Capacitance (Measured @ 1 MHz)
V = 5V, V = 0V, V = 2.5V (Note 4)
6pF
P
N
INPUT
Package Power Rating
000SOIC Package
000MSOP Package
350mW
200mW
Note 2: From I/O pins to VP or VN only. Bypass opacitor between VP and VN is not required. However, a 0.2 µF ceramic chip
capacitor bypassing VP to VN is recommended if the lowest possible channel clamp voltage is desired.
Note 3: Human Body Model per MIL-STD-883, Method 3015, CDischarge=100pF, RDischarge=1.5KΩ, VP=5.0V, VN=GND.
Note 4: This parameter is guaranteed by design and characterization.
Note 5: Standard IEC 61000-4-2 with CDischarge=150pF, and RDischarge=330Ω, VP=5V, VN=GND.
C0540399
© 1999 Calirornia Micro Devices Corp. All rights reserved.
PAC is a trademark of California Micro Devices Corp.
11/99
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
1
CALIFORNIA MICRO DEVICES
PAC DN016
Input Capacitance vs. Input Voltage
5
4
3
2
1
0
0
1
2
3
4
5
Input Voltage
Typical variation of CIN with VIN (VP=5V, VN=0V)
(VP = 5V, VN = 0V, 0.1µF chip capacitor between VP & VN)
S TA N D A R D P A R T O R D E R IN G IN F O R M A TIO N
Package
Ordering Part Num ber
Part Marking
Pins
Style
SOIC
8
8
PACDN016S
MSOP
PACDN016M
When placing an order please specify desired shipping: Tubes or Tape & Reel.
Application Information
See also California Micro Devices Application note AP209, Design Considerations for ESD protection.
In order to realize the maximum protection against ESD pulses, care must be taken in the PCB layout to minimize parasitic
series inductances to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse
applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is
represented by L1. The voltage VZ on the line being protected is:
VZ = Forward voltage drop of D1 + L1 x d(Iesd)/dt + VSupply
where Iesd is the ESD current pulse, and VSupply is the positive supply voltage.
Figure 1
An ESD current pulse can rise from zero to its peak value in a very short time. As an example, a level 4 contact discharge per
the IEC 61000-4-2 standard results in a current pulse that rises from zero to 30 Amps in 1nS. Here d(Iesd)/dt can be
approximated by ∆Iesd/∆t, or 30/(1x10-9). So just 10nH of series inductance (L1) will lead to a 300V increment in VZ!
©1999 California Micro Devices Corp. All rights reserved.
2
11/99
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
CALIFORNIA MICRO DEVICES
PAC DN016
Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to drastically increased
negative voltage on the line being protected.
Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a
much higher output impedance to fast transient current spikes. In the VZ equation above, the VSupply term, in reality, is given
by (VDC + Iesd x Rout), where VDC and Rout are the nominal supply DC output voltage and effective output impedance of the
power supply respectively. As an example, a Rout of 1 ohm would result in a 10V increment in VZ for a peak Iesd of 10A.
To mitigate these effects, a Zener diode has been integrated into this Protection Array between VP and VN. This Zener diode
clamps the maximum voltage of VP relative to VN at the breakdown voltage of the Zener diode. Although not strictly necessary,
it is recommended that VP be bypassed to the ground plane with a high frequency bypass capacitor. This will lower the
channel clamp voltage, and is especially effective when VP is much lower than the Zener breakdown voltage. The value of this
bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in VP.
Typically a value in the 0.1 µF to 0.2 µF range is adequate for IEC-61000-4-2 level 4 contact discharge protection (8KV). For
higher ESD voltages, the bypass capacitor should be increased accordingly. Ceramic chip capacitors mounted with short
printed circuit board traces are good choices for this application. Electrolytic capacitors should be avoided as they have poor
high frequency characteristics.
As a general rule, the ESD Protection Array should be located as close as possible to the point of entry of expected electrostatic
discharges. The power supply bypass capacitor mentioned above should be as close to the VP pin of the Protection Array as
possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance.
Figure 5
© 1999 Calirornia Micro Devices Corp. All rights reserved.
4
8/99
215 Topaz Street, Milpitas, California 95035
Tel: (408) 263-3214
Fax: (408) 263-7846
www.calmicro.com
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