CAT1025ZD4I-25GT2 [CATALYST]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, 3 X 3 MM, 0.80 MM HIEGHT, ROHS COMPLIANT, MO-229WEEC, TDFN-8;
| 型号： | CAT1025ZD4I-25GT2 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8, 3 X 3 MM, 0.80 MM HIEGHT, ROHS COMPLIANT, MO-229WEEC, TDFN-8 光电二极管 |
| 文件： | 总20页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT1024, CAT1025
Supervisory Circuits with I2C Serial 2k-bit
CMOS EEPROM and Manual Reset
FEATURES
DESCRIPTION
ꢀ Precision Power Supply Voltage Monitor
The CAT1024 and CAT1025 are complete memory
— 5V, 3.3V and 3V systems
— Five threshold voltage options
ꢀ Active High or Low Reset
— Valid reset guaranteed at VCC = 1V
ꢀ 400kHz I2C Bus
and supervisory solutions for microcontroller-based
systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together in low power CMOS techno–
logy. Memory interface is via a 400kHz I2C bus.
The CAT1025 provides a precision VCC sense circuit
and two open drain outputs: one (RESET) drives high
ꢀ 2.7V to 5.5V Operation
ꢀ Low power CMOS technology
ꢀ 16-Byte Page Write Buffer
ꢀ Built-in inadvertent write protection
— WP pin (CAT1025)
¯¯¯¯¯¯
and the other (RESET) drives low whenever VCC falls
below the reset threshold voltage. The CAT1025 also
has a Write Protect input (WP). Write operations are
disabled if WP is connected to a logic high.
The CAT1024 also provides a precision VCC sense
ꢀ 1,000,000 Program/Erase cycles
ꢀ Manual Reset Input
¯¯¯¯¯¯
circuit, but has only a RESET output and does not
have a Write Protect input.
ꢀ 100 year data retention
The power supply monitor and reset circuit protect
memory and system controllers during power up/down
and against brownout conditions. Five reset threshold
voltages support 5V, 3.3V and 3V systems. If power
supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller,
ASIC or peripherals from operating. Reset signals
become inactive typically 200 ms after the supply
voltage exceeds the reset threshold level. With both
active high and low reset signals, interface to
microcontrollers and other ICs is simple. In addition,
ꢀ Industrial and extended temperature ranges
ꢀ Green packages available with NiPdAu Lead
finished
¯¯¯¯¯¯
¯¯¯
the RESET pin or a separate input, MR, can be used
as an input for push-button manual reset capability.
For Ordering Information details, see page 19.
The CAT1024/25 memory features a 16-byte page. In
addition, hardware data protection is provided by a
VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until
VCC reaches the reset threshold during power up.
Available packages include an 8-pin DIP and a
surface mount 8-pin SO, 8-pin TSSOP, 8-pin TDFN
and 8-pin MSOP packages. The TDFN package thick-
ness is 0.8mm maximum. TDFN footprint is 3x3mm.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 3008 Rev. N
CAT1024, CAT1025
BLOCK DIAGRAM
THRESHOLD VOLTAGE OPTION
EXTERNAL LOAD
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
SENSEAMPS
SHIFT REGISTERS
D
OUT
ACK
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
V
CC
WORDADDRESS
BUFFERS
COLUMN
DECODERS
V
SS
START/STOP
SDA
WP*
LOGIC
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
HIGHVOLTAGE/
TIMING CONTROL
RESET Controller
STATE COUNTERS
SCL
Precision
Vcc Monitor
SLAVE
ADDRESS
COMPARATORS
MR
RESET*
RESET
* CAT1025 Only
PIN CONFIGURATION
DIP Package (L)
(Bottom View)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (ZD4)
¯¯¯
MR
¯¯¯
MR
VCC
NC
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
VCC
NC
¯¯¯¯¯¯
RESET
¯¯¯¯¯¯
RESET
CAT1024
CAT1025
CAT1024
CAT1025
NC
VSS
SCL
SDA
SCL
SDA
NC
VSS
¯¯¯
MR
¯¯¯
MR
1
2
3
4
8
7
6
5
VCC
VCC
WDI
SCL
SDA
8
7
6
5
1
2
3
4
¯¯¯¯¯¯
RESET
WP
¯¯¯¯¯¯
RESET
RESET
VSS
SCL
SDA
RESET
VSS
Doc. No. 3008 Rev. N
2
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
PIN FUNCTION
PIN DESCRIPTION
¯¯¯¯¯¯
(RESET CAT1025 Only)
These are open drain pins and RESET can be used
as a manual reset trigger input. By forcing a reset
condition on the pin the device will initiate and
maintain a reset condition. The RESET pin must be
connected through a pull-down resistor, and the
RESET/RESET: RESET OUTPUTs
Pin
Name
Function
No Connect
¯¯¯¯¯¯
NC
¯¯¯¯¯¯
RESET
Active Low Reset Input/Output
Ground
VSS
SDA
SCL
Serial Data/Address
Clock Input
¯¯¯¯¯¯
resistor.
RESET pin must be connected through a pull-up
Active High Reset Output
(CAT1025 only)
RESET
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
VCC
WP
Power Supply
Write Protect (CAT1025 only)
Manual Reset Input
¯¯¯
MR
SCL: SERIAL CLOCK
Serial clock input.
OPERATING TEMPERATURE RANGE
¯¯¯
MR: MANUAL RESET INPUT
Industrial
-40ºC to 85ºC
Manual Reset input is a debounced input that can be
connected to an external source for Manual Reset.
Pulling the MR input low will generate a Reset
Extended -40ºC to 125ºC
¯¯¯
condition. Reset outputs are active while MR input is
¯¯¯
low and for the reset timeout period after MR returns
to high. The input has an internal pull up resistor.
WP (CAT1025 Only): WRITE PROTECT INPUT
When WP input is tied to VSS or left unconnected write
operations to the entire array are allowed. When tied
to VCC, the entire array is protected. This input has an
internal pull down resistor.
CAT10XX FAMILY OVERVIEW
Manual
Reset
Input Pin
Watchdog
Monitor
Pin
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET:
Active High
and LOW
Device
Watchdog
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
SDA
SDA
WDI
2k
2k
2k
2k
2k
2k
2k
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
WDI
ꢁ
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 3008 Rev. N
CAT1024, CAT1025
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
–55 to +125
–65 to +150
–2.0 to VCC + 2.0
–2.0 to 7.0
1.0
Units
ºC
ºC
V
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
VCC with Respect to Ground
V
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current(3)
W
300
ºC
mA
100
D.C. OPERATING CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol Parameter
Test Conditions
VIN = GND to Vcc
VIN = GND to Vcc
Min
-2
Typ
Max
10
Units
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
-10
10
µA
fSCL = 400kHz
VCC = 5.5V
ICC1
ICC2
ISB
Power Supply Current (Write)
3
1
mA
mA
µA
fSCL = 400kHz
Power Supply Current (Read)
Standby Current
VCC = 5.5V
Vcc = 5.5V,
VIN = GND or Vcc
40
(4)
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.3 x Vcc
Vcc + 0.5
V
V
(4)
0.7 x Vcc
I
V
OL = 3mA
CC = 2.7V
VOL
VOH
0.4
V
V
V
¯¯¯¯¯¯
(SDA, RESET)
Output High Voltage
(RESET)
IOH = -0.4mA
Vcc - 0.75
4.50
V
CC = 2.7V
CAT102x-45
(VCC = 5.0V)
4.75
4.50
3.15
3.00
2.70
CAT102x-42
(VCC = 5.0V)
4.25
CAT102x-30
(VCC = 3.3V)
VTH
Reset Threshold
3.00
CAT102x-28
(VCC = 3.3V)
2.85
CAT102x-25
(VCC = 3.0V)
2.55
VRVALID
Reset Output Valid VCC Voltage
Reset Threshold Hysteresis
1.00
15
V
(5)
VRT
mV
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) VIL min and VIH max are reference values only and are not tested.
(5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
Doc. No. 3008 Rev. N
4
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol Test
Test Conditions
VOUT = 0V
Max
8
Units
pF
(1)
COUT
Output Capacitance
Input Capacitance
(1)
CIN
VIN = 0V
6
pF
AC CHARACTERISTICS
CC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
V
Memory Read & Write Cycle(2)
Symbol Parameter
Min
Max
400
100
Units
kHz
ns
fSCL
tSP
tLOW
tHIGH
Clock Frequency
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
1.3
0.6
µs
Clock High Period
µs
(1)
tR
SDA and SCL Rise Time
300
300
ns
(1)
tF
SDA and SCL Fall Time
ns
tHD; STA
tSU; STA
tHD; DAT
tSU; DAT
tSU; STO
tAA
Start Condition Hold Time
0.6
0.6
0
µs
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
µs
ns
Data Input Setup Time
100
0.6
ns
Stop Condition Setup Time
SCL Low to Data Out Valid
Data Out Hold Time
µs
900
5
ns
tDH
50
ns
(1)
tBUF
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
1.3
µs
(3)
tWC
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 3008 Rev. N
CAT1024, CAT1025
RESET CIRCUIT AC CHARACTERISTICS
Symbol
tPURST
tRDP
Parameter
Test Conditions
Note 2
Min
Typ
Max
270
5
Units
ms
µs
Power-Up Reset Timeout
VTH to RESET Output Delay
VCC Glitch Reject Pulse Width
130
200
Note 3
tGLITCH
Note 4, 5
Note 1
30
ns
MR Glitch Manual Reset Glitch Immunity
100
ns
tMRW
tMRD
MR Pulse Width
Note 1
5
µs
MR Input to RESET Output Delay
Note 1
1
µs
POWER-UP TIMING (5), (6)
Symbol
tPUR
Parameter
Test Conditions
Min
Typ
Max
270
270
Units
ms
Power-Up to Read Operation
Power-Up to Write Operation
tPUW
ms
AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
0.2VCC to 0.8VCC
10ns
0.3VCC, 0.7VCC
0.5VCC
Current Source: IOL = 3mA; CL = 100pF
RELIABILITY CHARACTERISTICS
Symbol Parameter
Reference Test Method
Min
Max
Units
(5)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
Cycles/Byte
Years
(5)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(5)
VZAP
2000
Volts
(5)(7)
ILTH
100
mA
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data
(5) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(6) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
(7) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1V to VCC + 1V.
Doc. No. 3008 Rev. N
6
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
DEVICE OPERATION
Reset Controller Description
generate a reset condition. The input has an internal
pull up resistor.
The CAT1024/25 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open
drain RESET outputs.
¯¯¯
Reset remains asserted while MR is low and for the
¯¯¯
Reset Timeout period after MR input has gone high.
¯¯¯
Glitches shorter than 100ns on MR input will not ge-
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
nerate a reset pulse. No external debouncing circuits
are required. Manual reset operation using MR input
¯¯¯
driving the outputs for approximately 200ms (tPURST
)
is shown in Figure 2.
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this
point the reset outputs will be pulled up or down by
their respective pull up/down resistors.
Hardware Data Protection
The CAT1024/25 supervisors have been designed to
solve many of the data corruption issues that have long
been associated with serial EEPROMs. Data corruption
occurs when incorrect data is stored in a memory
location which is assumed to hold correct data.
During power-down, the RESET outputs will be active
¯¯¯¯¯¯
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designed to ignore the fast negative going VCC transi-
ent pulses (glitches).
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM
are aborted and no new communications are allowed.
In this condition an internal write cycle to the memory
can not be started, but an in progress internal non-
volatile memory write cycle can not be aborted. An
internal write cycle initiated before the Reset condition
can be successfully finished if there is enough time
(5ms) before VCC reaches the minimum value of 2V.
Reset output timing is shown in Figure 1.
Manual Reset Operation
¯¯¯¯¯¯
The RESET pin can operate as reset output and
manual reset input. The input is edge triggered; that
¯¯¯¯¯¯
is, the RESET input will initiate a reset timeout after
detecting a high to low transition.
¯¯¯¯¯¯
When RESET I/O is driven to the active state, the
200ms timer will begin to time the reset interval. If
external reset is shorter than 200ms, Reset outputs
will remain active at least 200ms.
In addition, the CAT1025 includes a Write Protection
Input which when tied to VCC will disable any write
operations to the device.
The CAT1024/25 also have a separate manual reset
¯¯¯
input. Driving the MR input low by connecting a
¯¯¯
pushbutton (normally open) from MR pin to GND will
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 3008 Rev. N
CAT1024, CAT1025
Figure 1. RESET Output Timing
tGLITCH
VTH
V
RVALID
tRPD
tPURST
VCC
tRPD
tPURST
RESET
RESET
Figure 2: ¯M¯R¯ Operation and Timing
t
MRW
MR
t
t
MRD
PURST
RESET
RESET
Doc. No. 3008 Rev. N
8
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
SDA when SCL is HIGH. The CAT1024/25 monitors
the SDA and SCL lines and will not respond until this
condition is met.
EMBEDDED EEPROM OPERATION
The CAT1024 and CAT1025 feature a 2-kbit embedded
serial EEPROM that supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. Both the Master device
and Slave device can operate as either transmitter
or receiver, but the Master device controls which mode
is activated.
STOP CONDITION
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
programmable in metal and the default is 1010.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
After the Master sends a START condition and the
slave address byte, the CAT1024/25 monitors the bus
and responds with an acknowledge (on the SDA line)
when its address matches the transmitted slave
address. The CAT1024/25 then perform a Read or
START CONDITION
¯¯
Write operation depending on the R/W bit.
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
Figure 3. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 3008 Rev. N
CAT1024, CAT1025
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
¯¯
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknow-
ledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The CAT1024/25 acknowledges once more and the
Master generates the STOP condition. At this time, the
device begins an internal programming cycle to non-
volatile memory. While the cycle is in progress,
the device will not respond to any request from the
Master device.
The CAT1024/25 responds with an acknowledge
after receiving a START condition and its slave
address. If the device has been selected along with
a write operation, it responds with an acknowledge
after receiving each 8-bit byte.
When the CAT1024/25 begins a READ mode it
transmits 8 bits of data, releases the SDA line and
monitors the line for an acknowledge. Once it
receives this acknowledge, the CAT1024/25 will
continue to transmit data. If no acknowledge is sent
by the Master, the device terminates data transmis–
sion and waits for a STOP condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7: Slave Address Bits
Default Configuration
1
0
1
0
0
0
0
R/W
Doc. No. 3008 Rev. N
10
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
Page Write
The CAT1024/25 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of
terminating after the initial byte is transmitted, the
Master is allowed to send up to 15 additional bytes.
After each byte has been transmitted, the CAT1024/25
will respond with an acknowledge and internally
increment the lower order address bits by one. The
high order bits remain unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1024/25 in a single write cycle.
Figure 8. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 9: Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 3008 Rev. N
CAT1024, CAT1025
Acknowledge Polling
READ OPERATIONS
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1024/25 initiates the
internal write cycle. ACK polling can be initiated
immediately. This involves issuing the start condition
followed by the slave address for a write operation. If
the device is still busy with the write operation, no
ACK will be returned. If a write operation has
completed, an ACK will be returned and the host can
then proceed with the next read or write operation.
The READ operation for the CAT1024/25 is initiated in the
same manner as the write operation with one exception,
¯¯
the R/W bit is set to one. Three different READ operations
are possible: Immediate/Current Address READ,
Selective/Random READ and Sequential READ.
WRITE PROTECTION PIN (WP)
The Write Protection feature (CAT1025 only) allows
the user to protect against inadvertent memory array
programming. If the WP pin is tied to VCC, the entire
memory array is protected and becomes read only.
The CAT1025 will accept both slave and byte addre-
sses, but the memory location accessed is protected
from programming by the device’s failure to send an
acknowledge after the first byte of data is received.
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVIT Y:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. 3008 Rev. N
12
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
Immediate/Current Address Read
Sequential Read
The CAT1024 and CAT1025 address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ
or WRITE access was to address N, the READ
immediately following would access data from
address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid
data. After the CAT1024/1025 receives its slave
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1024 and CAT1025 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1024 and CAT1025 will continue to
output an 8-bit byte for each acknowledge, thus sending
the STOP condition.
¯¯
address information (with the R/W bit set to one), it
The data being transmitted from the CAT1024 and
CAT1025 is sent sequentially with the data from
address N followed by data from address N + 1. The
READ operation address counter increments all of the
CAT1024 and CAT1025 address bits so that the entire
memory array can be read during one operation.
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge, but will generate a STOP condition.
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1024 and CAT1025 acknowledges, the Master
device sends the START condition and the slave
¯¯
address again, this time with the R/W bit set to one.
The CAT1024 and CAT1025 then responds with its
acknowledge and sends the 8-bit byte requested.
The master device does not send an acknowledge
but will generate a STOP condition.
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 3008 Rev. N
CAT1024, CAT1025
PACKAGE OUTLINES
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
4.57
0.38
3.05
0.36
1.14
0.21
9.02
7.62
6.09
3.81
0.56
1.77
0.35
10.16
8.25
7.11
0.46
0.26
b2
c
D
E
7.87
6.35
E1
e
2.54 BSC
eB
L
7.87
2.92
9.65
3.81
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
Doc. No. 3008 Rev. N
14
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
8-LEAD 150 MIL SOIC (W)
E1
E
h x 45
D
C
A
q1
e
A1
L
b
SYMBOL
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
q1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MS-012 dimensions.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. 3008 Rev. N
CAT1024, CAT1025
8-LEAD TSSOP (V)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
q1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
0.90
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
q1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC Standard MO-153
Doc. No. 3008 Rev. N
16
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
8-LEAD MSOP (Z)
E1
E
e
e
e
D
GAUGE
PLANE
A2
A
L2
θ
L
b
A1
L1
SYMBOL
MIN
NOM
MAX
1.1
A
A1
A2
b
0.05
0.75
0.28
0.10
0.85
0.33
0.15
0.95
0.38
c
D
2.90
4.80
2.90
3.00
4.90
3.00
3.10
5.00
3.10
E
E1
e
0.65 BSC
0.45
L
0.35
0º
0.55
6º
For current Tape and Reel information, download the PDF
file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
L1
L2
Ө
Notes:
(1) All dimensions are in millimeters.
(2) This part is compliant with JEDEC Specification MO-187 Variations AA.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
17
Doc. No. 3008 Rev. N
CAT1024, CAT1025
TDFN 3 x 3 PACKAGE (ZD4)
3
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimentions in mm. Angels in degrees.
(2) Complies to JEDEC MO-229 / WEEC.
(3) Coplanarity shall not exceed 0.10mm.
(4) Warpage shall not exceed 0.10mm.
(5) Package lenght / package width are considered as special characteristic(s).
Doc. No. 3008 Rev. N
18
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1024, CAT1025
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
1024
W
I
-30
–
G
T3
Temperature Range
Tape & Reel
Company ID
T: Tape & Reel
2: 2000/Reel (only TDFN)
3: 3000/Reel
I = Industrial (-40ºC to 85ºC)
Product
Number
1024: 2K
1025: 2K
Package
L: PDIP
Reset Threshold Voltage
-45: 4.50V – 4.75V
-42: 4.25V – 4.50V
-30: 3.00V – 3.15V
-28: 2.85V – 3.00V
-25: 2.55V – 2.70V
W: SOIC
Y: TSSOP
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Z: MSOP
ZD4: TDFN 3x3mm (5)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is Matte-Tin.
(3) The device used in the above example is a CAT1024WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15V, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
(5) TDFN not available in NiPdAu (–G) version.
Ordering Part Number – CAT1024xx
Ordering Part Number – CAT1025xx
CAT1024LI-45
CAT1024LI-42
CAT1024LI-30
CAT1024LI-28
CAT1024LI-25
CAT1024WI-45
CAT1024WI-42
CAT1024WI-30
CAT1024WI-28
CAT1024WI-25
CAT1024YI-45
CAT1024YI-42
CAT1024YI-30
CAT1024YI-28
CAT1024YI-25
CAT1024ZI-45
CAT1024ZI-42
CAT1024ZI-30
CAT1024ZI-28
CAT1024ZI-25
CAT1024ZD4I-45
CAT1024ZD4I-42
CAT1024ZD4I-30
CAT1024ZD4I-28
CAT1024ZD4I-25
CAT1025LI-45
CAT1025LI-42
CAT1025LI-30
CAT1025LI-28
CAT1025LI-25
CAT1025WI-45
CAT1025WI-42
CAT1025WI-30
CAT1025WI-28
CAT1025WI-25
CAT1025YI-45
CAT1025YI-42
CAT1025YI-30
CAT1025YI-28
CAT1025YI-25
CAT1025ZI-45
CAT1025ZI-42
CAT1025ZI-30
CAT1025ZI-28
CAT1025ZI-25
CAT1025ZD4I-45
CAT1025ZD4I-42
CAT1025ZD4I-30
CAT1025ZD4I-28
CAT1025ZD4I-25
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
19
Doc. No. 3008 Rev. N
REVISION HISTORY
Date
Rev. Reason
11/07/2003
I
Eliminated Automotive temperature range
Eliminated data sheet designation
Updated Reel Ordering Information
4/12/2004
J
Changed SOIC package designators
Eliminated 8-pad TDFN (3x4.9mm) package
Added package outlines
11/01/2004
11/04/2004
K
L
Update Pin Configuration
Update Feature
Update Description
Update DC Operating Characteristic
Update AC Characteristics
11/11/2004
02/02/2007
M
N
Update Example of Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include ech of the following:
Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR
THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY
ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where
personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: 3008
Revision:
N
Issue date:
02/02/07
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