CAT1026ZD4I-42T2 [CATALYST]
Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM; 双电压监控电路，带有I²C串行2K位CMOS EEPROM
| 型号： | CAT1026ZD4I-42T2 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM |
| 文件： | 总20页 (文件大小：314K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT1026, CAT1027
Dual Voltage Supervisory Circuits with
I2C Serial 2k-bit CMOS EEPROM
supply monitor and reset circuit protects memory and
FEATURES
systems controllers during power up/down and
against brownout conditions. If power supply voltages
are out of tolerance reset signals become active
preventing the system microcontroller, ASIC, or
peripherals from operating.
ꢀ Precision VCC Power Supply Voltage Monitor
— 5V, 3.3V and 3V systems
— Five threshold voltage options
ꢀ Additional voltage monitoring
— Externally adjustable down to 1.25V
ꢀ Watchdog timer (CAT1027 only)
ꢀ Active High or Low Reset
The CAT1026 features two open drain reset outputs:
¯¯¯¯¯¯
one (RESET) drives high and the other (RESET)
drives low whenever VCC falls below the threshold.
Reset outputs become inactive typically 200 ms after
the supply voltage exceeds the reset threshold value.
With both active high and low reset signals, interface
to microcontrollers and other ICs is simple. CAT1027
— Valid reset guaranteed at VCC = 1V
ꢀ 400kHz I2C Bus
ꢀ 2.7V to 5.5V Operation
¯¯¯¯¯¯
¯¯¯¯¯¯
has only a RESET output. In addition, the RESET pin
can be used as an input for push-button manual reset
capability.
ꢀ Low power CMOS technology
ꢀ 16-Byte Page Write Buffer
ꢀ Built-in inadvertent write protection
ꢀ 1,000,000 Program/Erase cycles
ꢀ Manual Reset capability
The CAT1026 and CAT1027 provide an auxiliary
voltage sensor input, VSENSE, which is used to monitor
a second system supply. The auxiliary high impe-
dance comparator drives the open drain output, VLOW
,
ꢀ 100 year data retention
whenever the sense voltage is below 1.25V threshold.
ꢀ Industrial and extended temperature ranges
The CAT1027 is designed with a 1.6 second
watchdog timer circuit that resets a system to a known
state if software or a hardware glitch halts or “hangs”
the system. The CAT1027 features a watchdog timer
interrupt input, WDI.
ꢀ 8-pin DIP, SOIC, TSSOP, MSOP or TDFN
(3 x 3mm foot-print) packages
— TDFN max height is 0.8mm
For Ordering Information details, see page 19.
The on-chip 2k-bit EEPROM memory features a 16-byte
page. In addition, hardware data protection is provided
by a VCC sense circuit that prevents writes to memory
whenever VCC falls below the reset threshold or until VCC
reaches the reset threshold during power up.
DESCRIPTION
The CAT1026 and CAT1027 are complete memory
and supervisory solutions for microcontroller-based
systems. A 2k-bit serial EEPROM memory and a
system power supervisor with brown-out protection
are integrated together in low power CMOS techno–
logy. Memory interface is via a 400kHz I2C bus.
Available packages include 8-pin DIP and surface
mount, 8-pin SO, 8-pin TSSOP, 8-pin TDFN and 8-pin
MSOP packages. The TDFN package thickness is
0.8mm maximum. TDFN footprint is 3 x 3mm.
The CAT1026 and CAT1027 provide a precision VCC
sense circuit with five reset threshold voltage options
that support 5V, 3.3V and 3V systems. The power
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 3010 Rev. L
CAT1026, CAT1027
BLOCK DIAGRAM
RESET THRESHOLD OPTION
EXTERNAL LOAD
SENSEAMPS
SHIFT REGISTERS
D
Part Dash
Number
Minimum
Threshold
Maximum
Threshold
OUT
ACK
V
CC
WORDADDRESS
BUFFERS
COLUMN
DECODERS
-45
-42
-30
-28
-25
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
V
SS
START/STOP
LOGIC
SDA
2kbit
EEPROM
XDEC
CONTROL
LOGIC
DATA IN STORAGE
V
CC Monitor
HIGHVOLTAGE/
TIMING CONTROL
V
CC
STATE COUNTERS
SCL
SLAVE
ADDRESS
COMPARATORS
+
-
RESET
Controller
WDI
(CAT1027)
V
REF
AuxiliaryVoltage Monitor
RESET
(CAT1026)
RESET
V
+
-
SENSE
V
LOW
V
REF
PIN CONFIGURATION
DIP Package (L)
(Bottom View)
SOIC Package (W)
TSSOP Package (Y)
MSOP Package (Z)
TDFN Package: 3mm x 3mm
0.8mm maximum height - (ZD4)
VCC
RESET
SCL
8
7
6
5
1
2
3
4
VLOW
VLOW
1
2
3
4
8
7
6
5
VCC
¯¯¯¯¯¯
RESET
¯¯¯¯¯¯
RESET
RESET
SCL
CAT1026
CAT1027
CAT1026
CAT1027
VSENSE
VSS
VSENSE
VSS
SDA
SDA
VLOW
1
2
3
4
8
7
6
5
VCC
VCC
WDI
SCL
SDA
8
7
6
5
1
2
3
4
VLOW
¯¯¯¯¯¯
RESET
WDI
SCL
SDA
¯¯¯¯¯¯
RESET
VSENSE
VSS
VSENSE
VSS
Doc. No. 3010 Rev. L
2
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1026, CAT1027
PIN FUNCTION
PIN DESCRIPTION
¯¯¯¯¯¯
(RESET CAT1026 Only)
These are open drain pins and RESET can be used
as a manual reset trigger input. By forcing a reset
condition on the pin the device will initiate and
maintain a reset condition. The RESET pin must be
connected through a pull-down resistor, and the
RESET/RESET: RESET OUTPUTs
Pin
Name
¯¯¯¯¯¯
RESET
Function
Active Low Reset Input/Output
¯¯¯¯¯¯
VSS
SDA
SCL
Ground
Serial Data/Address
Clock Input
¯¯¯¯¯¯
resistor.
RESET pin must be connected through a pull-up
Active High Reset Output
(CAT1026 only)
RESET
SDA: SERIAL DATA ADDRESS
VCC
VSENSE
VLOW
Power Supply
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA
pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
Auxiliary Voltage Monitor Input
Auxiliary Voltage Monitor Output
Watchdog Timer Interrupt
(CAT1027 only)
WDI
SCL: SERIAL CLOCK
Serial clock input.
OPERATING TEMPERATURE RANGE
VSENSE: AUXILIARY VOLTAGE MONITOR INPUT
The VSENSE input is a second voltage monitor which is
compared against CAT1026 and CAT1027 internal
reference voltage of 1.25V typically. Whenever the
input voltage is lower than 1.25V, the open drain VLOW
output will be driven low. An external resistor divider is
used to set the voltage level to be sensed. Connect
VSENSE to VCC if unused.
Industrial
-40ºC to 85ºC
Extended -40ºC to 125ºC
VLOW: AUXILIARY VOLTAGE MONITOR OUTPUT
This open drain output goes low when VSENSE is less
than 1.25V and goes high when VSENSE exceeds the
reference voltage.
WDI (CAT1027 Only): WATCHDOG TIMER INTERRUPT
Watchdog Timer Interrupt Input is used to reset the
watchdog timer. If a transition from high to low or low
to high does not occur every 1.6 seconds, the RESET
outputs will be driven active.
CAT10XX FAMILY OVERVIEW
Manual
Reset
Input Pin
Watchdog
Monitor
Pin
Write
Protection
Pin
Independent
Auxiliary
Voltage Sense
RESET:
Active High
and LOW
Device
Watchdog
EEPROM
CAT1021
CAT1022
CAT1023
CAT1024
CAT1025
CAT1026
CAT1027
SDA
SDA
WDI
2k
2k
2k
2k
2k
2k
2k
ꢁ ꢁ
ꢁ
ꢁ
ꢁ
ꢁ
ꢁ ꢁ
ꢁ ꢁ
ꢁ ꢁ
ꢁ
ꢁ
ꢁ ꢁ
WDI
ꢁ
ꢁ
For supervisory circuits with embedded 16k EEPROM, please refer to the CAT1161, CAT1162 and CAT1163
data sheets.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. 3010 Rev. L
CAT1026, CAT1027
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
–55 to +125
–65 to +150
–2.0 to VCC + 2.0
–2.0 to 7.0
1.0
Units
ºC
ºC
V
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
VCC with Respect to Ground
V
Package Power Dissipation Capability (TA = 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current(3)
W
300
ºC
mA
100
D.C. OPERATING CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions unless otherwise specified.
Symbol Parameter
Test Conditions
VIN = GND to Vcc
VIN = GND to Vcc
Min
-2
Typ
Max
10
Units
µA
ILI
Input Leakage Current
ILO
Output Leakage Current
-10
10
µA
Power Supply Current
(Write)
f
SCL = 400kHz
ICC1
ICC2
ISB
3
1
mA
mA
µA
VCC = 5.5V
Power Supply Current
(Read)
fSCL = 400kHz
VCC = 5.5V
CAT1026
CAT1027
50
60
Vcc = 5.5V,
VIN = GND or Vcc
Standby Current
(4)
VIL
VIH
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.5
0.3 x Vcc
V
V
(4)
0.7 x Vcc
Vcc + 0.5
IOL = 3mA
VOL
VOH
0.4
V
¯¯¯¯¯¯
(SDA, RESET)
VCC = 2.7V
Output High Voltage
(RESET)
IOH = -0.4mA
Vcc - 0.75
V
V
VCC = 2.7V
CAT102x-45 (VCC = 5.0V)
CAT102x-42 (VCC = 5.0V)
CAT102x-30 (VCC = 3.3V)
CAT102x-28 (VCC = 3.3V)
CAT102x-25 (VCC = 3.0V)
4.50
4.25
3.00
2.85
2.55
4.75
4.50
3.15
3.00
2.70
VTH
Reset Threshold
Reset Output Valid VCC
Voltage
VRVALID
1.00
15
V
(5)
VRT
Reset Threshold Hysteresis
mV
VS
Auxiliary Voltage Monitor
Threshold
VREF
1.2
1.25
1.3
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) VIL min and VIH max are reference values only and are not tested.
(5) This parameter is tested initially and after a design or process change that affects the parameter. Not 100% tested.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
4
Doc. No. 3010 Rev. L
CAT1026, CAT1027
CAPACITANCE
TA = 25ºC, f = 1.0MHz, VCC = 5V
Symbol Test
Test Conditions
VOUT = 0V
Max
8
Units
pF
(1)
COUT
Output Capacitance
Input Capacitance
(1)
CIN
VIN = 0V
6
pF
AC CHARACTERISTICS
VCC = 2.7V to 5.5V and over the recommended temperature conditions, unless otherwise specified.
Memory Read & Write Cycle(2)
Symbol Parameter
fSCL Clock Frequency
tSP
tLOW
tHIGH
Min
Max
400
100
Units
kHz
ns
Input Filter Spike Suppression (SDA, SCL)
Clock Low Period
1.3
0.6
µs
Clock High Period
µs
(1)
tR
SDA and SCL Rise Time
300
300
ns
(1)
tF
SDA and SCL Fall Time
ns
tHD; STA
tSU; STA
tHD; DAT
tSU; DAT
tSU; STO
tAA
Start Condition Hold Time
0.6
0.6
0
µs
Start Condition Setup Time (for a Repeated Start)
Data Input Hold Time
µs
ns
Data Input Setup Time
100
0.6
ns
Stop Condition Setup Time
µs
SCL Low to Data Out Valid
900
5
ns
tDH
Data Out Hold Time
50
ns
(1)
tBUF
Time the Bus must be Free Before a New Transmission Can Start
Write Cycle Time (Byte or Page)
1.3
µs
(3)
tWC
ms
Notes:
(1) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(2) Test Conditions according to “AC Test Conditions” table.
(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. 3010 Rev. L
CAT1026, CAT1027
VOLTAGE MONITOR AND RESET CIRCUIT AC CHARACTERISTICS
Symbol
tPURST
tRDP
Parameter
Test Conditions
Note 2
Min
Typ
Max
270
5
Units
ms
µs
Reset Timeout
130
200
VTH to RESET Output Delay
VCC Glitch Reject Pulse Width
Watchdod Timeout
VSENSE to VLOW Delay
Note 3
tGLITCH
tWD
Note 4, 5
Note 1
30
2.1
5
ns
1.0
1.6
s
tRPD2
Note 5
µs
POWER-UP TIMING (6), (7)
Symbol
tPUR
Parameter
Test Conditions
Min
Typ
Max
270
270
Units
ms
Power-Up to Read Operation
Power-Up to Write Operation
tPUW
ms
AC TEST CONDITIONS
Parameter
Test Conditions
Input Pulse Voltages
Input Rise and Fall Times
Input Reference Voltages
Output Reference Voltages
Output Load
0.2VCC to 0.8VCC
10ns
0.3VCC, 0.7VCC
0.5VCC
Current Source: IOL = 3mA; CL = 100pF
RELIABILITY CHARACTERISTICS
Symbol Parameter
Reference Test Method
Min
Max
Units
(6)
NEND
Endurance
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
1,000,000
100
Cycles/Byte
Years
(6)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(6)
VZAP
2000
Volts
(6)(8)
ILTH
100
mA
Notes:
(1) Test Conditions according to “AC Test Conditions” table.
(2) Power-up, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(3) Power-Down, Input Reference Voltage VCC = VTH, Reset Output Reference Voltage and Load according to “AC Test Conditions” Table
(4) VCC Glitch Reference Voltage = VTHmin; Based on characterization data
5) 0 < VSENSE - VCC, VLOW Output Reference Voltage and Load according to “AC Test Conditions” Table.
(6) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.
(7) tPUR and tPUW are the delays required from the time VCC is stable until the specified memory operation can be initiated.
(8) Latch-up protection is provided for stresses up to 100mA on input and output pins from -1 V to VCC + 1 V.
Doc. No. 3010 Rev. L
6
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1026, CAT1027
DEVICE OPERATION
Reset Controller Description
output to generate a reset condition when either of the
supplies is invalid. In other applications, VLOW signal
can be used to interrupt the system controller for an
impending power failure notification.
The CAT1026 and CAT1027 precision RESET
controllers ensure correct system operation during
brownout and power up/down conditions. They are
configured with open drain RESET outputs.
Data Protection
During power-up, the RESET outputs remain active
until VCC reaches the VTH threshold and will continue
The CAT1026 and CAT1027 devices have been
designed to solve many of the data corruption issues
that have long been associated with serial EEPROMs.
Data corruption occurs when incorrect data is stored
in a memory location which is assumed to hold correct
data.
driving the outputs for approximately 200ms (tPURST
)
after reaching VTH. After the tPURST timeout interval, the
device will cease to drive the reset outputs. At this
point the reset outputs will be pulled up or down by
their respective pull up/down resistors.
Whenever the device is in a Reset condition, the
embedded EEPROM is disabled for all operations,
including write operations. If the Reset output(s) are
active, in progress communications to the EEPROM
are aborted and no new communications are allowed.
In this condition an internal write cycle to the memory
can not be started, but an in progress internal non-
volatile memory write cycle can not be aborted. An
internal write cycle initiated before the Reset condition
can be successfully finished if there is enough time
(5ms) before VCC reaches the minimum value of 2 V.
During power-down, the RESET outputs will be active
¯¯¯¯¯¯
when VCC falls below VTH. The RESET output will be
valid so long as VCC is >1.0V (VRVALID). The device is
designed to ignore the fast negative going VCC transi-
ent pulses (glitches).
Reset output timing is shown in Figure 1.
Manual Reset Capability
¯¯¯¯¯¯
The RESET pin can operate as reset output and
manual reset input. The input is edge triggered; that
¯¯¯¯¯¯
In addition, to avoid data corruption due to the loss of
power supply voltage during the memory internal write
operation, the system controller should monitor the
unregulated DC power. Using the second voltage
sensor, VSENSE, to monitor an unregulated power
supply, the CAT1026 and CAT1027 signals an impen-
ding power failure by setting VLOW low.
is, the RESET input will initiate a reset timeout after
detecting a high to low transition.
¯¯¯¯¯¯
When RESET I/O is driven to the active state, the
200ms timer will begin to time the reset interval. If
external reset is shorter than 200ms, Reset outputs
will remain active at least 200ms.
Monitoring Two Voltages
Watchdog Timer
The CAT1026 and CAT1027 feature a second voltage
sensor, VSENSE, which drives the open drain VLOW
output low whenever the input voltage is below 1.25V.
The auxiliary voltage monitor timing is shown in
Figure 2.
The Watchdog Timer provides an independent protec-
tion for microcontrollers. During a system failure, the
CAT1027 device will provide a reset signal after a
time-out interval of 1.6 seconds for a lack of activity.
CAT1027 is designed with the Watchdog timer feature
on the WDI pin. If WDI does not toggle within 1.6
second intervals, the reset condition will be generated
on reset output. The watchdog timer is cleared by any
transition on monitored line.
By using an external resistor divider the sense
circuitry can be set to monitor a second supply in the
system. The circuit shown in Figure 3 provides an
externally adjustable threshold voltage, VTH_ADJ to
monitor the auxiliary voltage. The low leakage current
at VSENSE allows the use of large value resistors, to
reduce the system power consumption. The VLOW
output can be externally connected to the RESET
As long as reset signal is asserted, the watchdog
timer will not count and will stay cleared.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. 3010 Rev. L
CAT1026, CAT1027
Figure 1. RESET Output Timing
tGLITCH
VTH
V
RVALID
tRPD
tPURST
VCC
tRPD
tPURST
RESET
RESET
Figure 2: Auxiliary Voltage Monitor Timing
V
REF
V
SENSE
t
t
t
t
RPD2
RPD2
RPD2
RPD2
V
LOW
Figure 3: Auxiliary Voltage Monitor
V
CC
V
AUX
CAT1026/27
Externally adjustable
Power Fail
Interrupt
threshold
V
LOW
R
1
V
TH-ADJ
V
SENSE
R
2
R
R
2
R
1 +
R
2
+
1
V
= V
×
= 1.25V ×
TH-ADJ
REF
R
R
2
2
Doc. No. 3010 Rev. L
8
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1026, CAT1027
SDA when SCL is HIGH. The CAT1026 and CAT1027
monitor the SDA and SCL lines and will not respond
until this condition is met.
EMBEDDED EEPROM OPERATION
The CAT1026 and CAT1027 feature a 2-kbit embedded
serial EEPROM that supports the I2C Bus data
transmission protocol. This Inter-Integrated Circuit Bus
protocol defines any device that sends data to the bus to
be a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. Both the Master device
and Slave device can operate as either transmitter
or receiver, but the Master device controls which mode
is activated.
STOP CONDITION
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must
end with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a
START condition. The Master sends the address of
the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are
programmable in metal and the default is 1010.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bit is set to 1, a Read operation is selected, and when
set to 0, a Write operation is selected.
(1) Data transfer may be initiated only when the bus
is not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any
changes in the data line while the clock line is
high will be interpreted as a START or STOP
condition.
After the Master sends a START condition and the
slave address byte, the CAT1026 and CAT1027
monitor the bus and responds with an acknowledge
(on the SDA line) when its address matches the
transmitted slave address. The CAT1026 and
CAT1027 then perform a Read or Write operation
START CONDITION
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
¯¯
depending on the R/W bit.
Figure 3. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 4. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. 3010 Rev. L
CAT1026, CAT1027
ACKNOWLEDGE
WRITE OPERATIONS
After a successful data transfer, each receiving
device is required to generate an acknowledge. The
acknowledging device pulls down the SDA line
during the ninth clock cycle, signaling that it received
the 8 bits of data.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
¯¯
the Slave generates an acknowledge, the Master sends
a 8-bit address that is to be written into the address
pointers of the device. After receiving another acknow-
ledge from the Slave, the Master device transmits the
data to be written into the addressed memory location.
The CAT1026 and CAT1027 acknowledge once more
and the Master generates the STOP condition. At this
time, the device begins an internal programming cycle
to non-volatile memory. While the cycle is in progress,
the device will not respond to any request from the
Master device.
The CAT1026 and CAT1027 respond with an
acknowledge after receiving a START condition and
its slave address. If the device has been selected
along with a write operation, it responds with an
acknowledge after receiving each 8-bit byte.
When the CAT1026 and CAT1027 begin a READ
mode it transmits 8 bits of data, releases the SDA
line and monitors the line for an acknowledge. Once
it receives this acknowledge, the CAT1026 and
CAT1027 will continue to transmit data. If no
acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
Figure 5. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 6. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 7: Slave Address Bits
Default Configuration
1
0
1
0
0
0
0
R/W
Doc. No. 3010 Rev. L
10
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1026, CAT1027
Page Write
The CAT1026 and CAT1027 write up to 16 bytes of
data in a single write cycle, using the Page Write
operation. The page write operation is initiated in the
same manner as the byte write operation, however
instead of terminating after the initial byte is
transmitted, the Master is allowed to send up to 15
additional bytes. After each byte has been transmitted,
the CAT1026 and CAT1027 will respond with an
acknowledge and internally increment the lower order
address bits by one. The high order bits remain
unchanged.
If the Master transmits more than 16 bytes before
sending the STOP condition, the address counter
‘wraps around,’ and previously transmitted data will be
overwritten.
When all 16 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT1026 and CAT1027 in a single write cycle.
Figure 8. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 9: Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. 3010 Rev. L
CAT1026, CAT1027
Acknowledge Polling
READ OPERATIONS
Disabling of the inputs can be used to take
advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the
host’s write opration, the CAT1026 and CAT1027
initiates the internal write cycle. ACK polling can be
initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the device is still busy with the write
operation, no ACK will be returned. If a write
operation has completed, an ACK will be returned
and the host can then proceed with the next read or
write operation.
The READ operation for the CAT1026 and CAT1027 is
initiated in the same manner as the write operation with
¯¯
one exception, the R/W bit is set to one. Three different
READ operations are possible: Immediate/Current
Address READ, Selective/Random READ and
Sequential READ.
Figure 10. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVIT Y:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. 3010 Rev. L
12
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1026, CAT1027
Immediate/Current Address Read
Sequential Read
The CAT1026 and CAT1027 address counter
contains the address of the last byte accessed,
incremented by one. In other words, if the last READ
or WRITE access was to address N, the READ
immediately following would access data from
address N + 1. For N = E = 255, the counter will
wrap around to zero and continue to clock out valid
data. After the CAT1026and CAT1027 receive its
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT1026 and CAT1027 sends the
inital 8-bit byte requested, the Master will responds with
an acknowledge which tells the device it requires more
data. The CAT1026 and CAT1027 will continue to
output an 8-bit byte for each acknowledge, thus sending
the STOP condition.
¯¯
slave address information (with the R/W bit set to
The data being transmitted from the CAT1026 and
CAT1027 is sent sequentially with the data from
address N followed by data from address N + 1. The
READ operation address counter increments all of the
CAT1026 and CAT1027 address bits so that the entire
memory array can be read during one operation.
one), it issues an acknowledge, then transmits the
8-bit byte requested. The master device does not
send an acknowledge, but will generate a STOP
condition.
Selective/Random Read
Selective/Random READ operations allow the
Master device to select at random any memory
location for a READ operation. The Master device
first performs a ‘dummy’ write operation by sending
the START condition, slave address and byte
addresses of the location it wishes to read. After the
CAT1026 and CAT1027 acknowledges, the Master
device sends the START condition and the slave
¯¯
address again, this time with the R/W bit set to one.
The CAT1026 and CAT1027 then responds with its
acknowledge and sends the 8-bit byte requested.
The master device does not send an acknowledge
but will generate a STOP condition.
Figure 11. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Figure 12. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. 3010 Rev. L
CAT1026, CAT1027
PACKAGE OUTLINES
8-LEAD 300 MIL WIDE PLASTIC DIP (L)
E1
E
D
A2
A
L
A1
e
eB
b2
b
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
4.57
0.38
3.05
0.36
1.14
0.21
9.02
7.62
6.09
3.81
0.56
1.77
0.35
10.16
8.25
7.11
0.46
0.26
b2
c
D
E
7.87
6.35
E1
e
2.54 BSC
eB
L
7.87
2.92
9.65
3.81
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
Doc. No. 3010 Rev. L
14
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1026, CAT1027
8-LEAD 150 MIL SOIC (W)
E1
E
h x 45
D
C
A
q1
e
A1
L
b
SYMBOL
MIN
0.10
1.35
0.33
0.19
4.80
5.80
3.80
NOM
MAX
0.25
1.75
0.51
0.25
5.00
6.20
4.00
A1
A
b
C
D
E
E1
e
1.27 BSC
h
0.25
0.40
0°
0.50
1.27
8°
L
q1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MS-012 dimensions.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. 3010 Rev. L
CAT1026, CAT1027
8-LEAD TSSOP (V)
D
5
8
SEE DETAIL A
c
E
E1
E/2
GAGE PLANE
0.25
1
4
PIN #1 IDENT.
q1
L
A2
SEATING PLANE
SEE DETAIL A
A
e
A1
b
SYMBOL
MIN
NOM
0.90
MAX
A
A1
A2
b
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
0.05
0.80
0.19
0.09
2.90
6.30
4.30
c
D
3.00
6.4
E
E1
e
4.40
0.65 BSC
0.60
L
0.50
0.00
0.75
8.00
q1
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC Standard MO-153
Doc. No. 3010 Rev. L
16
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1026, CAT1027
8-LEAD MSOP (Z)
E1
E
e
e
e
D
GAUGE
PLANE
A2
A
L2
θ
L
b
A1
L1
SYMBOL
MIN
NOM
MAX
1.1
A
A1
A2
b
0.05
0.75
0.28
0.10
0.85
0.33
0.15
0.95
0.38
c
D
2.90
4.80
2.90
3.00
4.90
3.00
3.10
5.00
3.10
E
E1
e
0.65 BSC
0.45
L
0.35
0º
0.55
6º
For current Tape and Reel information, download the PDF
file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
L1
L2
Ө
Notes:
(1) All dimensions are in millimeters.
(2) This part is compliant with JEDEC Specification MO-187 Variations AA.
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
17
Doc. No. 3010 Rev. L
CAT1026, CAT1027
TDFN 3 x 3 PACKAGE (ZD4)
3
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimentions in mm. Angels in degrees.
(2) Complies to JEDEC MO-229 / WEEC.
(3) Coplanarity shall not exceed 0.10mm.
(4) Warpage shall not exceed 0.10mm.
(5) Package lenght / package width are considered as special characteristic(s).
Doc. No. 3010 Rev. L
18
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT1026, CAT1027
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
1026
W
I
-30
–
G
T3
Temperature Range
Tape & Reel
Company ID
T: Tape & Reel
2: 2000/Reel (only TDFN)
3: 3000/Reel
I = Industrial (-40ºC to 85ºC)
Product
Number
1026: 2K
1027: 2K
Package
Reset Threshold Voltage
-45: 4.50V – 4.75V
-42: 4.25V – 4.50V
-30: 3.00V – 3.15V
-28: 2.85V – 3.00V
-25: 2.55V – 2.70V
L: PDIP
W: SOIC
Y: TSSOP
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Z: MSOP
ZD4: TDFN 3x3mm (5)
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is Matte-Tin.
(3) The device used in the above example is a CAT1026WI-30-GT3 (SOIC, Industrial Temperature, 3.0 - 3.15V, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
(5) TDFN not available in NiPdAu (–G) version.
Ordering Part Number – CAT1026xx
Ordering Part Number – CAT1027xx
CAT1026LI-45
CAT1026LI-42
CAT1026LI-30
CAT1026LI-28
CAT1026LI-25
CAT1026WI-45
CAT1026WI-42
CAT1026WI-30
CAT1026WI-28
CAT1026WI-25
CAT1026YI-45
CAT1026YI-42
CAT1026YI-30
CAT1026YI-28
CAT1026YI-25
CAT1026ZI-45
CAT1026ZI-42
CAT1026ZI-30
CAT1026ZI-28
CAT1026ZI-25
CAT1026ZD4I-45
CAT1026ZD4I-42
CAT1026ZD4I-30
CAT1026ZD4I-28
CAT1026ZD4I-25
CAT1027LI-45
CAT1027LI-42
CAT1027LI-30
CAT1027LI-28
CAT1027LI-25
CAT1027WI-45
CAT1027WI-42
CAT1027WI-30
CAT1027WI-28
CAT1027WI-25
CAT1027YI-45
CAT1027YI-42
CAT1027YI-30
CAT1027YI-28
CAT1027YI-25
CAT1027ZI-45
CAT1027ZI-42
CAT1027ZI-30
CAT1027ZI-28
CAT1027ZI-25
CAT1027ZD4I-45
CAT1027ZD4I-42
CAT1027ZD4I-30
CAT1027ZD4I-28
CAT1027ZD4I-25
© 2007 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
19
Doc. No. 3010 Rev. L
REVISION HISTORY
Date
Rev. Reason
Added Green Package logo. Updated DC Operating Characteristic notes. Updated
Reliability Characteristics notes
9/25/2003
F
Eliminated Automotive temperature range. Updated Ordering Information with
“Green” package marking codes
11/07/2003
4/12/2004
11/01/2004
11/04/2004
G
H
I
Eliminated data sheet designation. Updated Reel Ordering Information
Changed SOIC package designators. Eliminated 8-pad TDFN (3 x 4.9mm) package.
Added package outlines
J
Update Pin Configuration
Update Feature
Update Description
Update DC Operating Characteristic
Update AC Characteristics
11/11/2004
02/02/2007
K
L
Update Example of Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include ech of the following:
Beyond Memory™, DPP™, EZDim™, MiniPot™, and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR
THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY
ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where
personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: 3010
Revision:
L
Issue date:
02/02/07
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明