CAT24C042J-42TE13 [CATALYST]
Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer; 监控电路，带有I2C串行E2PROM CMOS ，精密复位控制器和看门狗定时器
| 型号： | CAT24C042J-42TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer |
| 文件： | 总12页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advanced
CAT24C161/162(16K), CAT24C081/082(8K)
CAT24C041/042(4K), CAT24C021/022(2K)
2
2
Supervisory Circuits with I C Serial CMOS E PROM, Precision Reset Controller and Watchdog Timer
FEATURES
■ Active High or Low Reset Outputs
— Precision Power Supply Voltage Monitoring
— 5V, 3.3V and 3V options
■ Watchdog Timer on SDA for 24CXX1
■ Programmable Reset Threshold
2
■ 400 KHz I C Bus Compatible
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
■ 2.7 to 6 Volt Operation
■ Low Power CMOS Technology
■ 16 - Byte Page Write Buffer
■ Built-in inadvertent write protection
— VCC Lock Out
■ 8-Pin DIP or 8-Pin SOIC
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24CXXX is a single chip solution to three
popular functions of EEPROM memory, precision reset
controller and watchdog timer. The 24C161/162(16K),
24C081/082(8K),24C041/042(4K)and24C021/022(2K)
feature a I2C Serial CMOS EEPROM. Catalyst's ad-
vanced CMOS technology substantially reduces device
power requirements. The 24CXXX features a 16-byte
pageandisavailablein8-pinDIPor8-pinSOICpackages.
The reset function of the 24CXXX protects the system
duringbrownoutandpowerup/downconditions. During
system failure the watchdog timer feature protects the
microcontroller with a reset signal. 24CXXX features
active low reset on pin 2 and active high reset on pin 7.
24CXX1 features watchdog timer on the SDA line.
24CXX2 does not feature the watchdog timer function.
BLOCK DIAGRAM
PIN CONFIGURATION
EXTERNAL LOAD
24CXX1/XX2*
SENSE AMPS
SHIFT REGISTERS
D
OUT
V
DC
RESET
WP
CC
ACK
RESET
V
V
CC
SCL
SDA
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SS
V
SS
START/STOP
LOGIC
*All products offered in P and J packages
SDA
WP
PIN FUNCTIONS
E2PROM
XDEC
Pin Name
Function
CONTROL
LOGIC
SDA
Serial Data/Address
Reset I/O
RESET/RESET
DATA IN STORAGE
SCL
Vcc
DC
Clock Input
Power Supply
Do Not Connect
Ground
HIGH VOLTAGE/
TIMING CONTROL
RESET Controller
High
STATE COUNTERS
SCL
VSS
WP
Precision
SLAVE
ADDRESS
COMPARATORS
Only for
24C161
WATCHDOG
Write Protect
Vcc Monitor
24C1601 BLOCK
RESET/RESET
© 1998 by Catalyst Semiconductor, Inc.
Doc. No. 25079-00 1/98 M-1
1
Characteristics subject to change without notice
CAT24CXX1/XX2
Advanced
ABSOLUTE MAXIMUM RATINGS*
COMMENT
Temperature Under Bias....................–55°C to +125°C
Storage Temperature........................ –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
(1)
Respect to Ground
..............–2.0V to +V
+ 2.0V
CC
VCC with Respect to Ground..................–2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)1.0W.................................1.0W
Lead Soldering Temperature (10 secs)...............300°C
Output Short Circuit Current(2) ..........................100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Min.
Max. Units
Reference Test Method
(3)
NEND
Endurance
1,000,000
100
Cycles/Byte
Years
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.7V to +6.0V, unless otherwise specified.
Limits
Symbol
ICC
Parameter
Min.
Typ. Max.
Units
mA
Test Conditions
fSCL = 100 KHz
Vcc=3.3V
Power Supply Current
Standby Current
3
Isb
40
µA
50
2
µA
µA
µA
V
Vcc=5
ILI
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN=GND or VCC
VIN=GND or VCC
ILO
10
VIL
–1
VCC x 0.3
VIH
VOL
Input High Voltage
VCC x 0.7
VCC + 0.5
0.4
V
Output Low Voltage (SDA)
V
IOL = 3 mA ,VCC=3.0V
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Test
Max.
Units
Conditions
VI/O = 0V
VIN = 0V
(3)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (SCL)
8
6
pF
pF
(3)
CIN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25079-00 1/98 M-1
2
Advanced
CAT24CXX1/XX2
A.C. CHARACTERISTICS
V
=2.7V to 6.0V unless otherwise specified.
CC
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol
Parameter
VCC=2.7V - 6V
VCC=4.5V - 5.5V
Min.
Max.
100
Min.
Max.
Units
kHz
ns
FSCL
TI(1)
Clock Frequency
400
200
Noise Suppression Time
200
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
1
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
0.6
1.2
0.6
0.6
µs
µs
µs
µs
4.7
4
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
4.7
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
(1)(2)
Power-Up Timing
Symbol
Parameter
Max.
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
Units
tWR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device
does not respond to its slave address.
Doc. No. 25079-00 1/98 M-1
3
CAT24CXX1/XX2
Advanced
RESET CIRCUIT CHARACTERISTICS
Symbol
tGLITCH
VRT
Parameter
Min.
Max. Units
Glitch Reject Pulse Width
Reset Threshold Hystersis
Reset Output Low Voltage (IOLRS=1mA)
Reset Output High Voltage
100
ns
mV
V
15
VOLRS
VOHRS
0.4
Vcc-0.75
4.50
V
Reset Threshold (Vcc=5V)
(24CXXX-45)
4.75
Reset Threshold (Vcc=5V)
(24CXXX-42)
4.25
3.00
4.50
3.15
V
Reset Threshold (Vcc=3.3V)
(24CXXX-30)
VTH
Reset Threshold (Vcc=3.3V)
(24CXXX-28)
2.85
2.55
3.00
2.70
Reset Threshold (Vcc=3V)
(24CXXX-25)
t
PURST
Power-Up Reset Timeout
VTH to RESET Output Delay
RESET Output Valid
130
1
270
5
ms
µs
V
t
RPD
VRVALID
Doc. No. 25079-00 1/98 M-1
4
Advanced
CAT24CXX1/XX2
PIN DESCRIPTIONS
WP: WRITE PROTECT
VTH threshold and will continue driving the outputs for
approximately 200ms (tPURST) after reaching VTH. After
the tPURST timeout interval, the device will cease to drive
reset outputs. At this point the reset outputs will be
pulled up or down by their respective pull up/pull down
devices. During power-down, the RESET outputs will
begin driving active when VCC falls below VTH. The
RESET outputs will be valid so long as VCC is >1.0V
(VRVALID).
If the pin is tied to VCC the entire memory array becomes
WriteProtected(READonly). WhenthepinistiedtoVSS
or left floating normal read/write operations are allowed
to the device.
SCL: SERIAL CLOCK
The serial clock input clocks all data transferred into or
out of the device.
RESET/RESET: RESET I/O
The RESET pins are I/Os; therefore, the CAT24CXXX
can act as a signal conditioning circuit for an externally
applied reset. The inputs are level triggered; that is, the
RESET input in the 24CXXX will initiate a reset timeout
after detecting a high and the RESET input in the
24CXXXwillinitiatearesettimeoutafterdetectingalow.
These are open drain pins and can be used as reset
triggerinputs. Byforcingaresetconditiononthepinsthe
device will initiate and maintain a reset condition for
approximately 200ms. RESET pin must be connected
through a pull-down and RESET pin must be connected
through a pull-up device.
Watchdog Timer
SDA: SERIAL DATA/ADDRESS
The Watchdog Timer provides an independent protec-
tion for microcontrollers. During a system failure, the
CAT24CXX1willrespondwitharesetsignalafteratime-
out interval of 1.6 seconds for lack of activity. 24CXX1
isdesignedwiththeWatchdogTimerfeatureontheSDA
input. For the 24CXX1, if the microcontroller does not
toggle the SDA input pin within 1.6 seconds the Watch-
dog Timer times out. This will generate a reset condition
onresetoutputs. The WatchdogTimerisclearedbyany
transition on SDA.
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
opendrainoropencollectoroutputs. Inthe24CXX1, the
SDA line is also used as the Watchdog Timer Monitor.
DEVICE OPERATION
Reset Controller Description
The CAT24CXXX provides a precision RESET control-
ler that ensures correct system operation during brown-
out and power-up/down conditions. It is configured
with open drain RESET outputs. During power-up, the
RESET outputs remain active until VCC reaches the
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared. 24CXX2 does
not feature the Watchdog Timer function.
Figure 1. RESET Output Timing
tGLITCH
VTH
V
RVALID
VCC
tRPD
tPURST
tPURST
RESET
tRPD
RESET
Doc. No. 25079-00 1/98 M-1
5
CAT24CXX1/XX2
Advanced
Reset Threshold Voltage
Hardware Data Protection
From the factory the 24CXXX is offered in five different
variations of reset threshold voltages. They are 4.50-
4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-
2.70V. To provide added flexibility to design engineers
using this product, the 24CXXX is designed with an
additional feature of programming the reset threshold
voltage. This allows the user to change the existing
reset threshold voltage to one of the other four reset
threshold voltages. Once the reset threshold voltage is
selected it will not change even after cycling the power,
unless the user uses the programmer to change the
reset threshold voltage. However, the programming
functionisavailableonlythroughthirdpartyprogrammer
manufacturers. PleasecallCatalystforalistofprogram-
mer manufacturers who support this function.
The 24CXXX is designed with the following hardware
data protection features to provide a high degree of data
integrity.
(1) The24CXXXfeaturesaWPpin.WhenWPpin istied
high the entire memory array becomes write protected
(read only).
(2) The VCC sense provides write protection when VCC
fallsbelowtheresetthresholdvalue(VTH). TheVCC lock
out inhibits writes to the serial EEPROM whenever VCC
falls below (power down) VTH or until VCC reaches the
reset threshold (power up) VTH
.
Figure 2. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
SDA IN
BUF
t
t
DH
AA
SDA OUT
Figure 3. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 4. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 25079-00 1/98 M-1
6
Advanced
CAT24CXX1/XX2
FUNCTIONAL DESCRIPTION
STOP Condition
The CAT24CXXX supports the I2C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24CXXX
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master sends the address of the particu-
larslavedeviceitisrequesting. Thefourmostsignificant
bits of the 8-bit slave address are fixed as 1010.
The next three bits (Fig. 6) define memory addressing.
For the 24C021/022, the three bits are don't care. For
the 24C041/042, the next two bits are don't care and the
third bit is the high order address bit. For the 24C081/
082, the next bit is don't care and the successive bits
define the higher order address bits. For the 24C161/
162 the three bits define higher order bits.
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
The last bit of the slave address specifies whether a
Read or Write operation is to be performed. When this
bitissetto1, aReadoperationisselected, andwhenset
to 0, a Write operation is selected.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes in
thedatalinewhiletheclocklineishighwillbeinterpreted
as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT24CXXX monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24CXXX then performs a Read or Write operation
depending on the state of the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDAwhenSCLisHIGH. TheCAT24CXXXmonitorsthe
SDA and SCL lines and will not respond until this
condition is met.
Figure 5. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 6. Slave Address Bits
24C021/022
1
0
1
0
X
X
X
X
R/W
24C081/082
24C161/162
1
1
0
0
1
1
0
0
X
a9
a8 R/W
a8 R/W
24C041/042
a10 a9
1
0
1
0
X
a8 R/W
* 'X' Corresponds to Don't Care Bits (can be a zero or a one)
** a8, a9 and a10 correspond to the address of the memory array address word.
Doc. No. 25079-00 1/98 M-1
7
CAT24CXX1/XX2
Advanced
ACKNOWLEDGE
location. The CAT24CXXX acknowledges once more
and the Master generates the STOP condition. At this
time,thedevicebeginsaninternalprogrammingcycleto
nonvolatile memory. While the cycle is in progress, the
device will not respond to any request from the Master
device.
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24CXXX responds with an acknowledge after
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
Page Write
The 24CXXX writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted, CAT24CXXX will respond with an
acknowledge, and internally increment the lower order
address bits by one. The high order bits remain un-
changed.
When the CAT24CXXX begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24CXXX will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
terminates data transmission and waits for a STOP
condition.
WRITE OPERATIONS
If the Master transmits more than 16 bytes before
sendingtheSTOPcondition,theaddresscounter‘wraps
around’,andpreviouslytransmitteddatawillbeoverwrit-
ten.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
theSlavegeneratesanacknowledge, theMastersends
a 8-bit address that is to be written into the address
pointers of the CAT24CXXX. After receiving another
acknowledge from the Slave, the Master device trans-
mits the data to be written into the addressed memory
When all 16 bytes are received, and the STOP condi
tion has been sent by the Master, the internal program-
ming cycle begins. At this point, all received data is
written to the CAT24CXXX in a single write cycle.
Figure 7. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 8. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+15
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc. No. 25079-00 1/98 M-1
8
Advanced
CAT24CXX1/XX2
Acknowledge Polling
protected and becomes read only. The CAT24CXXX
will accept both slave and byte addresses, but the
memory location accessed is protected from program-
ming by the device's failure to send an acknowledge
after the first byte of data is received.
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host’s write operation,
CAT24CXXX initiates the internal write cycle. ACK poll-
ing can be initiated immediately. This involves issuing
the start condition followed by the slave address for a
writeoperation. IfCAT24CXXXisstillbusywiththewrite
operation, no ACK will be returned. If
CAT24CXXX has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
READ OPERATIONS
The READ operation for the CAT24CXXX is initiated in
the same manner as the write operation with one excep-
tion, that R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ,Selective/Random READandSequential READ.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
Figure 9. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
24C1601Fig.8
Doc. No. 25079-00 1/98 M-1
9
CAT24CXX1/XX2
Advanced
Immediate/Current Address Read
The CAT24CXXX’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E= 255 for
24C021/022, E=511 for 24C041/042, E=1023 for
24C081/082 and E=2047 for 24C161/162) then the
counter will ‘wrap around’ to address 0 and continue to
clock out data. After the CAT24CXXX receives its slave
address information (with the R/W bit set to one), it
issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an ac-
knowledge, but will generate a STOP condition.
doesnotsendanacknowledgebutwillgenerateaSTOP
condition.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24CXXX sends the initial 8-bit
byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24CXXX will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
Selective/Random Read
The data being transmitted from CAT24CXXX is output-
ted sequentially with data from address N followed by
data from address N+1. The READ operation address
counter increments all of the CAT24CXXX address bits
so that the entire memory array can be read during one
operation. If more than E (where E= 255 for 24C021/
022, E=511 for 24C041/042, E=1023 for 24C081/082
and E=2047 for 24C161/162) bytes are read out, the
counter will ‘wrap around’ and continue to clock out data
bytes.
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24CXXX acknowledges, the
MasterdevicesendstheSTARTconditionandtheslave
address again, this time with the R/W bit set to one.
The CAT24CXXX then responds with its acknowledge
and sends the 8-bit byte requested. The master device
Figure 10. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
24C1601Fig.9
Figure 11. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
24C1601Fig.10
Doc. No. 25079-00 1/98 M-1
10
Advanced
CAT24CXX1/XX2
Ordering Information
Prefix
Device #
Suffix
24C162
-30
CAT
J
I
TE13
Optional
Temperature Range
Product
Tape & Reel
TE13: 2000/Reel
Company ID
Blank = Commercial (0˚ to 70˚C)
I = Industrial (-40˚ to 85˚C)
A = Automotive (-40˚to +105˚C)*
Number
24C161: 16K
24C162: 16K
24C081: 8K
24C082: 8K
24C041: 4K
24C042: 4K
24C021: 2K
24C022: 2K
ResetThreshold
Voltage
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
Package
P: PDIP
J: SOIC (JEDEC)
* -40˚ to +125˚C is available upon request
Note:
2
(1) The device used in the above example is a CAT24C162JI-30TE13 (16K I C Memory, SOIC, Industrial Temperature, 3.0-3.15V Reset
Threshold Voltage, Tape and Reel)
Doc. No. 25079-00 1/98 M-1
11
CAT24CXX1/XX2
Advanced
Doc. No. 25079-00 1/98 M-1
12
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