CAT24C043JI-25TE13 [CATALYST]

Power Supply Management Circuit, Adjustable, 1 Channel, CMOS, PDSO8, SOIC-8;


型号：	CAT24C043JI-25TE13
厂家：	CATALYST SEMICONDUCTOR
描述：	Power Supply Management Circuit, Adjustable, 1 Channel, CMOS, PDSO8, SOIC-8 光电二极管
文件：	总12页 (文件大小：73K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Advanced Information

CAT24C163(16K), CAT24C083(8K)

CAT24C043(4K), CAT24C023(2K)

Supervisory Circuits with I C Serial CMOS E PROM, Precision Reset Controller and Watchdog Timer

FEATURES

■ Active High or Low Reset Outputs

— Precision Power Supply Voltage Monitoring

— 5V, 3.3V and 3V options

■ Watchdog Timer Input (WDI)

■ Programmable Reset Threshold

■ 400 KHz I C Bus Compatible

■ 1,000,000 Program/Erase Cycles

■ 100 Year Data Retention

■ 2.7 to 6 Volt Operation

■ Low Power CMOS Technology

■ 16 - Byte Page Write Buffer

■ Built-in inadvertent write protection

— V_CCLock Out

■ 8-Pin DIP or 8-Pin SOIC

■ Commercial, Industrial and Automotive

Temperature Ranges

DESCRIPTION

The CAT24CXX3 is a single chip solution to three

popular functions of EEPROM memory, precision reset

controller and watchdog timer. The 24C163(16K),

24C083(8K), 24C043(4K) and 24C023(2K) feature aI²C

Serial CMOS EEPROM Catalyst advanced CMOS tech-

nologysubstantiallyreducesdevicepowerrequirements.

The 24CXX3 features a 16-byte page and is available in

8-pin DIP or 8-pin SOIC packages.

The reset function of the 24CXX3 protects the system

duringbrownoutandpowerup/downconditions. During

system failure the watchdog timer feature protects the

microcontroller with a reset signal. 24CXX3 features

active low reset on pin 2 and active high reset on pin 7.

24CXX3 features watchdog timer on the WDI input pin

(pin 1).

PIN CONFIGURATION

BLOCK DIAGRAM

EXTERNAL LOAD

24CXX3

SENSE AMPS

SHIFT REGISTERS

OUT

WDI

RESET

ACK

RESET

SCL

WORD ADDRESS

BUFFERS

COLUMN

DECODERS

SDA

START/STOP

*All products offered in P and J packages

SDA

LOGIC

PIN FUNCTIONS

E²PROM

XDEC

Pin Name

Function

CONTROL

LOGIC

SDA

Serial Data/Address

Reset I/O

RESET/RESET

SCL

DATA IN STORAGE

Clock Input

Vcc

Power Supply

Ground

HIGH VOLTAGE/

TIMING CONTROL

V_SS

RESET Controller

High

WDI

Watchdog Timer Input

Write Protect

STATE COUNTERS

SCL

Precision

SLAVE

ADDRESS

COMPARATORS

WATCHDOG

Vcc Monitor

24C1601 BLOCK

WDI RESET/RESET

Doc. No. 25080-00 8/99 M-1

Characteristics subject to change without notice

CAT24C163/083/043/023

Advanced Information

ABSOLUTE MAXIMUM RATINGS*

COMMENT

Temperature Under Bias....................–55°C to +125°C

Storage Temperature........................ –65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation

of the device at these or any other conditions outside of

those listed in the operational sections of this specifica-

tion is not implied. Exposure to any absolute maximum

rating for extended periods may affect device perfor-

mance and reliability.

Voltage on Any Pin with

(1)

Respect to Ground

..............–2.0V to +V

+ 2.0V

V_CCwith Respect to Ground..................–2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)1.0W.................................1.0W

Lead Soldering Temperature (10 secs)...............300°C

Output Short Circuit Current⁽²⁾..........................100mA

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min.

Max. Units

Reference Test Method

(3)

N_END

Endurance

1,000,000

100

Cycles/Byte

Years

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(3)

T_DR

Data Retention

ESD Susceptibility

Latch-up

(3)

V_ZAP

2000

Volts

(3)(4)

I_LTH

100

D.C. OPERATING CHARACTERISTICS

= +2.7V to +6.0V, unless otherwise specified.

Limits

Symbol

I_CC

Parameter

Min.

Typ. Max.

Units

Test Conditions

f_SCL= 100 KHz

Vcc=3.3V

Power Supply Current

Standby Current

Isb

µA

Vcc=5

ILI

Input Leakage Current

Output Leakage Current

Input Low Voltage

V_IN=G_NDor V_CC

ILO

V_IL

–1

V_CCx 0.3

V_IH

V_OL

Input High Voltage

V_CCx 0.7

V_CC+ 0.5

0.4

Output Low Voltage (SDA)

I_OL= 3 mA, V_CC= 3.0V

CAPACITANCE T = 25°C, f = 1.0 MHz, V

= 5V

Symbol

Test

Max.

Units

Conditions

V_I/O= 0V

V_IN= 0V

(3)

C_I/O

Input/Output Capacitance (SDA)

Input Capacitance (SCL)

(3)

C_IN

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Advanced Information

A.C. CHARACTERISTICS

=2.7V to 6.0V unless otherwise specified.

Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

Symbol

Parameter

V_CC=2.7V - 6V

V_CC=4.5V - 5.5V

Min.

Max.

100

Min.

Max.

400

Units

kHz

F_SCL

T_I⁽¹⁾

Clock Frequency

Noise Suppression Time

200

Constant at SCL, SDA Inputs

t_AA

SCL Low to SDA Data Out

and ACK Out

3.5

µs

(1)

t_BUF

Time the Bus Must be Free Before

a New Transmission Can Start

4.7

1.2

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

0.6

1.2

0.6

µs

4.7

t_HIGH

Clock High Period

t_SU:STA

Start Condition Setup Time

4.7

(for a Repeated Start Condition)

t_HD:DAT

t_SU:DAT

Data In Hold Time

µs

Data In Setup Time

(1)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

Data Out Hold Time

0.3

(1)

t_F

300

t_SU:STO

t_DH

0.6

100

(1)(2)

Power-Up Timing

Symbol

Parameter

Max.

Units

t_PUR

t_PUW

Power-up to Read Operation

Power-up to Write Operation

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

Write Cycle Limits

Symbol

Parameter

Min.

Typ.

Max

Units

t_WR

Write Cycle Time

The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase

cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device

does not respond to its slave address.

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Advanced Information

RESET CIRCUIT CHARACTERISTICS

Symbol

t_GLITCH

V_RT

Parameter

Min.

Max. Units

Glitch Reject Pulse Width

Reset Threshold Hystersis

Reset Output Low Voltage (I_OLRS=1mA)

Reset Output High Voltage

100

V_OLRS

V_OHRS

0.4

Vcc-0.75

4.50

Reset Threshold (Vcc=5V)

(24CXXX-45)

4.75

Reset Threshold (Vcc=5V)

(24CXXX-42)

4.25

3.00

4.50

3.15

Reset Threshold (Vcc=3.3V)

(24CXXX-30)

V_TH

Reset Threshold (Vcc=3.3V)

(24CXXX-28)

2.85

2.55

3.00

2.70

Reset Threshold (Vcc=3V)

(24CXXX-25)

PURST

Power-Up Reset Timeout

V_THto RESET Output Delay

RESET Output Valid

130

270

µs

RPD

V_RVALID

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Advanced Information

PIN DESCRIPTIONS

with open drain RESET outputs. During power-up, the

RESET outputs remain active until V_CCreaches the

V_THthreshold and will continue driving the outputs for

approximately 200ms (t_PURST) after reaching V_TH.After

the t_PURSTtimeout interval, the device will cease to drive

resetoutputs.Atthispointtheresetoutputswillbepulled

upordownbytheirrespectivepullup/pulldowndevices.

During power-down, the RESET outputs will begin driv-

ing active when V_CCfalls below V_TH.The RESET

outputs will be valid so long as V_CCis >1.0V (V_RVALID).

WDI: WATCHDOG INPUT

If there is no transition on the WDI for more than 1.6

seconds, the watchdog timer times out.

WP: WRITE PROTECT

If the pin is tied to V_CCthe entire memory array becomes

WriteProtected(READonly). WhenthepinistiedtoV_SS

or left floating normal read/write operations are allowed

to the device.

The RESET pins are I/Os; therefore, the CAT24CXXX

can act as a signal conditioning circuit for an externally

applied reset. The inputs are edge triggered; that is, the

RESET input in the 24CXXX will initiate a reset timeout

after detecting a low to high transition and the RESET

input in the 24CXXX will initiate a reset timeout after

detecting a high to low transition.

SCL: SERIAL CLOCK

The serial clock input clocks all data transferred into or

out of the device.

RESET/RESET: RESET I/O

These are open drain pins and can be used as reset

triggerinputs. Byforcingaresetconditiononthepinsthe

device will initiate and maintain a reset condition for

approximately 200ms. RESET pin must be connected

through a pull-down and RESET pin must be connected

through a pull-up device.

Watchdog Timer

The Watchdog Timer provides an independent protec-

tion for microcontrollers. During a system failure, the

CAT24CXXX will respond with a reset signal after a

time-outintervalof1.6secondsforalackofactivity. The

24CXX3 is designed with a WDI input pin for the Watch-

dogTimerfunction. Forthe24CXX3,ifthemicrocontroller

doesnot toggletheWDIinputpinwithin1.6seconds,the

Watchdog Timer times out. This will generate a reset

condition on reset outputs. The Watchdog Timer is

cleared by any transition on WDI.

SDA: SERIAL DATA/ADDRESS

The bidirectional serial data/address pin is used to

transfer all data into and out of the device. The SDA pin

is an open drain output and can be wire-ORed with other

open drain or open collector outputs.

DEVICE OPERATION

Reset Controller Description

As long as the reset signal is asserted, the Watchdog

Timer will not count and will stay cleared.

The CAT24CXXX provides a precision RESET control-

ler that ensures correct system operation during brown-

out and power up/down conditions. It is configured

Figure 1. RESET Output Timing

GLITCH

RVALID

RPD

PURST

RESET

RPD

RESET

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Hardware Data Protection

Advanced Information

Reset Threshold Voltage

From the factory the 24CXXX is offered in five different

variations of reset threshold voltages. They are 4.50-

4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-

2.70V. To provide added flexibility to design engineers

using this product, the 24CXXX is designed with an

additional feature of programming the reset threshold

voltage. This allows the user to change the existing

reset threshold voltage to one of the other four reset

threshold voltages. Once the reset threshold voltage is

selected it will not change even after cycling the power,

unless the user uses the programmer to change the

reset threshold voltage. However, the programming

functionisavailableonlythroughthirdpartyprogrammer

manufacturers. PleasecallCatalystforalistofprogram-

mer manufacturers who support this function.

The 24CXXX is designed with the following hardware

data protection features to provide a high degree of data

integrity.

(1) The24CXXXfeaturesaWPpin.WhenWPpin istied

high the entire memory array becomes write protected

(read only).

(2) The V_CCsense provides write protection when V_CC

fallsbelowtheresetthresholdvalue(V_TH). TheV_CClock

out inhibits writes to the serial EEPROM whenever V_CC

falls below (power down) V_THor until V_CCreaches the

reset threshold (power up) V_TH

Figure 2. Bus Timing

HIGH

LOW

SCL

HD:DAT

SU:STA

HD:STA

SU:DAT

SU:STO

SDA IN

BUF

SDA OUT

Figure 3. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 4. Start/Stop Timing

SDA

SCL

START BIT

STOP BIT

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Advanced Information

FUNCTIONAL DESCRIPTION

STOP Condition

The CAT24CXXX supports the I²C Bus data transmis-

sion protocol. This Inter-Integrated Circuit Bus protocol

defines any device that sends data to the bus to be a

transmitter and any device receiving data to be a re-

ceiver. The transfer is controlled by the Master device

which generates the serial clock and all START and

STOP conditions for bus access. The CAT24CXXX

operates as a Slave device. Both the Master device and

Slave device can operate as either transmitter or re-

ceiver, but the Master device controls which mode is

activated.

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master sends the address of the particu-

larslavedeviceitisrequesting. Thefourmostsignificant

bits of the 8-bit slave address are fixed as 1010.

The next three bits (Fig. 6) define memory addressing.

For the 24C023, the three bits are don't care. For the

24C043, the next two bits are don't care and the third bit

is the high order address bit. For the 24C083, the next

bit is don't care and the successive bits define the higher

order address bits. For the 24C163 the three bits define

higher order bits.

I²C BUS PROTOCOL

The features of the I²C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus is

not busy.

The last bit of the slave address specifies whether a

Read or Write operation is to be performed. When this

bitissetto1, aReadoperationisselected, andwhenset

to 0, a Write operation is selected.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes in

thedatalinewhiletheclocklineishighwillbeinterpreted

as a START or STOP condition.

After the Master sends a START condition and the slave

address byte, the CAT24CXXX monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT24CXXX then performs a Read or Write operation

depending on the state of the R/W bit.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDAwhenSCLisHIGH. TheCAT24CXXXmonitorsthe

SDA and SCL lines and will not respond until this

condition is met.

Figure 5. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 6. Slave Address Bits

24C023

R/W

24C083

24C163

a8 R/W

24C043

a10 a9

a8 R/W

* 'X' Corresponds to Don't Care Bits (can be a zero or a one)

** a8, a9 and a10 correspond to the address of the memory array address word.

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

ACKNOWLEDGE

Advanced Information

location. The CAT24CXXX acknowledges once more

and the Master generates the STOP condition. At this

time,thedevicebeginsaninternalprogrammingcycleto

nonvolatile memory. While the cycle is in progress, the

device will not respond to any request from the Master

device.

Afterasuccessfuldatatransfer, eachreceivingdeviceis

requiredtogenerateanacknowledge.TheAcknowledg-

ing device pulls down the SDA line during the ninth clock

cycle, signaling that it received the 8 bits of data.

The CAT24CXXX responds with an acknowledge after

receivingaSTARTconditionanditsslaveaddress. Ifthe

device has been selected along with a write operation,

it responds with an acknowledge after receiving each 8-

bit byte.

Page Write

The 24CXXX writes up to 16 bytes of data in a single

write cycle, using the Page Write operation. The page

write operation is initiated in the same manner as the

byte write operation, however instead of terminating

after the initial byte is transmitted, the Master is allowed

to send up to 15 additional bytes. After each byte has

been transmitted, CAT24CXXX will respond with an

acknowledge, and internally increment the lower order

address bits by one. The high order bits remain un-

changed.

When the CAT24CXXX begins a READ mode it trans-

mits 8 bits of data, releases the SDA line, and monitors

the line for an acknowledge. Once it receives this ac-

knowledge, the CAT24CXXX will continue to transmit

data. IfnoacknowledgeissentbytheMaster, thedevice

terminates data transmission and waits for a STOP

condition.

WRITE OPERATIONS

If the Master transmits more than 16 bytes before

sendingtheSTOPcondition,theaddresscounter‘wraps

around’,andpreviouslytransmitteddatawillbeoverwrit-

ten.

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information

(with the R/W bit set to zero) to the Slave device. After

theSlavegeneratesanacknowledge, theMastersends

a 8-bit address that is to be written into the address

pointers of the CAT24CXXX. After receiving another

acknowledge from the Slave, the Master device trans-

mits the data to be written into the addressed memory

When all 16 bytes are received, and the STOP condi

tion has been sent by the Master, the internal program-

ming cycle begins. At this point, all received data is

written to the CAT24CXXX in a single write cycle.

Figure 7. Byte Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS

DATA

SDA LINE

Figure 8. Page Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

DATA n

DATA n+1

DATA n+15

SDA LINE

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Advanced Information

Acknowledge Polling

protected and becomes read only. The CAT24CXXX

will accept both slave and byte addresses, but the

memory location accessed is protected from program-

ming by the device's failure to send an acknowledge

after the first byte of data is received.

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write operation,

CAT24CXXX initiates the internal write cycle. ACK poll-

ing can be initiated immediately. This involves issuing

the start condition followed by the slave address for a

writeoperation. IfCAT24CXXXisstillbusywiththewrite

operation, no ACK will be returned. If

CAT24CXXX has completed the write operation, an

ACK will be returned and the host can then proceed with

the next read or write operation.

READ OPERATIONS

The READ operation for the CAT24CXXX is initiated in

the same manner as the write operation with one excep-

tion, that R/W bit is set to one. Three different READ

operations are possible: Immediate/Current Address

READ,Selective/Random READandSequential READ.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is tied to V_CC, the entire memory array is

Figure 9. Immediate Address Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

SDA LINE

DATA

SCL

SDA

8TH BIT

DATA OUT

NO ACK

STOP

24C1601Fig.8

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Advanced Information

Immediate/Current Address Read

The CAT24CXXX’s address counter contains the ad-

dress of the last byte accessed, incremented by one. In

other words, if the last READ or WRITE access was to

address N, the READ immediately following would ac-

cess data from address N+1. If N=E (where E= 255 for

24C023, E=511 for 24C043, E=1023 for 24C083 and

E=2047 for 24C163) then the counter will ‘wrap around’

to address 0 and continue to clock out data. After the

CAT24CXXX receives its slave address information

(with the R/W bit set to one), it issues an acknowledge,

then transmits the 8-bit byte requested. The master

device does not send an acknowledge, but will generate

a STOP condition.

doesnotsendanacknowledgebutwillgenerateaSTOP

condition.

Sequential Read

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations. After the CAT24CXXX sends the initial 8-bit

byte requested, the Master will respond with an ac

knowledge which tells the device it requires more data.

TheCAT24CXXXwillcontinuetooutputan8-bitbyte for

each acknowledge sent by the Master. The operation

will terminate when the Master fails to respond with an

acknowledge, thus sending the STOP condition.

Selective/Random Read

The data being transmitted from CAT24CXXX is output-

ted sequentially with data from address N followed by

data from address N+1. The READ operation address

counter increments all of the CAT24CXXX address bits

so that the entire memory array can be read during one

operation. If more than E (where E= 255 for 24C023,

E=511 for 24C043, E=1023 for 24C083 and E=2047 for

24C163) bytes are read out, the counter will ‘wrap

around’ and continue to clock out data bytes.

Selective/Random READ operations allow the Master

device to select at random any memory location for a

READ operation. The Master device first performs a

‘dummy’ write operation by sending the START condi-

tion, slave address and byte addresses of the location it

wishes to read. After CAT24CXXX acknowledges, the

MasterdevicesendstheSTARTconditionandtheslave

address again, this time with the R/W bit set to one.

The CAT24CXXX then responds with its acknowledge

and sends the 8-bit byte requested. The master device

Figure 10. Selective Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE

ADDRESS (n)

SLAVE

ADDRESS

SDA LINE

DATA n

24C1601Fig.9

Figure 11. Sequential Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

24C1601Fig.10

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Advanced Information

Ordering Information

Prefix

Device #

24C163

Suffix

-30

CAT

TE13

Optional

Company ID

Temperature Range

Product

Tape & Reel

TE13: 2000/Reel

Blank = Commercial (0˚ to 70˚C)

I = Industrial (-40˚ to 85˚C)

A = Automotive (-40˚to +105˚C)

Number

24C163: 16K

24C083: 8K

24C043: 4K

24C023: 2K

ResetThreshold

Package

Voltage

P: PDIP

45: 4.5-4.75V

42: 4.25-4.5V

30: 3.0-3.15V

28: 2.85-3.0V

25: 2.55-2.7V

J: SOIC (JEDEC)

* -40˚ to +125˚C is available upon request

Note:

(1) The device used in the above example is a CAT24C163JI-30TE13 (16K I C Memory, SOIC, Industrial Temperature, 3.0-3.15V Reset

Threshold Voltage, Tape and Reel)

Doc. No. 25080-00 8/99 M-1

CAT24C163/083/043/023

Advanced Information

Doc. No. 25080-00 8/99 M-1

CAT24C043JI-25TE13 [CATALYST]

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