CAT24C208WI-1.8TE13 [CATALYST]
EEPROM;
| 型号： | CAT24C208WI-1.8TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 |
| 文件： | 总14页 (文件大小：124K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
E
CAT24C208
8K (1K x 8) -Bit Dual Port Serial EEPROM for VESA Plug and Play Applications
in LCD Projectors and Monitors
TM
FEATURES
■ 400 kHz I2C bus compatible*
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Complies with VESA E-EDID, E-DDC, DI-EXT
and M1 specifications
■ 8-pin DIP, SOIC, TSSOP or MSOP packages
- Green package option
■ 1.8 to 5.5 volt operation
■ Industrial and extended temperature ranges
■ Low power CMOS technology
■ 16-byte page write buffer
■ Self-timed write cycle with auto-clear
DESCRIPTION
Using Catalyst's advanced CMOS technology which
substantially reduces device power requirements, the
CAT24C208 can be powered from either of two
independent VCC inputs.
The CAT24C208 is an 8k-bit Dual Port Serial CMOS
EEPROM internally organized as 1k words of 8 bits
each. The CAT24C208 features a 16-byte page write
buffer and can be accessed from either of two separate
I2C compatible ports, DSP (SDA, SCL) and DDC (SDA,
SCL) which conform to the VESA E-EDID EEPROM
Standard.
The CAT24C208 operates over the full industrial and
extended temperature range and is available in
miniature 8-pin DIP, SOIC, TSSOP and MSOP
packages.
Arbitration between the two interface ports is automatic
and allows the appearance of simultaneous access to
the memory from both interfaces.
BLOCK DIAGRAM
DSP VCC
DDC VCC
ARBITRATION
LOGIC
D
E
C
O
D
E
R
S
D
E
C
O
D
E
R
S
1K X 8
MEMORY
ARRAY
DDC
CONTROL
LOGIC
DISPLAY
CONTROL
LOGIC
DSP SCL
DSP SDA
DDC SCL
DDC SDA
CONFIGURATION
REGISTER
DDC SEL
VSS
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1044, Rev. B
1
CAT24C208
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DSP V
DDC V
CC
DSP V
DDC V
CC
CC
CC
DSP SCL
EDID SEL
DDC SCL
DDC SDA
DSP SCL
DSP SDA
EDID SEL
DDC SCL
DDC SDA
DSP SDA
V
V
SS
SS
MSOP Package (R, Z)
TSSOP Package (U, Y)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
DSP V
DDC V
CC
DSP V
CC
DSP SCL
DDC V
CC
CC
DSP SCL
DSP SDA
EDID SEL
DDC SCL
DDC SDA
EDID SEL
DDC SCL
DDC SDA
DSP SDA
V
V
SS
SS
PIN DESCRIPTION
Pin Number
Pin Name
Function
1
DSP VCC
Device power from display controller
The CAT24C208 DSP serial clock input pin is used to clock all data
transfers into or out of the device DSP SDA pin.
2
3
DSP SCL
DSP SDA
DSP Serial Data/Address. The bidirectional DSP serial
data/address pin is used to transfer data into and out of the device
from a display controller. The DSP SDA pin is an open drain output
and can be wire-OR'ed with other open drain or open collector
outputs.
4
5
VSS
Device ground.
DDC Serial Data/Address. The bidirectional DDC serial
data/address pin is used to transfer data into and out of the device
from a DDC host. The DDC SDA pin is an open drain output and
can be wire-OR'ed with other open drain or open collector outputs.
DDC SDA
The CAT24C208 DDC serial clock input pin is used to clock all data
transfers into or out of the device DDC SDA pin.
6
DDC SCL
EDID select. The CAT24C208 EDID select input selects the active
bank of memory to be accessed via the DDC SDA/SCL interface as
set in the configuration register.
7
8
EDID SEL
DDC VCC
Device power when powered from a DDC host.
Doc. No. 1044, Rev. B
2
CAT24C208
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ............ -2.0V to +VCC + 2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
Endurance
MIL-STD-883, Test Method 1033 1,000,000
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
4000
100
(3)
VZAP
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Symbol
ICC
Parameter
Test Conditions
fSCL = 100 KHz
Min
Typ
Max
Units
mA
µA
Power Supply Current
Standby Current (VCC = 5.0V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
3
0
(5)
ISB
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
ILI
10
10
µA
ILO
VIL
VIH
µA
–1
VCC x 0.3
VCC + 0.5
V
V
Input High Voltage
VCC x 0.7
0.05
VHYS
VOL1
Input Hysteresis
V
Output Low Voltage (VCC = 3.0V)
Output Low Voltage (VCC = 1.8V)
IOL = 3 mA
0.4
0.5
100
V
VOL2
IOL = 1.5 mA
V
VCCL1
Leakage DSP to VCC
DDC to VCC
µA
VCCL2
Leakage DDC VCC to DSP VCC
100
µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Standby Current (I ) = 0µA (<900nA).
SB
Doc. No. 1044, Rev. B
3
CAT24C208
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Parameter
Conditions
VI/O = 0V
VIN = 0V
Min
Typ
Max
Units
pF
(1)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (VCLK, SCL)
8
6
(1)
CIN
pF
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
A.C. CHARACTERISTICS
V
CC
= +1.8V to +6.0V, unless otherwise specified.
Read & Write Cycle Limits
Symbol
Parameter
1.8V-5.5V
2.5V-5.5V
Min
Max
Min
Max
Units
FSCL
TI(1)
Clock Frequency
100
200
400
200
kHz
ns
Noise Suppression Time
Constant at SCL, SDA Inputs
tAA
SCL Low to SDA Data Out
and ACK Out
3.5
1
µs
µs
(1)
tBUF
Time the Bus Must be Free Before
a New Transmission Can Start
4.7
1.2
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
4.7
4
0.6
1.2
0.6
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
tSU:STA
Start Condition Setup Time
4.7
(for a Repeated Start Condition)
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
0.3
(1)
tF
300
300
tSU:STO
tDH
4
0.6
100
100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
(1)(2)
Power-Up Timing
Symbol
tPUR
Parameter
Min
Typ
Max
Units
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
tPUW
Doc. No. 1044, Rev. B
4
CAT24C208
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
5
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
FUNCTIONAL DESCRIPTION
The CAT24C208 has a total memory space of 1K bytes
which is accessible from either of two I2C interface ports,
(DSP_SDA and DSP_SCL) or (DDC_SDA and
DDC_SCL).
Each bank of memory can be used to store an E-EDID
data structure. However, only one bank can be read
through the DDC port at a time. The active bank of
memory (that is, the bank that appears at address A0h
on the DDC port) is controlled through the configuration
register at 62h and the EDID_SEL pin.
The entire memory appears as contiguous memory
space from the perspective of the display interface
(DSP_SDA and DSP_SCL).
No write operations are possible from the DDC interface
unless the DDC Write Enable bit is set (WE = 1) in the
device configuration register at device address 62h.
A configuration register at addresses 62/63h is used to
configure the operation and memory map of the device
as seen from the DDC interface, (DDC_SDA and
DDC_SCL).
The device automatically arbitrates between the two
interfaces to allow the appearance of simultaneous
access to the memory from both interfaces.
Read and write operations can be performed on any
location within the memory space from the display
interface regardless of the state of the EDID SEL pin or
the activity on the DDC interface. From the DDC
interface,thememoryspaceappearsaseitheronelarge
1K byte bank of memory or as two 500 byte banks of
memory.
In a typical E-EDID application the EDID_SEL pin is
usually connected to the “Analog Cable Detect” pin of a
VESA M1 compliant, dual-mode (analog and digital)
display. In this manner, the E-EDID appearing at ad-
dress A0h on the DDC port will be either the analog or
digital E-EDID, depending on the state of the “Analog
Cable Detect” pin (pin C3 of the M1-DA connector). See
Figure 1.
Figure 1.
+5VDC
(SUPPLIED
BY DISLAY)
28
DDC +5V
47.5K
10K
8
7
6
5
1
2
3
4
C3
27
28
I2C TO PROJECTOR/MONITOR
DISPLAY CONTROLLER
E-EDID
EEPROM
TO HOST
CONTROLLER
DDC CLK
DDC DATA
FUSE, RESISTOR
OR OTHER
CURRENT LIMITING
DEVICE REQUIRED
IN ALL M1 DISPLAYS
RELAY CONTACTS SHOWN IN
DE-ENERGIZED POSITION
26
HPD
2A MAX
Doc. No. 1044, Rev. B
5
CAT24C208
I2C Bus Protocol
Acknowledge
ThefollowingdefinesthefeaturesoftheI2Cbusprotocol:
After a successful data transfer, each receiving device is
requiredtogenerateanacknowledge.Theacknowledging
devicepullsdowntherespectiveSDAlineduringtheninth
clock cycle, signaling that it received the 8 bits of data.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
The CAT24C208 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
either SDA when the respective SCL is HIGH. The
CAT24C208 monitors the SDA and SCL lines and will
not respond until this condition is met.
When the CAT24C208 is in a READ mode it transmits 8
bits of data, releases the respective SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24C208 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
Figure 2. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Doc. No. 1044, Rev. B
6
CAT24C208
256 bytes within a segment. Note that if the segment
pointer is set to 00h then the device will behave like a
standard DDC2B EEPROM.
DEVICE ADDRESSING
Both the DDC and DSP interfaces to the device are
based on the I2C bus serial interface. All memory space
operations are done at the A0/A1 DDC address pair.
Note that the least significant bit (LSB) of the DDC
address is used to determine if the data is being written
(LSB=0) or read (LSB=1). As such, all write operations
to the memory space are done at DDC address A0h and
all read operations of the memory space are done at
DDC address A1h.
The segment pointer is a volatile register unlike the
configuration register and the EEPROM used for the
main memory space. The configuration register will be
shipped in the erased (set to FFh) state.
Figure 3 shows the bit sequence of a random read from
anywhere within the memory space. The word offset
determines which of the 256 bytes within segment 00h
is being read. One can think of this sequence as a
dummy write to address A0 of the word offset followed
by a read of the data. The dummy write sets the word
offset for the read to follow.
The segment pointer is at the address 60h and is write-
only. This means that a memory access at 61h will give
undefined results. The segment pointer is a volatile
register. Thedeviceconfigurationregisterat62/63(hex)
is a non-volatile register.
Sequentialreadscanbedoneinmuchthesamemanner
by reading successive bytes after each acknowledge
without generating a stop condition. See Figure 4. The
device must automatically increment the word offset
value (8-bit value) as well as the segment pointer up to
the values permitted by the physical memory limitations
and the state of the configuration bits in the control
The segment pointer is used to expand the available
DDC address space while maintaining backward com-
patibility with older DDC interfaces such as DDC2B. For
each value of the 8-bit segment pointer one segment
(256 bytes) is available at the A0/A1 pair. The standard
DDC 8-bit address is sufficient to address each of the
Figure 3. Random Access Read (Segment 0 only)
S
S
T
A
R
T
T
A
R
T
S
T
O
P
DDC
ADDRESS
BUS ACTIVITY:
MASTER
OFFSET
ADDRESS
DDC
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
DATA n
Figure 4. Sequential Read (Segment 0 only)
S
T
A
R
T
S
T
A
R
T
S
T
O
P
DDC
ADDRESS
BUS ACTIVITY:
MASTER
OFFSET
ADDRESS
DDC
ADDRESS
DATA n+x
DATA n
DATA n+1
DATA n+2
SDA LINE
S
P
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Doc. No. 1044, Rev. B
7
CAT24C208
register (DDC interface only). Note that the device
should not acknowledge the read of the last allowable
data byte.
Arbitration logic within the device monitors activity on
DDC_SCLandDSP_SCL.WhenbothI2Cportsareidle,
DDC_SCL and DSP_SCL are both high and the
arbitration logic is inactive. When either DDC_SCL or
DSP_SCL is pulled low, initiating a read or write, the
arbitration logic pulls down the other SCL line and holds
it low, holding off activity on the other port (by stretching
the clock on that port). When the initiating SCL line has
remained high for one full second, the arbitration logic
assumes that the initiating devices is finished and
releases the other SCL line. If the non-initiating device
has been waiting for access, it can now read or write the
device.
Figure 5 shows the bit sequence for a random read from
anywhere within the allowable address space. The
device must support sequential reads beginning at any
location. The host indicates a sequential read by putting
out a clock without generating a stop condition. Just as
before the device signals the host that is has just
received the last byte of a sequential read by not
acknowledging the last byte. The host is responsible for
generating the stop condition when it does not receive
an acknowledge from a sequential read.
For this scheme to work properly, both the DDC and
DSP devices must properly implement clock stretching
as defined by the I2C specification. Additionally, it is very
important that when writing to the device that the SCL
line never remains high longer than 1 second, until the
write is complete. This prevents the other port from
having access until the device is fully written.
ARBITRATION
The device performs a simplistic arbitration between the
DDCanddisplayinterfaces.Whilethearbitrationscheme
described is not foolproof, it does prevent most errors.
The arbitration logic uses “clock stretching”, an I2C bus
term, to hold off writes from one port while the other port
is active.
Figure 5. Byte Read From Any Loction
S
T
A
R
T
S
T
A
R
T
S
T
O
P
SEGMENT
POINTER
DDC
ADDRESS
DDC
ADDRESS
BUS ACTIVITY:
MASTER
OFFSET
ADDRESS (n)
DDC
ADDRESS
SDA LINE
S
S
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Doc. No. 1044, Rev. B
8
CAT24C208
CONFIGURATION REGISTER
M
S
B
L
S
B
7
6
5
4
3
2
1
0
Register Function
X
X
X
X
WE
AB1
AB0
NB
Configuration Register
Function Description:
NB:
AB0:
Number of memory banks in DDC port memory map. 0 = 2 Banks, 1 = 1 Bank
Active Bank Control Bit 0 (See Table 1-3)
AB1:
Active Bank Control Bit 1 (See Table 1-3)
WE DDC:
Write Enable 0 = Write Disabled, 1= Write Enabled
Note: WE affects only write operations from the DDC port, not the display port. The display port always has write access.
Figure 6. Configuration Register Truth Table
EDID
Select Pin
AB1
AB0
NP
Active Bank
0
0
1
1
X
X
X
0
0
1
0
0
0
0
1
Lower Bank
Upper Bank
X
X
X
Lower Bank
1
Upper Bank
X
Lower (only) Bank
Doc. No. 1044, Rev. B
9
CAT24C208
ORDERING INFORMATION
Prefix
Device #
24C208
Suffix
CAT
J
I
-1.8
TE13
Temperature Range
Product Number
24C208: 8K
Tape & Reel
TE13: 2000/Reel
Optional
Company ID
I = Industrial (-40 to 85 C)
A = Automotive (-40 to 105 C)
E = Extended (-40 to 125 C)
Operating Voltage
Blank: 2.5V - 5.5V
1.8: 1.8V - 5.5V
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
R: MSOP
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a CAT24C208JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
PACKAGING INFORMATION
8 Lead PDIP (P, L)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
D
0.120 (3.05)
0.180 (4.57) MAX
0.150 (3.81)
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
—
0.100 (2.54)
BSC
0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
Dimension D
0.014 (0.36)
0.022 (0.56)
Pkg
8L
Min
0.355 (9.02)
Max
0.400 (10.16)
Doc. No. 1044, Rev. B
10
CAT24C208
PACKAGING INFORMATION
8 Lead 150 mil Wide SOIC (J, W)
0.149 (3.80)
0.1574 (4.00)
0.2284 (5.80)
0.2440 (6.20)
0.1890 (4.80)
0.1968 (5.00)
0.0532 (1.35)
0.0688 (1.75)
0.050 (1.27) BSC
0.0040 (0.10)
0.0098 (0.25)
0.013 (0.33)
0.020 (0.51)
0.0099 (0.25)
0.0196 (0.50)
X 45
˚
0.0075 (0.19)
0.0098 (0.25)
0˚-8˚
0.016 (0.40)
0.050 (1.27)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
3. Lead coplanarity is 0.004" (0.102mm) maximum.
Doc. No. 1044, Rev. B
11
CAT24C208
PACKAGING INFORMATION
8 Lead TSSOP (U, Y)
Notes:
1. Lead coplanarity is 0.004" (0.102mm) maximum.
Doc. No. 1044, Rev. B
12
CAT24C208
PACKAGING INFORMATION
8 Lead MSOP (R, Z)
0.38
0.28
0.0150
0.0110
0.1970
0.1890
5.00
4.80
S
0.0256 [0.65] BSC
3.10
2.90
0.1220
0.1142
0.0374
0.0295
0.95
0.75
0.0433 [1.10] MAX.
0.0059
0.0020
0.15
0.05
0.039 [0.10] MAX.
S
S
0.0150
0.0110
0.38
0.28
WITH PLATING
0.0091 0.23
0.0051 0.13
0.0050 [0.127]
0.1220
0.1142
3.10
2.90
0.0276
0.0157
0.70
0.40
0˚ - 6˚
WITH PLATING
BASE METAL
0.0118 [0.30] REF.
SECTION A - A
Doc. No. 1044, Rev. B
13
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Catalyst Semiconductor, Inc.
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Publication #: 1044
Revison:
Issue date:
Type:
B
6/24/03
Advance
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www.catalyst-semiconductor.com
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CAT24C208YE-TE13
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