CAT24C21RI [CATALYST]
128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, MSOP-8;
| 型号： | CAT24C21RI |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 128X8 I2C/2-WIRE SERIAL EEPROM, PDSO8, MSOP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Preliminary Information
E
CAT24C21
1K (128 x 8) -Bit Dual Mode Serial EEPROM for VESA™ "Plug-and-Play"
TM
FEATURES
■ 400 kHz I2C bus compatible*
■ 16-byte page write buffer
■ DDC1TM/DDC2TM interface compliant for
■ Self-timed write cycle with auto-clear
■ 1,000,000 program/erase cycles
■ 100 year data retention
monitor identification
■ 2.5 to 5.5 volt operation
■ Low power CMOS technology
■ 8-pin DIP, SOIC, TSSOP or MSOP packages
■ Industrial and extended temperature ranges
■ Write protect feature
— Entire array protected when VCLK at VIL
DESCRIPTION
input. Catalyst’s advanced CMOS technology
substantially reduces device power requirements. The
CAT24C21 features a 16-byte page write buffer. The
device operates via the I2C bus serial interface, has a
special write protection feature, and is available in 8-pin
DIP, SOIC, TSSOP and MSOP packages.
The CAT24C21 is a 1k-bit Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. The
CAT24C21 can operate in two modes compliant to the
VESA™, DDC1™ and DDC2™ standards for "Plug-
and-Play"monitors. TheTransmit-onlyModecontrolled
bytheVCLKinputandthebi-directionalModewherethe
memories content is controlled by the I2C bus, SCL
BLOCK DIAGRAM
PIN CONFIGURATION
SOIC Package (J, W)
DIP Package (P, L)
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
NC
NC
NC
V
NC
NC
NC
D
CC
V
CC
VCLK
OUT
VCLK
ACK
SCL
SCL
V
V
CC
SS
V
SDA
V
SS
SS
SDA
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
MSOP Package (R, Z)
TSSOP Package (U, Y)
START/STOP
SDA
LOGIC
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
NC
NC
NC
NC
NC
NC
V
CC
VCLK
V
CC
VCLK
SCL
SCL
EEPROM
V
XDEC
V
SDA
SS
SDA
SS
CONTROL
LOGIC
SCL
PIN FUNCTIONS
VCLK
Pin Name
Function
DATA IN STORAGE
NC
No Connect
SDA
SCL
VCLK
VCC
VSS
Serial Data/Address
HIGH VOLTAGE/
TIMING CONTROL
Serial Clock (Bidirectional Mode)
Serial Clock (Transmit only Mode)
+2.5V to +5.5V Power Supply
Ground
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
© 2003 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1032, Rev. G
1
CAT24C21
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ............ -2.0V to +VCC + 2.0V
VCC with Respect to Ground ................ -2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Max
Units
Cycles/Byte
Years
(3)
NEND
Endurance
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
V
= +2.5V to +5.5V, unless otherwise specified.
CC
Symbol
ICC
Parameter
Test Conditions
fSCL = 100 KHz
Min
Typ
Max
Units
mA
µA
µA
µA
V
Power Supply Current
3
0
(5)
ISB
Standby Current (VCC = 5.0V)
Input Leakage Current
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
ILI
10
10
ILO
VIL
VIH
Output Leakage Current
Input Low Voltage (SCL & SDA)
Input High Voltage (SCL & SDA)
Output Low Voltage (VCC = 3.0V)
Output Low Voltage (VCC = 1.8V)
Input Low Voltage (VCLK)
Input High Voltage (VCLK)
–1
VCC x 0.3
VCC + 0.5
0.4
VCC x 0.7
V
VOL1
VOL2
VIL
IOL = 3 mA
V
IOL = 1.5 mA
0.5
V
VCC x 0.2
0.8
V
VIH
2.0
V
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Parameter
Conditions
VI/O = 0V
VIN = 0V
Min
Typ
Max
Units
pF
(3)
CI/O
Input/Output Capacitance (SDA)
Input Capacitance (VCLK, SCL)
8
6
(3)
CIN
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Standby Current (I ) = 0µA (<900nA).
SB
Doc. No. 1032, Rev. G
2
CAT24C21
A.C. CHARACTERISTICS
V
CC
= +2.5V to +5.5V, unless otherwise specified.
Transmit-only Mode
2.5V to 5.5V
Typ
Symbol
Parameter
Output valid from VCLK
Units
Min
Max
TVAA
0.5
µs
µs
µs
µs
ns
TVHIGH VCLK high
0.6
1.3
TVLOW
TVHZ
VCLK low
Mode transition
Transmit-only power-up
0.5
TUPV
0
2.5V to 5.5V
Typ
Symbol
Parameter
Units
Min
Max
FSCL
TI(1)
Clock Frequency
400
200
kHz
ns
Noise Suppression Time
Constant at SCL, SDA Inputs
Read & Write Cycle Limits
SCL Low to SDA Data Out
tAA
1
µs
µs
and ACK Out
Time the Bus Must be Free Before a
New Transmission Can Start
(1)
tBUF
1.2
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
0.6
1.2
0.6
µs
µs
µs
tHIGH
Clock High Period
Start Condition Setup Time (for a
Repeated Start Condition)
tSU:STA
0.6
µs
tHD:DAT
tSU:DAT
Data In Hold Time
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
0.3
(1)
tF
300
tSU:STO
tDH
0.6
100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 1032, Rev. G
3
CAT24C21
(1)(2)
Power-Up Timing
Symbol
tPUR
Parameter
Min
Min
Typ
Typ
Max
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Write Cycle Limits
Symbol
Parameter
Max
Units
tWR
Write Cycle Time
10
ms
erase cycle. During the write cycle, the bus interface
circuits are disabled, SDA is allowed to remain high, and
the device does not respond to its slave address.
The write cycle time is the time from a valid stop condition
of a write sequence to the end of the internal program/
and output one bit of data on the SDA pin for each rising
edge of the VCLK pin. Data is transmitted in 8 bit words
with the most significant bit first followed by a 9th "don't
care" bit which will be in the high impedance state. The
CAT24C21willcontinuouslysequencethroughtheentire
memory array as long as VCLK is present and no falling
edgesonSCLarereceived.Whenthemaximumaddress
(7FH) is reached, the output will wrap around to the zero
location (00H) and continue. The bi-directional mode
clock (SCL) pin must be held high for the device to
remain in the transmit-only mode.
FUNCTIONAL DESCRIPTION
The CAT24C21 has two modes of operation: the Trans-
mit-only Mode and the Bi-directional Mode. There is a
separate 2-wire protocol to support each mode; each
having a separate clock input (SCL and VCLK) and both
modessharingacommonBi-directionaldataline(SDA).
The CAT24C21 enters the transmit-only mode upon
powerupandbeginsoutputtingdataontheSDApinwith
each clock signal on the VCLK pin. The device will
remain in the transmit-only mode until there is a valid
high to low transition on the SCL pin. The device will
switch into the bi-directional mode when there is a valid
transitionontheSCLpin. Onceinthebi-directinalmode,
the only way to return to the transmit-only mode is by
powering down the device.
Upon power-up, the CAT24C21 will output valid data
only after it has been initialized. During initialization,
data will not be available until after the first nine clocks
are sent to the device. The starting address for the
transmit-only mode can be determined during
initialization. If the SDA pin is high during the first eight
clocks, the starting address will be 7FH. If the SDA pin
Transmit-only Mode: (DDC1)
The CAT24C21 will power up in the Transmit-only mode
Figure 1. Transmit-only Mode
SCL must remain high for transmit-only mode
SCL
Bit8
(MSB)
Bit1
Don't
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit8
Bit7
SDA
VCLK
(LSB) Care
T
T
VLOW
VHIGH
Doc. No. 1032, Rev. G
4
CAT24C21
is low during the first eight clocks, the starting address
willbe00H.Duringtheninthclock,SDAwillbeinthehigh
impedance state.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
PIN DESCRIPTIONS
When in the Bi-directional mode, all inputs to the VCLK
pin are ignored, except when a logic high is required to
enable write capability.
SCL: Serial Clock
The CAT24C21 serial clock input pin is used to clock all
data transfers into or out of the device when in the
bi-directional mode.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24C21 monitors the
SDA and SCL lines and will not respond until this
condition is met.
SDA: Serial Data/Address
The CAT24C21 bi-directional serial data/address pin is
usedtotransferdataintoandoutofthedevice. TheSDA
pin is an open drain output and can be wire-ORed with
other open drain or open collector outputs.
STOP Condition
VCLK: Serial Clock
The VCLK serial clock input pin is used to clock data out
of the device when in transmit-only mode.
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
BI-DIRECTIONAL MODE (DDC2)
DEVICE ADDRESSING
ThefollowingdefinesthefeaturesoftheI2Cbusprotocol
when in the bi-directional mode:
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
(1) Data transfer may be initiated only when the bus is
not busy.
Figure 2. Device Initialization for Transmit-only Mode
SCL
SDA
SDA at high impedance for 9 clock cycles
Bit8
Bit7 Bit6 Bit5 Bit4
VCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
T
VPU
T
VAA
Figure 3. Mode Transition
Transmit-Only Mode
Bi-Directional Mode
SCL
T
VHZ
SDA
VCLK
Doc. No. 1032, Rev. G
5
CAT24C21
as 1010 for the CAT24C21 (see Fig. 8). The next three
significant bits are "don't care". The last bit of the slave
address specifies whether a Read or Write operation is
to be performed. When this bit is set to 1, a Read
operationisselected,andwhensetto0,aWriteoperation
is selected.
The CAT24C21 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation, it
responds with an acknowledge after receiving each 8-bit
byte.
When the CAT24C21 is in a READ mode it transmits 8
bits of data, releases the SDA line, and monitors the line
for an acknowledge. Once it receives this acknowledge,
the CAT24C21 will continue to transmit data. If no
acknowledgeissentbytheMaster,thedeviceterminates
data transmission and waits for a STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT24C21 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24C21 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
requiredtogenerateanacknowledge.TheAcknowledging
device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
Figure 4. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 5. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Doc. No. 1032, Rev. G
6
CAT24C21
Page Write
WRITE OPERATIONS
The CAT24C21 writes up to 16 bytes of data in a single
write cycle, using the Page Write operation. The Page
Write operation is initiated in the same manner as the
Byte Write operation, however instead of terminating
after the initial word is transmitted, the Master is allowed
tosenduptofifteenadditionalbytes. Aftereachbytehas
been transmitted the CAT24C21 will respond with an
acknowledge, and internally increment the low order
address bits by one. The high order bits remain
unchanged.
VCLK must be held high in order to program the device.
This applies to byte write and page write operation.
Once the device is in its self-timed program cycle,
VCLK can go low and not affect programming.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24C21. After receiving another
acknowledgefromtheSlave,theMasterdevicetransmits
the data byte to be written into the addressed memory
location. The CAT24C21 acknowledge once more and
the Master generates the STOP condition, at which time
the device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
If the Master transmits more than sixteen bytes prior to
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
Once all sixteen bytes are received and the STOP
condition has been sent by the Master, the internal
programmingcyclebegins.Atthispointallreceiveddata
is written to the CAT24C21 in a single write cycle.
Figure 6. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Figure 7. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 8. Slave Address Bits
CAT24C21
1
0
1
0
X
X
X
R/W
Doc. No. 1032, Rev. G
7
CAT24C21
Acknowledge Polling
READ OPERATIONS
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT24C21 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24C21 is still busy with
the write operation, no ACK will be returned. If the
CAT24C21 has completed the write operation, an ACK
will be returned and the host can then proceed with the
TheREADoperationfortheCAT24C21isinitiatedinthe
same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24C21’s address counter contains the address
of the last byte accessed, incremented by one. In other
words,ifthelastREADorWRITEaccesswastoaddress
N, the READ immediately following would access data
from address N+1. If N=127, then the counter will 'wrap
around' to address 0 and continue to clock out data.
next read or write operation.
WRITE PROTECTION
When the VCLK pin is connected to GND and the
CAT24C21 is in the bi-directional mode, the entire
memory is protected and becomes "read only".
Figure 9. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
*
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
Figure 10. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16
* = Don't care for CAT24WC01
Doc. No. 1032, Rev. G
8
CAT24C21
either the immediate Address READ or Selective READ
operations. After the 24WC01/02/04/08/16 sends initial
8-bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. TheCAT24C21willcontinuetooutputan8-bitbyte
foreachacknowledgesentbytheMaster. Theoperation
is terminated when the Master fails to respond with an
acknowledge, thus sending the STOP condition.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24C21 acknowledge the word
address,theMasterdeviceresendstheSTARTcondition
and the slave address, this time with the R/W bit set to
one.TheCAT24C21thenrespondswithitsacknowledge
and sends the 8-bit byte requested. The master device
doesnotsendanacknowledgebutwillgenerateaSTOP
condition.
The data being transmitted from the CAT24C21 is
outputtedsequentiallywithdatafromaddressNfollowed
bydatafromaddressN+1.TheREADoperationaddress
counter increments all of the CAT24C21 address bits so
that the entire memory array can be read during one
operation. If more than the 128 bytes are read out, the
counterwill“wraparound”andcontinuetoclockoutdata
bytes.
Sequential Read
The Sequential READ operation can be initiated by
Figure 11. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
* * *
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Figure 12. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
* * *
*
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
Doc. No. 1032, Rev. G
9
CAT24C21
Figure 13. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
ORDERING INFORMATION
Prefix
Device #
24C21
Suffix
CAT
J
I
TE13
Temperature Range
I = Industrial (-40 to 85 C)
Product Number
24C21: 1K
Tape & Reel
TE13: 2000/Reel
Optional
Company ID
E = Extended (-40 to 125 C)
Package
P: PDIP
J: SOIC (JEDEC)
U: TSSOP
R: MSOP
L: PDIP (Lead free, Halogen free)
W: SOIC (Lead free, Halogen free)
Z: MSOP (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a CAT24C21JITE13 (SOIC, Industrial Temperature, 2.5 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
Doc. No. 1032, Rev. G
10
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
I2C is a trademark of Philips.
DDC, DDC1, DDC2 and VESA are trademarks of the Video Electronics Standards Association.
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1032
Revison:
Issue date:
Type:
G
5/9/03
Preliminary
Fax: 408.542.1200
www.catalyst-semiconductor.com
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