CAT24FC32AUI [CATALYST]

CAT24FC32AUI;


型号：	CAT24FC32AUI
厂家：	CATALYST SEMICONDUCTOR
描述：	CAT24FC32AUI
文件：	总12页 (文件大小：599K)
中文：	中文翻译
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CAT24FC32A

32K-Bit Fast Mode I²C Serial CMOS EEPROM

FEATURES

I Fast mode I²C bus compatible*

I Output slope control to eliminate ground

bounce

I Max clock frequency:

I Zero standby current

400 kHz for V_CC=1.8V to 3.6V

I Industrial temperature range

I 1,000,000 program/erase cycles

I 100 years data retention

I Hardware write protect for entire array

I Cascadable for up to eight devices

I 32-Byte page or byte write modes

I Self-timed write cycle with autoclear

I 5 ms max write cycle time

I 8-pin PDIP, 8-pin SOIC (150 and 200 mil) and

8-pin TSSOP packages

I "Green" package options available

I Random and sequential read modes

I Schmitt trigger and spike suppression at SDA

and SCL inputs

DESCRIPTION

The CAT24FC32A is a 32K-bit Serial CMOS EEPROM

internally organized as 4Kx8 bits. The device is

compatible with Fast-mode I²C bus specification and

operates down to 1.8V with a bit rate up to 400 kbit/s.

Extended addressing capability allows up to 8 devices

to share the same bus. Catalyst's advanced CMOS

technology substantially reduces device power

requirements. The device is optimized for high

performanceapplications,wherelowpower,lowvoltage

and high speed operation are required.

CAT24FC32A is available in 8-pin DIP, 8-pin SOIC

(JEDEC and EIAJ) and 8-pin TSSOP packages.

PIN CONFIGURATION

BLOCK DIAGRAM

EXTERNAL LOAD

TSSOP Package (U, Y)

DIP Package (P, L)

SENSE AMPS

SHIFT REGISTERS

OUT

ACK

WORD ADDRESS

BUFFERS

COLUMN

DECODERS

SCL

SDA

SCL

SDA

256

START/STOP

LOGIC

SDA

SOIC Package (J,W) (K, X)

EEPROM

128 X 256

XDEC 128

CONTROL

LOGIC

SCL

SDA

DATA IN STORAGE

HIGH VOLTAGE/

TIMING CONTROL

SCL

STATE COUNTERS

SLAVE

ADDRESS

COMPARATORS

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.

Characteristics subject to change without notice

Doc. No. 1048, Rev. E

CAT24FC32A

PIN FUNCTIONS

Pin Name

Function

A0, A1, A2

SDA

Device Address Inputs

Serial Data/Address

Serial Clock

SCL

Write Protect

V_CC

Power Supply

Ground

V_SS

ABSOLUTE MAXIMUM RATINGS*

*COMMENT

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation of

the device at these or any other conditions outside of those

listed in the operational sections of this specification is not

implied. Exposure to any absolute maximum rating for

extended periods may affect device performance and

reliability.

Voltage on Any Pin with

Respect to Ground⁽¹⁾........... –2.0V to +V_CC+ 2.0V

V_CCwith Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (T_A= 25°C) ................................... 1.0W

Lead Soldering Temperature (10 secs) ............ 300°C

Output Short Circuit Current⁽²⁾........................ 100mA

RELIABILITY CHARACTERISTICS

SymbolParameter

Min.

Max.

1,000,000

100

Units

Reference

Test

Method

(3)

N_END

Endurance

Data Retention

Cycles/Byte

Years

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(3)

T_DR

(3)

V_ZAP

ESD Susceptibility

Latch-up

2000

Volts

(3)(4)

I_LTH

100

RECOMMENDED OPERATING CONDITIONS

Temperature Range

Minimum

Maximum

Industrial

-40˚C

+85˚C

Supply Voltage Range

Device

1.8V to 3.6V

CAT24FC32A

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

Doc. No. 1048, Rev. E

CAT24FC32A

D.C. OPERATING CHARACTERISTICS

Over recommended operating conditions, unless otherwise specified

Symbol

Parameter

Min.

-10

Typ.

Max.

Units

µA

Test Conditions

(4)

Input Leakage Current

= GND to V

(4)

Output Leakage Current

-10

µA

= GND to V

CC1

Power Supply Current

(Operating Write)

= 400kHz

= 3.6V

SCL

Power Supply Current

(Operating Read)

400

µA

= 400kHz

= 3.6V

CC2

SCL

(1)

Standby Current

= 3.6V

= GND or V

(2)

Input Low Voltage

Input High Voltage

Output Low Voltage

-0.5

0.3V

0.7V

V + 0.5

0.4

2.5V ≤ V

≤ 3.6V

OL1

= 3.0 mA

Output Low Voltage

0.2V

1.8V ≤ V

< 2.5V

OL2

= 3 mA

CAPACITANCE T = 25°C, f = 1.0 MHz, V

= 3.6V

SymbolTest

Max.

Units

Conditions

(3)

C_I/O

Input/Output Capacitance (SDA)

V_I/O= 0V

V_IN= 0V

(3)

C_IN

Input Capacitance (A0, A1, A2, SCL, WP)

Note:

(1) Standby current, I < 900 nA; A0, A1, A2, WP connected to GND; SCL, SDA = GND or VCC.

(2) V min and V max are reference values only and are not tested.

(3) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

(4) I/O pins, SDA and SCL do not obstruct the bus lines if V is switched off.

Doc. No. 1048, Rev. E

CAT24FC32A

A.C. CHARACTERISTICS

Over recommended operating conditions, unless otherwise specified (Note 1).

VCC=1.8V - 3.6V

Typ

Min

Max

400

Symbol Parameter

f_SCLClock Frequency

t_SP

Units

kHz

Input Filter Spike Suppression (SDA, SCL)

Clock Low Period

µs

t_LOW

t_HIGH

1.3

Clock High Period

0.6

µs

(2)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Start Condition Hold Time

300

(2)

t_F

t_HD:STA

t_SU:STA

0.6

Start Condition Setup Time (for a

Repeated Start)

0.6

t_HD:DAT

t_SU:DAT

t_SU:STO

t_SU:WP

t_HD:WP

t_AA

Data Input Hold Time

Data In Setup Time

Stop Condition Setup Time

WP Setup Time

µs

100

0.6

WP Hold Time

2.5

SCL Low to Data Out Valid

Data Out Hold Time

900

t_DH

1.3

Time the Bus must be Free Before a New

Transmission Can Start

(2)

t_BUF

µs

(2)

t_OF

Output Fall Time from V_IHmin to V_ILmax

Write Cycle Time (Byte or Page)

250

(3)

t_WC

(2)(4)

Power-Up Timing

Symbol Parameter

Min

Typ

Max

Units

t_PUR

t_PUW

Power-Up to Read Operation

Power-Up to Write Operation

Note:

(1) Test Conditions according to "AC Test Conditions" Table.

(2) This parameter is characterized initially and after a design or process change that affects the parameter. Not 100% tested.

(3) The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the

write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.

(4) t

and t

are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

Doc. No. 1048, Rev. E

CAT24FC32A

AC TEST CONDITIONS

Input pulse voltages

Input rise and fall times

Input reference voltages

Output reference voltages

Output load

0.2V_CCto 0.8V_CC

≤ 50 ns

0.3V_CC, 0.7V_CC

0.5V_CC

Current source: I_OL= 3mA;

CL: 400pF for f_SClmax = 400kHz / 100pF for f_SCLmax = 1 MHz

Figure 1. Bus Timing

HIGH

LOW

SCL

HD:DAT

SU:STA

HD:STA

SU:DAT

SU:STO

BUF

SDA IN

SDA OUT

Figure 2. WP Timing

2nd Byte Address

Data

SCL

SDA

SU:WP

HD:WP

Figure 3. Write Cycle Timing

SCL

SDA

8TH BIT

ACK

BYTE n

STOP

CONDITION

START

CONDITION

ADDRESS

Doc. No. 1048, Rev. E

CAT24FC32A

PIN DESCRIPTION

SCL: Serial Clock

WP: Write Protect

This input controls the device write protect feature. WP

pinconnectedtoV_SSallowswriteoperationstotheentire

memory. When this pin is connected to Vcc, the entire

memoryiswriteprotected. Whenleftfloating,aninternal

pull-down resistor on this input will keep the memory

unprotected. Read operations are not affected.

The serial clock input clocks all data transferred into or

outofthedevice. TheSCLlinerequiresapull-upresistor

if it is driven by an open drain output.

SDA: Serial Data/Address

A0, A1, A2: Device Address Inputs

The bidirectional serial data/address pin is used to

transfer all data into and out of the device. The SDA pin

is an open drain output and can be wire-ORed with other

open drain or open collector outputs. A pull-up resistor

must be connected from SDA line to Vcc. The value of

the pull-up resistor, Rp, can be calculated based on

minimumandmaximumvaluesfromFigure4andFigure

5. (see Note).

Theseinputsareusedforextendedaddressingcapability.

The A0, A1, A2 pins can be hardwired to V_CCor V_SS, or

left unconnected. When hardwired, up to eight

CAT24FC32As may be addressed on a single bus

system. When the pins are left unconnected, the default

valuesarezero.Thelevelsontheseinputsarecompared

with corresponding bits, A2, A1, A0, from the slave

address byte.

Minimum R as a Function of Supply Voltage

Minimum R Value versus Bus Capacitance

(Fast Mode I C Bus / tr max = 300ns)

(IOL = 3mA @ VOLmax)

8.00

7.00

6.00

5.00

4.00

3.00

2.00

1.00

0.00

0.5

100 150 200 250 300

350 400

1.6

2.4

2.8

3.2

3.6

(V)

Cbus (pF)

Figure 4

Figure 5

Note: According to the Fast Mode I²C bus specification, for bus capacitance up to 200pF, the pull up device

can be a resistor. For bus loads between 200pF and 400pF, the pull-up device can be a current source

(Imax=3mA) or a switched resistor circuit.

Doc. No. 1048, Rev. E

CAT24FC32A

FUNCTIONAL DESCRIPTION

SDA when SCL is HIGH. The CAT24FC32A monitors

the SDA and SCL lines and will not respond until this

condition is met.

The CAT24FC32A supports the I²C Bus data

transmission protocol. This Inter-Integrated Circuit Bus

protocol defines any device that sends data to the bus to

be a transmitter and any device receiving data to be a

receiver. The transfer is controlled by the Master device

which generates the serial clock and all START and

STOP conditions for bus access. The CAT24FC32A

operates as a Slave device. Both the Master device and

Slavedevicecanoperateaseithertransmitterorreceiver,

but the Master device controls which mode is activated.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

DEVICE ADDRESSING

After the bus Master sends a START condition, a slave

address byte is required to enable the CAT24FC32A for

a read or write operation (Figure 7). The four most

significant bits of the 8-bit slave address are fixed as

binary 1010. The CAT24FC32A uses the next three bits

as address bits. The address bits A2, A1 and A0 are

used to select which device is accessed from maximum

eightdevicesonthesamebus. Thesebitsmustcompare

to their hardwired input pins. The last bit of the slave

address specifies whether a read or write operation is to

beperformed. Whenthisbitissetto“1”,areadoperation

is initiated, and when set to “0”, a write operation is

selected.

I²C Bus Protocol

The features of the I C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stablewhenevertheclocklineishigh.Anychanges

in the data line while the clock line is high will be

interpretedasaSTARTorSTOPcondition(Figure

6).

Following the START condition and the slave address

byte, the CAT24FC32A monitors the bus and responds

with an acknowledge (on the SDA line) when its address

matches the transmitted slave address. The

CAT24FC32A then performs a read or write operation

depending on the state of the R/W bit.

START Condition

The START condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

Figure 6. Start/Stop Timing

SDA

SCL

START BIT

STOP BIT

Figure 7. Slave Address Bits

A0 R/W

Doc. No. 1048, Rev. E

CAT24FC32A

Acknowledge

WRITE OPERATIONS

Byte Write

Afterasuccessfuldatatransfer, eachreceivingdeviceis

required to generate an acknowledge. The

acknowledging device pulls down the SDA line during

the ninth clock cycle, signaling that it received the 8 bits

of data. The SDA line remains stable LOW during the

HIGH period of the acknowledge related clock pulse

(Figure 8).

In the Byte Write mode, the Master device sends the

START condition and the slave address information

(with the R/W bit set to zero) to the Slave device. After

the Slave generates an acknowledge, the Master sends

two 8-bit address words that are to be written into the

address pointers of the CAT24FC32A. After receiving

another acknowledge from the Slave, the Master device

transmits the data to be written into the addressed

memorylocation.TheCAT24FC32Aacknowledgesonce

more and the Master generates the STOP condition. At

this time, the device begins an internal programming

cycle to nonvolatile memory. While the cycle is in

progress, thedevicewillnotrespondtoanyrequestfrom

the Master device.

The CAT24FC32A responds with an acknowledge after

receivingaSTARTconditionanditsslaveaddress. Ifthe

device has been selected along with a write operation,

it responds with an acknowledge after receiving each 8-

bit byte. The CAT24FC32A does not generate

acknowledge if an internal write cycle is in progress.

WhentheCAT24FC32AbeginsaREADmodeittransmits

8 bits of data, releases the SDA line, and monitors the

line for an acknowledge. Once it receives this

acknowledge,theCAT24FC32Awillcontinuetotransmit

data. IfnoacknowledgeissentbytheMaster, thedevice

terminates data transmission and waits for a STOP

condition. The master must then issue a stop condition

to return the CAT24FC32A to the standby power mode

and place the device in a known state.

Page Write

The CAT24FC32A writes up to 32 bytes of data, in a

single write cycle, using the Page Write operation. The

page write operation is initiated in the same manner as

the byte write operation, however instead of terminating

after the initial byte is transmitted, the Master is allowed

to send up to 31 additional bytes. After each byte has

Figure 8. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 9. Byte Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

—A

A —A

DATA

SDA LINE

X X X

X = Don't care bit

Doc. No. 1048, Rev. E

CAT24FC32A

WRITE PROTECTION

been transmitted, CAT24FC32A will respond with an

acknowledge,andinternallyincrementthefiveloworder

address bits by one. The high order bits remain

unchanged.

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is connected to V , the entire memory

array is protected and becomes read only. The

CAT24FC32Awillacceptbothslaveandbyteaddresses,

but the memory location accessed is protected from

programming by the device’s failure to send an

acknowledge after the first byte of data is received. The

WP input is sampled in the end of acknowledge pulse

after second address byte, accordingly with setup and

hold times relative to negative clock edge (Figure 2).

If the Master transmits more than 32 bytes before

sendingtheSTOPcondition,theaddresscounter‘wraps

around’, and previously transmitted data will be

overwritten.

When all 32 bytes are received, and the STOP condition

has been sent by the Master, the internal programming

cycle begins. At this point, all received data is written to

the CAT24FC32A in a single write cycle.

Acknowledge Polling

READ OPERATIONS

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host’s write operation,

CAT24FC32A initiates the internal write cycle. ACK

pollingcanbeinitiatedimmediately.Thisinvolvesissuing

the start condition followed by the slave address for a

write operation. If CAT24FC32A is still busy with the

writeoperation,noACKwillbereturned.IfCAT24FC32A

has completed the write operation, an ACK will be

returned and the host can then proceed with the next

read or write operation.

The READ operation for the CAT24FC32A is initiated in

the same manner as the write operation with one

exception, that R/W bit is set to one. Three different

READ operations are possible: Immediate/Current

Address READ, Selective/Random READ and

Sequential READ.

Immediate/Current Address Read

The CAT24FC32A’s address counter contains the

address of the last byte accessed, incremented by one.

In other words, if the last READ or WRITE access was

Figure 10. Page Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

—A

A —A

DATA

DATA n

DATA n+31

SDA LINE

X X X X

X=Don't care bit

Figure 11. Immediate Address Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA

SDA LINE

SCL

SDA

8TH BIT

DATA OUT

NO ACK

STOP

Doc. No. 1048, Rev. E

CAT24FC32A

to address N, the READ immediately following would

access data from address N+1. If N=E (where E=4095),

then the counter will ‘wrap around’ to address 0 and

continue to clock out data. After the CAT24FC32A

receives its slave address information (with the R/W bit

set to one), it issues an acknowledge, then transmits the

8 bit byte requested. The master device does not send

an acknowledge, but will generate a STOP condition.

Sequential Read

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations.AftertheCAT24FC32Asendstheinitial8-bit

byte requested, the Master will respond with an

acknowledge which tells the device it requires more

data. The CAT24FC32A will continue to output an 8-bit

byte for each acknowledge sent by the Master. The

operationwillterminatewhentheMasterfailstorespond

with an acknowledge, thus sending the STOP condition.

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a

READ operation. The Master device first performs a

‘dummy’writeoperationbysendingtheSTARTcondition,

slave address and byte addresses of the location it

wishes to read. After CAT24FC32A acknowledges, the

Master device sends the START condition and the

slave address again, this time with the R/W bit set to

one. The CAT24FC32A then responds with its

acknowledge and sends the 8-bit byte requested. The

master device does not send an acknowledge but will

generate a STOP condition.

The data being transmitted from CAT24FC32A is

outputtedsequentiallywithdatafromaddressNfollowed

bydatafromaddressN+1.TheREADoperationaddress

counter increments all of the CAT24FC32A address bits

so that the entire memory array can be read during one

operation. After the last memory address is read out, the

counter will ‘wrap around’ and continue to clock out data

bytes.

Figure 12. Selective Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

—A A —A

SLAVE

ADDRESS

DATA

SDA LINE

X X X X

X = Don't care bit

Figure 13. Sequential Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

Doc. No. 1048, Rev. E

CAT24FC32A

ORDERING INFORMATION

Prefix

Device #

24FC32A

Suffix

(2)

CAT

Rev A

TE13

Temperature Range

Optional

Company ID

Tape & Reel

Product

Number

Package

P: PDIP

Die Revision

K: SOIC (EIAJ)

J: SOIC (JEDEC)

U: TSSOP

L: PDIP (Lead free, Halogen free)

X: SOIC (EIAJ, Lead free, Halogen free)

W: SOIC (JEDEC, Lead free, Halogen free)

Y: TSSOP (Lead free, Halogen free)

Notes:

(1) The device used in the above example is a CAT24FC32AKI-TE13 (SOIC, Industrial Temperature, Tape & Reel)

(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWA). For additional

information, please contact your Catalyst sales office.

REVISION HISTORY

Date

Revision Comments

12/10/2003

04/18/2004

Eliminated Commercial temperature range

Delete data sheet designation

Add Lead Free Logo

Update Features

Update Ordering Information

Add Revision History

Update Rev Number

7/7/2004

Add die revision to Ordering Information

Doc. No. 1048, Rev. E

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™

AE²™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Fax: 408.542.1200

Publication #: 1048

Revison:

Issue date:

07/07/04

www.catalyst-semiconductor.com

CAT24FC32AUI [CATALYST]

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