CAT24WC03GLA-1.8REV-C [CATALYST]
EEPROM, 256X8, Serial, CMOS, PDIP8, 0.300 INCH, GREEN, PLASTIC, MS-001, DIP-8;
| 型号： | CAT24WC03GLA-1.8REV-C |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 256X8, Serial, CMOS, PDIP8, 0.300 INCH, GREEN, PLASTIC, MS-001, DIP-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 |
| 文件： | 总14页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not recommended for new design,
replace with CAT24C03/05
CAT24WC03/05
2K/4K-Bit Serial EEPROM with Partial Array Write Protection
FEATURES
■ Self-timed write cycle with auto-clear
■ 400 kHz I2C bus compatible*
■ 1.8 to 5.5 volt operation
■ 1,000,000 Program/Erase cycles
■ 100 Year data retention
■ Low power CMOS technology
■ 8-pin DIP, 8-pin SOIC, 8-lead MSOP and 8-pin
TSSOP Package
■ Write protect feature
–Top 1/2 array protected when WP at VIH
■ Commercial, industrial and automotive
temperature ranges
■ 16-Byte page write buffer
■ "Green" package options available
DESCRIPTION
The CAT24WC03/05 is a 2K/4K-bit Serial CMOS
EEPROM internally organized as 256/512 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
CAT24WC03/05 features a 16-byte page write buffer.
The device operates via the I2C bus serial interface, has
a special write protection feature, and is available in 8-
pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
BLOCK DIAGRAM
DIP Package (P, L, GL)
SOIC Package (J, W, GW)
EXTERNAL LOAD
SENSE AMPS
SHIFT REGISTERS
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
D
0
1
2
CC
0
1
2
V
CC
WP
OUT
WP
ACK
SCL
SDA
SCL
SDA
V
V
CC
V
V
SS
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SS
MSOP Package (R, Z, GZ)
TSSOP Package (U, Y, GY)
START/STOP
SDA
WP
1
2
3
4
8
7
6
5
A
A
A
1
2
3
4
8
7
6
5
0
1
2
V
CC
WP
A
A
A
0
1
2
V
CC
WP
LOGIC
SCL
SDA
SCL
SDA
V
E2PROM
SS
V
XDEC
SS
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
Function
DATA IN STORAGE
A0, A1, A2
SDA
Device Address Inputs
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
SCL
WP
Write Protect
SCL
STATE COUNTERS
VCC
+1.8V to +5.5V Power Supply
Ground
SLAVE
ADDRESS
COMPARATORS
A
A1
A2
0
VSS
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
1
CAT24WC03/05
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) .................................. 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
V
= +1.8V to +5.5V, unless otherwise specified.
CC
Limits
Typ
Symbol
Parameter
Min
Max
Units
mA
µA
µA
µA
V
Test Conditions
fSCL = 100 kHz
ICC
Power Supply Current
3
(5)
IS
Standby Current (VCC = 5.0V)
Input Leakage Current
0
10
VIN = GND or VCC
VIN = GND to VCC
VOUT = GND to VCC
ILI
ILO
Output Leakage Current
Input Low Voltage
10
VIL
–1
VCC x 0.3
VCC + 0.5
0.4
VIH
Input High Voltage
VCC x 0.7
V
VOL1
VOL2
Output Low Voltage (VCC = 3.0V)
Output Low Voltage (VCC = 1.8V)
V
IOL = 3 mA
0.5
V
IOL = 1.5 mA
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max
Units
Conditions
VI/O = 0V
VIN = 0V
(3)
CI/O
8
6
pF
pF
(3)
CIN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Standby Current (I ) = 0µA (<900nA).
SB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
2
CAT24WC03/05
A.C. CHARACTERISTICS
V
CC
= +1.8V to +5.5V, unless otherwise specified.
Read & Write Cycle Limits
CAT24WCXX-1.8
1.8V-5.5V
CAT24WCXX
2.5V-5.5V 4.5V-5.5V
Min.
Max.
Min.
Max.
Min.
Max.
Symbol Parameter
Units
FSCL
TI(1)
Clock Frequency
100
100
400
kHz
Noise Suppression Time Constant at
SCL, SDA Inputs
200
3.5
200
200
1
ns
µs
µs
SCL Low to SDA Data Out and ACK
Out
tAA
3.5
Time the Bus Must be Free Before
a New Transmission Can Start
(1)
tBUF
4.7
4.7
1.2
µs
µs
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
4.7
4
4
4.7
4
0.6
1.2
0.6
tHIGH
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
µs
tSU:STA
4.7
4.7
0.6
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
0
ns
ns
µs
ns
µs
ns
Data In Setup Time
50
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
1
0.3
(1)
tF
300
300
300
tSU:STO
tDH
4
4
0.6
100
100
100
(1)(2)
Power-Up Timing
Symbol
tPUR
Parameter
Max
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
Write Cycle Limits
Symbol
Parameter
Min
Typ
Max
Units
tWR
Write Cycle Time
10
ms
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
3
CAT24WC03/05
clock all data transfers into or out of the device. This is
an input pin.
FUNCTIONAL DESCRIPTION
The CAT24WC03/05 supports the I2C Bus data trans-
missionprotocol.ThisInter-IntegratedCircuitBusproto-
col defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver.DatatransferiscontrolledbytheMasterdevice
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC03/05
operates as a Slave device. Both the Master and Slave
devicescanoperateaseithertransmitterorreceiver,but
the Master device controls which mode is activated. A
maximum of 8 devices (24WC03) and 4 devices
(24WC05) may be connected to the bus as determined
by the device address inputs A0, A1, and A2.
SDA: Serial Data/Address
The CAT24WC03/05 bidirectional serial data/address
pinisusedtotransferdataintoandoutofthedevice.The
SDA pin is an open drain output and can be wire-ORed
with other open drain or open collector outputs.
A0, A1, A2: Device Address Inputs
These inputs set device address when cascading mul-
tiple devices. When these pins are left floating the
default values are zeros.
A maximum of eight devices can be cascaded when
using the CAT24WC03. All three address pins are used
for CAT24WC03. If only one CAT24WC03 is addressed
on the bus, all three address pins (A0, A1, and A2) can
PIN DESCRIPTIONS
be left floating or connected to VSS
.
SCL: Serial Clock
The CAT24WC03/05 serial clock input pin is used to
Figure 1. Bus Timing
Figure 2. Write Cycle Timing
Figure 3. Start/Stop Timing
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
4
CAT24WC03/05
A total of four devices can be addressed on a single bus
when using the CAT24WC05 device. Only A1 and A2
address pins are used with this device. The A0 address
pin is a no connect pin and can be tied to VSS or left
floating. If only one CAT24WC05 is being addressed on
thebus, theaddresspins(A1andA2)canbeleftfloating
or connected to VSS.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC03/05 (see Fig. 5). The next
three significant bits (A2, A1, A0) are the device address
bits and define which device or which part of the device
the Master is accessing. Up to eight CAT24WC03 and
four CAT24WC05 can be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
WP: Write Protect
IftheWPpinistiedtoVCC theupperhalfofmemoryarray
becomes Write Protected (READ only)(locations 80H to
FFH for the CAT24WC03 and locations 100H to 1FFH
for the CAT24WC05). When the WP pin is tied to VSS or
left floating normal read/write operations are allowed to
the device.
I2C BUS PROTOCOL
ThefollowingdefinesthefeaturesoftheI2Cbusprotocol:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
addressbyte, theCAT24WC03/05monitorsthebusand
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC03/05thenperformsaReadorWriteoperation
depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC03/05 monitor
the SDA and SCL lines and will not respond until this
condition is met.
Afterasuccessfuldatatransfer, eachreceivingdeviceis
required to generate an acknowledge. The
Acknowledging device pulls down the SDA line during
the ninth clock cycle, signaling that it received the 8 bits
of data.
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
24WC03
1
1
0
0
1
1
0
0
A2
A2
A1
A1
A0 R/W
a8 R/W
24WC05
*
A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.
** a8 corresponds to the address of the memory array address word.
***A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
5
CAT24WC03/05
The CAT24WC03/05 responds with an acknowledge
afterreceivingaSTARTconditionanditsslaveaddress.
If the device has been selected along with a write
operation,itrespondswithanacknowledgeafterreceiving
each 8-bit byte.
The CAT24WC03/05 writes up to 16 bytes of data in a
single write cycle, using the Page Write operation. The
Page Write operation is initiated in the same manner as
theByteWriteoperation;however,insteadofterminating
after the initial word is transmitted, the Master is allowed
to send up to 15 additional bytes. After each byte has
been transmitted, the CAT24WC03/05 will respond with
an acknowledge and internally increment the low order
address bits by one. The high order bits remain
unchanged.
WhentheCAT24WC03/05isinaREADmodeittransmits
8 bits of data, releases the SDA line, and monitors the
line for an acknowledge. Once it receives this
acknowledge, the CAT24WC03/05 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition.
If the Master transmits more than 16 bytes prior to
sendingtheSTOPcondition,theaddresscounter‘wraps
around’, and previously transmitted data will be
overwritten.
WRITE OPERATIONS
Once all 16 bytes are received and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point all received data is written to
the CAT24WC03/05 in a single write cycle.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
the byte address that is to be written into the address
pointer of the CAT24WC03/05. After receiving another
acknowledgefromtheSlave,theMasterdevicetransmits
the data byte to be written into the addressed memory
location. The CAT24WC03/05 acknowledge once more
and the Master generates the STOP condition, at which
time the device begins its internal programming cycle to
nonvolatile memory. While this internal cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
Acknowledge Polling
Thedisablingoftheinputscanbeusedtotakeadvantage
of the typical write cycle time. Once the stop condition
isissuedtoindicatetheendofthehost’swriteoperation,
the CAT24WC03/05 initiates the internal write cycle.
ACK polling can be initiated immediately. This involves
issuing the start condition followed by the slave address
for a write operation. If the CAT24WC03/05 is still busy
with the write operation, no ACK will be returned. If the
CAT24WC03/05 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS
DATA
SDA LINE
S
P
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
DATA n+P
SDA LINE
S
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
6
CAT24WC03/05
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E = 255
fortheCAT24WC03and511fortheCAT24WC05),then
the counter will ‘wrap around’ to address 0 and continue
to clock out data. After the CAT24WC03/05 receives its
slave address information (with the R/W bit set to one),
it issues an acknowledge, then transmits the 8-bit byte
requested. The master device does not send an
acknowledge but will generate a STOP condition.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the upper half (locations 80H
to FFH for CAT24WC03 and locations 100H to 1FFH for
CAT24WC05) of the memory array is protected and
becomes read only. The CAT24WC03/05 will accept
both slave and byte addresses, but the memory location
accessedisprotectedfromprogrammingbythedevice’s
failuretosendanacknowledgeafterthefirstbyteofdata
is received.
Selective Read
Selective READ operations allow the Master device to
select at random any memory location for a READ
operation. The Master device first performs a ‘dummy’
write operation by sending the START condition, slave
address and byte address of the location it wishes to
read. After the CAT24WC03/05 acknowledge the word
address,theMasterdeviceresendstheSTARTcondition
and the slave address, this time with the R/W bit set to
one. The CAT24WC03/05 then responds with its
acknowledge and sends the 8-bit byte requested. The
master device does not send an acknowledge but will
generate a STOP condition.
READ OPERATIONS
The READ operation for the CAT24WC03/05 is initiated
in the same manner as the write operation with the one
exception that the R/W bit is set to a one. Three different
READ operations are possible: Immediate Address
READ, Selective READ and Sequential READ.
Immediate Address Read
The CAT24WC03/05 address counter contains the
address of the last byte accessed incremented by one.
Figure 8. Immediate Address Read Timing
S
T
S
A
R
T
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
SDA LINE
S
P
A
C
K
N
O
DATA
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE
ADDRESS (n)
SLAVE
ADDRESS
SDA LINE
S
S
P
A
C
K
A
C
K
A
C
K
N
O
DATA n
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
7
CAT24WC03/05
Sequential Read
The data being transmitted from the CAT24WC03/05 is
outputtedsequentiallywithdatafromaddressNfollowed
bydatafromaddressN+1.TheREADoperationaddress
counter increments all of the CAT24WC03/05 address
bits so that the entire memory array can be read during
one operation. If more than the E (where E = 255 for the
CAT24WC03 and 511 for the CAT24WC05) bytes are
read out, the counter will “wrap around” and continue to
clock out data bytes.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations.AftertheCAT24WC03/05sendstheinitial8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC03/05 will continue to output an 8-
bit byte for each acknowledge sent by the Master. The
operationisterminatedwhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
8
CAT24WC03/05
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
0.355 (9.02)
0.400 (10.16)
0.120 (3.05)
0.180 (4.57) MAX
0.150 (3.81)
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
0.100 (2.54)
BSC
0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
8-LEAD 150 MIL WIDE SOIC (J, W, GW)
0.1497 (3.80) 0.2284 (5.80)
0.1574 (4.00) 0.2440 (6.20)
0.1890 (4.80)
0.1968 (5.00)
0.0099 (0.25)
X 45
0.0196 (0.50)
0.0075 (0.19)
0.0098 (0.25)
0.0532 (1.35)
0.0688 (1.75)
0 —8
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0.0040 (0.10)
0.0098 (0.25)
0.016 (0.40)
0.050 (1.27)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
9
CAT24WC03/05
8 LEAD MSOP (R, Z, GZ)
0.38
0.28
0.0150
0.0110
0.1970
0.1890
5.00
4.80
S
0.0256 [0.65] BSC
3.10
2.90
0.1220
0.1142
0.0374
0.0295
0.95
0.75
0.0433 [1.10] MAX.
0.0059
0.0020
0.15
0.05
0.039 [0.10] MAX.
S
S
0.0150
0.0110
0.38
0.28
WITH PLATING
0.0091 0.23
0.0051 0.13
0.0050 [0.127]
BASE METAL
0.1220
0.1142
3.10
2.90
0.0276
0.0157
0.70
0.40
0˚ - 6˚
WITH PLATING
0.0118 [0.30] REF.
SECTION A - A
Notes:
(1) All dimensions are in mm Angles in degrees.
2
3
4
Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side.
Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side.
Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm.
(5) This part is compliant with JEDEC Specification MO-187 Variations AA.
(6) Lead span/stand off height/coplanarity are considered as special characteristics. (S)
(7) Controlling dimensions in inches. [mm]
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
10
CAT24WC03/05
8-LEAD TSSOP (U, Y, GY)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
11
CAT24WC03/05
ORDERING INFORMATION
Prefix
Device #
24WC03
Suffix
CAT
J
-1.8
I
REV-C
TE13
Optional
Company ID
Temperature Range
Product Number
24WC03: 2K
24WC05: 4K
Tape & Reel
Blank = Commercial (0°C to 70°C)
I = Industrial (-40°C to 85°C)
A = Automotive (-40°C to 105°C)
E = Extended (-40°C to 125°C)
Package
P: PDIP
J: SOIC, JEDEC
R: MSOP
Operating Voltage
Blank: 2.5V - 5.5V
1.8: 1.8V - 5.5V
Die Revision
24WC03: C
24WC05: A
U: TSSOP
L: PDIP (Lead-free, Halogen-free)
W: SOIC, JEDEC (Lead-free, Halogen-free)
Z: MSOP (Lead-free, Halogen-free)
Y: TSSOP (Lead-free, Halogen-free)
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)
Notes:
(1) The device used in the above example is a CAT24WC03JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating
Voltage, Tape & Reel)
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
12
CAT24WC03/05
REVISION HISTORY
Date
Revision Comments
7/24/2001
A
B
C
Initial issue
Added: CAT24WC03 not recommended for new designs. See
CAT24FC03 data sheet.
2/3/2004
04/18/04
Add Lead Free Logo
Update Features
Update Ordering Information
Add Revision History
Update Rev Number
05/18/04
D
Delete: CAT24WC03 not recommended for new designs. See
CAT24FC03 data sheet.
Update Revision History
Update Rev Number
06/07/04
08/12/05
E
F
Added Die Revision to Ordering Information
Update Features
Update Pin Functions
Update Reliability Characteristics
Update D.C. Operating Characteristics
Update A.C. Characteristics
Add Page Dimensions
Update Ordering Information
07/26/06
G
Insert: Not recommended for new design, replace with CAT24C03/05
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1005, Rev. G
13
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
2
DPP ™
AE ™
MiniPot™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Publication #: 1005
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Revison:
G
Issue date:
07/26/06
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