CAT24WC256WI-3REVA [CATALYST]
EEPROM, 32KX8, Serial, CMOS, PDSO8, LEAD AND HALOGEN FREE, SOIC-8;
| 型号： | CAT24WC256WI-3REVA |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 32KX8, Serial, CMOS, PDSO8, LEAD AND HALOGEN FREE, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总10页 (文件大小：416K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT24WC256
256K-Bit I2C Serial CMOS EEPROM
(CAT24WC256 not recommended for new designs. See CAT24FC256 data sheet.)
TM
FEATURES
I 1MHz I2C bus compatible*
I Write protect feature
– entire array protected when WP at VIH
I 100,000 program/erase cycles
I 100 year data retention
I 1.8 to 6 volt operation
I Low power CMOS technology
I 64-byte page write buffer
I 8-pin DIP or 8-pin SOIC
I Self-timed write cycle with auto-clear
I "Green" package options available
I Commercial, industrial and automotive
temperature ranges
DESCRIPTION
features a 64-byte page write buffer. The device oper-
ates via the I2C bus serial interface and is available in 8-
pin DIP or 8-pin SOIC packages.
TheCAT24WC256isa256K-bitSerialCMOSEEPROM
internally organized as 32,768 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reducesdevicepowerrequirements.TheCAT24WC256
BLOCK DIAGRAM
PIN CONFIGURATION
EXTERNAL LOAD
DIP Package (P, L)
SENSE AMPS
SHIFT REGISTERS
1
2
3
4
8
7
6
5
V
D
A0
A1
CC
OUT
WP
ACK
NC
SCL
SDA
V
V
CC
SS
V
SS
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
512
START/STOP
SOIC Package (J, W, K, X)
SDA
LOGIC
1
2
3
4
8
7
6
5
V
A0
A1
CC
WP
EEPROM
512X512
SCL
SDA
XDEC
512
NC
V
SS
CONTROL
LOGIC
WP
PIN FUNCTIONS
Pin Name
Function
DATA IN STORAGE
A0, A1
SDA
SCL
WP
Address Inputs
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
Write Protect
SCL
STATE COUNTERS
VCC
+1.8V to +6.0V Power Supply
Ground
A0
A1
SLAVE
ADDRESS
COMPARATORS
VSS
NC
No Connect
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1031, Rev. F
1
CAT24WC256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
V
CC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Reference Test Method
Min
Typ
Max
Units
Cycles/Byte
Years
(3)
NEND
MIL-STD-883, Test Method 1033 100,000
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
100
2000
100
(3)
VZAP
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Symbol Parameter
Test Conditions
Min
Typ
Max
Units
I
Power Supply Current - Read
Power Supply Current - Write
Standby Current
f
= 100 KHz
SCL
1
3
1
mA
CC1
V
CC
=5V
I
f
= 100KHz
mA
CC2
SCL
V
=5V
CC
(5)
SB
I
V
V
= GND or V
µA
IN
CC
V
CC
=5V
I
Input Leakage Current
Output Leakage Current
Input Low Voltage
= GND to V
1
1
µA
µA
LI
IN
CC
I
V
= GND to V
OUT CC
LO
V
IL
–1
V
x 0.3
V
V
V
V
CC
V
Input High Voltage
V
x 0.7
V
+ 0.5
CC
IH
CC
V
Output Low Voltage (V
= +3.0V)
= +1.8V)
I
I
= 3.0 mA
= 1.5 mA
0.4
OL1
OL2
CC
CC
OL
V
Output Low Voltage (V
0.5
OL
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
CC
A
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (SCL, WP, A0, A1)
Conditions
VI/O = 0V
VIN = 0V
Min
Typ
Max
8
Units
pF
(3)
CI/O
(3)
CIN
6
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
Doc. No. 1031, Rev. F
2
CAT24WC256
A.C. CHARACTERISTICS
= +1.8V to +6V, unless otherwise specified
V
CC
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V
Min
Max
100
3.5
Min
Max
400
0.9
Min
Max
1000
0.55
Units
kHz
µs
FSCL
tAA
Clock Frequency
SCL Low to SDA Data Out
and ACK Out
0.1
0.05
1.2
0.05
0.5
(2)
tBUF
Time the Bus Must be Free Before 4.7
a New Transmission Can Start
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
4.0
0.6
1.2
0.6
0.6
0.25
0.6
µs
µs
µs
µs
tHIGH
Clock High Period
0.4
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
0.25
tHD:DAT
tSU:DAT
Data In Hold Time
0
0
0
ns
ns
µs
ns
µs
ns
ms
Data In Setup Time
100
100
100
(2)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
1.0
0.3
0.3
(2)
tF
300
300
100
tSU:STO
tDH
4.7
0.6
50
0.25
50
100
tWR
10
10
10
(2)(3)
Power-Up Timing
Symbol Parameter
Min
Typ
Max
1
Units
ms
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
ms
Note:
(1) AC measurement conditions:
RL (connects to V ): 0.3V to 0.7 V
CC
CC
CC
Input rise and fall times: < 50ns
Input and output timing reference voltages: 0.5 V
CC
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
Doc. No. 1031, Rev. F
3
CAT24WC256
SDA: Serial Data/Address
FUNCTIONAL DESCRIPTION
The bidirectional serial data/address pin is used to
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
The CAT24WC256 supports the I2C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC256
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. When this pin is tied to Vcc, the
entire memory is write protected. When left floating,
memory is unprotected.
A0, A1: Device Address Inputs
These pins are hardwired or left connected. When
hardwired,uptofourCAT24WC256'smaybeaddressed
on a single bus system. When the pins are left uncon-
nected, the default values are zero.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
Figure 1. Bus Timing
t
t
t
F
HIGH
R
t
t
LOW
LOW
SCL
t
t
HD:DAT
SU:STA
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
DH
AA
SDA OUT
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 3. Start/Stop Timing
SDA
SCL
START BIT
STOP BIT
Doc. No. 1031, Rev. F
4
CAT24WC256
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
many as four devices on the same bus. These bits must
compare to their hardwired input pins. The last bit of the
slave address specifies whether a Read or Write opera-
tion is to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write opera-
tion is selected.
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
After the Master sends a START condition and the slave
address byte, the CAT24WC256 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC256 then performs a Read or Write operation
depending on the state of the R/W bit.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC256 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Acknowledge
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
TheCAT24WC256respondswithanacknowledgeafter
receivingaSTARTconditionanditsslaveaddress. Ifthe
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The five most
significant bits of the 8-bit slave address are fixed as
10100(Fig. 5). The CAT24WC256 uses the next two bits
as address bits. The address bits A1 and A0 allow as
When the CAT24WC256 begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24WC256 will continue to transmit
data. IfnoacknowledgeissentbytheMaster, thedevice
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
Figure 5. Slave Address Bits
1
0
1
0
0
A1
A0 R/W
Doc. No. 1031, Rev. F
5
CAT24WC256
terminates data transmission and waits for a STOP
condition.
IftheMastertransmitsmorethan64bytesbeforesending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
When all 64 bytes are received, and the STOP condition
has been sent by the Master, the internal programming
cycle begins. At this point, all received data is written to
the CAT24WC256 in a single write cycle.
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
address pointers of the CAT24WC256. After receiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC256 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC256 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC256 is still busy with the
write operation, no ACK will be returned. If
CAT24WC256 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
The CAT24WC256 writes up to 64 bytes of data, in a
single write cycle, using the Page Write operation. The
page write operation is initiated in the same manner as
the byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 63 additional bytes. After each byte has
been transmitted, CAT24WC256 will respond with an
acknowledge, and internally increment the six low order
address bits by one. The high order bits remain un-
changed.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the entire memory array is
protected and becomes read only. The CAT24WC256
will accept both slave and byte addresses, but the
memory location accessed is protected from program-
ming by the device’s failure to send an acknowledge
after the first byte of data is received.
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
A
DATA
15
8
7
0
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
=Don't Care Bit
*
Figure 7. Page Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
DATA n
DATA n+63
15
8
7
SDA LINE
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
=Don't Care Bit
*
Doc. No. 1031, Rev. F
6
CAT24WC256
wishes to read. After CAT24WC256 acknowledges, the
MasterdevicesendstheSTARTconditionandtheslave
address again, this time with the R/W bit set to one. The
CAT24WC256 then responds with its acknowledge and
sends the 8-bit byte requested. The master device does
not send an acknowledge but will generate a STOP
condition.
READ OPERATIONS
The READ operation for the CAT24WC256 is initiated in
the same manner as the write operation with one excep-
tion, that R/W bit is set to one. Three different READ
operations are possible: Immediate/Current Address
READ,Selective/RandomREADandSequentialREAD.
Immediate/Current Address Read
Sequential Read
The CAT24WC256’s address counter contains the ad-
dress of the last byte accessed, incremented by one. In
other words, if the last READ or WRITE access was to
address N, the READ immediately following would ac-
cess data from address N+1. If N=E (where E=32767),
then the counter will ‘wrap around’ to address 0 and
continue to clock out data. After the CAT24WC256
receives its slave address information (with the R/W bit
set to one), it issues an acknowledge, then transmits the
8 bit byte requested. The master device does not send
an acknowledge, but will generate a STOP condition.
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations. After the CAT24WC256 sends the initial 8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC256 will continue to output an 8-bit
byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
The data being transmitted from CAT24WC256 is out-
puttedsequentiallywithdatafromaddressNfollowedby
data from address N+1. The READ operation address
counterincrementsalloftheCAT24WC256addressbits
so that the entire memory array can be read during one
operation. If more than E (where E=32767) bytes are
read out, the counter will ‘wrap around’ and continue to
clock out data bytes.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
Doc. No. 1031, Rev. F
7
CAT24WC256
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
—A A —A
0
SLAVE
ADDRESS
A
DATA
15
8
7
SDA LINE
S
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
=Don't Care Bit
*
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
Doc. No. 1031, Rev. F
8
CAT24WC256
ORDERING INFORMATION
Prefix
Device #
24WC256
Suffix
TE13
Rev B(2)
CAT
K
-1.8
I
Temperature Range
Optional
Company ID
Product
Number
Tape & Reel
Blank = Commercial (0˚ - 70˚C)
I = Industrial (-40˚ - 85˚C)
A = Automotive (-40˚ - 105˚C)*
Die Revision
24WC256: A, B
Package
Operating Voltage
Blank: 2.5 to 6.0V
1.8: 1.8 to 6.0V
P: PDIP
K: SOIC (EIAJ)
J: SOIC (JEDEC)
3: 3.0V to 5.5V
L: PDIP (Lead free, Halogen free)
W: SOIC, JEDEC (Lead free, Halogen free)
X: SOIC, EIAJ (Lead free, Halogen free)
* -40˚ to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 24WC256KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel).
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWB). For additional
information, please contact your Catalyst sales office.
Doc. No. 1031, Rev. F
9
REVISION HISTORY
Date
Revision Comments
Added: CAT24WC256 not recommended for new designs. See
CAT24FC256 data sheet.
02/03/2004
04/18/04
C
D
Delete data sheet designation
Update Features
Update Ordering Information
07/23/04
08/05/04
E
F
Add die revision to Ordering Information
Update DC Operating Characteristics table and notes
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory ™, DPP ™, EZDim ™, LDD ™, MiniPot™ and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1031
Revison:
F
Issue date:
08/05/04
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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