CAT24WC33LETE13B [CATALYST]
32K/64K-Bit I2C Serial CMOS EEPROM; 32K / 64K位I2C串行EEPROM CMOS
| 型号： | CAT24WC33LETE13B |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 32K/64K-Bit I2C Serial CMOS EEPROM |
| 文件： | 总12页 (文件大小：637K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT24WC33/65
32K/64K-Bit I2C Serial CMOS EEPROM
FEATURES
I 400 KHz I2C Bus Compatible*
I Commercial, Industrial and Automotive Tem-
perature Ranges
I 1.8 to 5.5 Volt Read and Write Operation
I Cascadable for up to Eight Devices
I 32/64-Byte Page Write Buffer
I Write Protection
–Bottom 1/4 Array Protected When WP at VIH
I 1,000,000 Program/Erase Cycles
I 100 Year Data Retention
I Self-Timed Write Cycle with Auto-Clear
I 8-Pin DIP or 8-Pin SOIC
I Schmitt Trigger Inputs for Noise Protection
DESCRIPTION
The CAT24WC33/65 is a 32K/64K-bit Serial CMOS
E2PROM internally organized as 4096/8192 words of 8
bits each. Catalyst’s advanced CMOS technology sub-
stantially reduces device power requirements. The
CAT24WC33/65 features a 32-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
BLOCK DIAGRAM
EXTERNAL LOAD
DIP Package (P, L)
SENSE AMPS
SHIFT REGISTERS
D
OUT
1
2
3
4
8
7
6
5
A
V
CC
WP
0
ACK
A
1
V
A
SCL
SDA
CC
2
V
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
SS
V
SS
256
START/STOP
SOIC Package (J, W, K, X)
SDA
LOGIC
1
2
3
4
8
7
6
5
A
A
A
V
CC
WP
0
1
2
E2PROM
128/256 X 256
XDEC 128/256
SCL
SDA
CONTROL
LOGIC
V
SS
WP
PIN FUNCTIONS
Pin Name
Function
DATA IN STORAGE
A0, A1, A2
SDA
Device Address Inputs
Serial Data/Address
Serial Clock
HIGH VOLTAGE/
TIMING CONTROL
SCL
WP
Write Protect
SCL
STATE COUNTERS
VCC
+1.8V to +5.5V Power Supply
Ground
SLAVE
ADDRESS
COMPARATORS
A
A1
A2
0
VSS
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1049, Rev. D
1
CAT24WC33/65
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +5.5V, unless otherwise specified.
V
CC
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
mA
µA
µA
µA
V
Test Conditions
I
I
I
I
Power Supply Current
3
1
f
= 100 KHz
= GND or V
= GND to V
CC
SCL
(5)
Standby Current (V
= 5V)
V
V
V
SB
LI
CC
IN
CC
CC
Input Leakage Current
10
10
IN
Output Leakage Current
Input Low Voltage
= GND to V
CC
LO
OUT
V
V
V
V
–1
V
x 0.3
IL
CC
Input High Voltage
V
x 0.7
V
+ 0.5
V
IH
CC
CC
Output Low Voltage (V
Output Low Voltage (V
= +3.0V)
= +1.8V)
0.4
0.5
V
I
I
= 3.0 mA
OL1
OL2
CC
CC
OL
OL
V
= 1.5 mA
CAPACITANCE T = 25°C, f = 1.0 MHz, V
= 5V
A
CC
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, SCL, WP)
Max.
Units
Conditions
VI/O = 0V
VIN = 0V
(3)
CI/O
8
6
pF
pF
(3)
CIN
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1049, Rev. D
2
CAT24WC33/65
A.C. CHARACTERISTICS
= +1.8V to +5.5V, unless otherwise specified
V
CC
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
CAT24WCXX-1.8
1.8V-5.5V
CAT24WCXX
2.5V-5.5V 4.5V-5.5V
Min.
Max.
Min.
Max.
Min.
Max.
Symbol Parameter
Units
FSCL
TI(1)
Clock Frequency
100
100
400
kHz
Noise Suppression Time Constant at
SCL, SDA Inputs
200
3.5
200
200
1
ns
µs
µs
SCL Low to SDA Data Out and ACK
Out
tAA
3.5
Time the Bus Must be Free Before
a New Transmission Can Start
(1)
tBUF
4.7
4.7
1.2
µs
µs
µs
tHD:STA
tLOW
Start Condition Hold Time
Clock Low Period
4
4.7
4
4
4.7
4
0.6
1.2
0.6
tHIGH
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
µs
tSU:STA
4.7
4.7
0.6
tHD:DAT
Data In Hold Time
0
0
0
ns
ns
µs
ns
µs
ns
tSU:DAT
Data In Setup Time
50
50
50
(1)
tR
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
1
1
0.3
(1)
tF
300
300
300
tSU:STO
tDH
4
4
0.6
100
100
100
(1)(2)
Power-Up Timing
Symbol
Parameter
Max.
Units
ms
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1
1
ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Write Cycle Limits
Symbol
Parameter
Min.
Typ.
Max
Units
tWR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
program/erase cycle. During the write cycle, the bus
interface circuits are disabled, SDA is allowed to remain
high, and the device does not respond to its slave
address.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1049, Rev. D
3
CAT24WC33/65
transfer all data into and out of the device. The SDA pin
is an open drain output and can be wire-ORed with other
open drain or open collector outputs.
FUNCTIONAL DESCRIPTION
The CAT24WC33/65 supports the I2C Bus data trans-
missionprotocol.ThisInter-IntegratedCircuitBusproto-
col defines any device that sends data to the bus to be
a transmitter and any device receiving data to be a
receiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC33/65
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
A0, A1, A2: Device Address Inputs
These pins are hardwired or left unconnected (for hard-
warecompatibilitywithCAT24WC16). Whenhardwired,
up to eight CAT24WC33/65s may be addressed on a
single bus system (refer to Device Addressing ). When
the pins are left unconnected, the default values are
zeros.
WP: Write Protect
This input, when tied to GND, allows write operations to
the entire memory. For CAT24WC33/65 when this pin
is tied to Vcc, the bottom 1/4 array of memory (locations
000H to 7FFH for the 24WC65 and locations 000H to
3FFHfor24WC33)iswriteprotected. Whenleftfloating,
memory is unprotected.
PIN DESCRIPTIONS
SCL: Serial Clock
The serial clock input clocks all data transferred into or
out of the device.
SDA: Serial Data/Address
The bidirectional serial data/address pin is used to
t
t
t
F
HIGH
R
Figure 1. Bus Timing
t
t
LOW
LOW
SCL
t
t
SU:STA
HD:DAT
t
t
t
t
HD:STA
SU:DAT
SU:STO
BUF
SDA IN
t
t
AA
DH
SDA OUT
5020 FHD F03
Figure 2. Write Cycle Timing
SCL
SDA
8TH BIT
BYTE n
ACK
t
WR
STOP
CONDITION
START
CONDITION
ADDRESS
5020 FHD F04
Figure 3. Start/Stop Timing
SDA
SCL
5020 FHD F05
START BIT
STOP BIT
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1049, Rev. D
4
CAT24WC33/65
I2C BUS PROTOCOL
comparetothehardwiredinputpins, A2, A1andA0. The
last bit of the slave address specifies whether a Read or
Write operation is to be performed. When this bit is set
to 1, a Read operation is selected, and when set to 0, a
Write operation is selected.
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
After the Master sends a START condition and the slave
addressbyte, theCAT24WC33/65monitorsthebusand
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC33/65 then performs a Read or Write opera-
tion depending on the state of the R/W bit.
(2) During a data transfer, the data line must remain
stablewhenevertheclocklineishigh.Anychanges
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
Acknowledge
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC33/65 monitors
the SDA and SCL lines and will not respond until this
condition is met.
Afterasuccessfuldatatransfer, eachreceivingdeviceis
requiredtogenerateanacknowledge.TheAcknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC33/65 responds with an acknowledge
afterreceivingaSTARTconditionanditsslaveaddress.
If the device has been selected along with a write
operation, it responds with an acknowledge after receiv-
ing each 8-bit byte.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determinestheSTOPcondition.Alloperationsmustend
with a STOP condition.
When the CAT24WC33/65 begins a READ mode it
transmits 8 bits of data, releases the SDA line, and
monitors the line for an acknowledge. Once it receives
this acknowledge, the CAT24WC33/65 will continue to
transmit data. If no acknowledge is sent by the Master,
the device terminates data transmission and waits for a
STOP condition. The master must then issue a stop
condition to return the CAT24WC33/65 to the standby
power mode and place the device in a known state.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 (Fig. 5). The next three bits (A2, A1, A0) are the
device address bits; up to eight 32K/64K devices may
to be connected to the same bus. These bits must
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
5020 FHD F06
Figure 5. Slave Address Bits
1
0
1
0
A2
A1
A0 R/W
5027 FHD F07
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1049, Rev. D
5
CAT24WC33/65
IftheMastertransmitsmorethan32/64bytesbeforesending
the STOP condition, the address counter ‘wraps around’,
and previously transmitted data will be overwritten.
WRITE OPERATIONS
Byte Write
In the Byte Write mode, the Master device sends the
START condition and the slave address information
(with the R/W bit set to zero) to the Slave device. After
the Slave generates an acknowledge, the Master sends
two 8-bit address words that are to be written into the
addresspointersoftheCAT24WC33/65. Afterreceiving
another acknowledge from the Slave, the Master device
transmits the data to be written into the addressed
memory location. The CAT24WC33/65 acknowledges
once more and the Master generates the STOP condi-
tion. At this time, the device begins an internal program-
ming cycle to nonvolatile memory. While the cycle is in
progress, thedevicewillnotrespondtoanyrequestfrom
the Master device.
When all 32/64 bytes are received, and the STOP condi-
tion has been sent by the Master, the internal program-
mingcyclebegins.Atthispoint,allreceiveddataiswritten
to the CAT24WC33/65 in a single write cycle.
Acknowledge Polling
Disabling of the inputs can be used to take advantage of
the typical write cycle time. Once the stop condition is
issued to indicate the end of the host's write operation,
CAT24WC33/65 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issu-
ing the start condition followed by the slave address for
a write operation. If CAT24WC33/65 is still busy with the
write operation, no ACK will be returned. If
CAT24WC33/65 has completed the write operation, an
ACK will be returned and the host can then proceed with
the next read or write operation.
Page Write
The CAT24WC33/65 writes up to 32/64 bytes of data,
in a single write cycle, using the Page Write operation.
CAT24WC33/65, Die Revision B = 32 Byte page.
CAT24WC65, Die Revision D = 64 Byte page. The page
write operation is initiated in the same manner as the
byte write operation, however instead of terminating
after the initial byte is transmitted, the Master is allowed
to send up to 31/63 additional bytes. After each byte has
been transmitted, CAT24WC33/65 will respond with
an acknowledge, and internally increment the five
low order address bits by one. The high order bits
remain unchanged.
WRITE PROTECTION
The Write Protection feature allows the user to protect
against inadvertent programming of the memory array.
If the WP pin is tied to VCC, the bottom 1/4 of the memory
array (locations 000H to 7FFH for the 24WC65 and
locations 000H to 3FFH for 24WC33) is protected and
becomes read only. The CAT24WC33/65 will accept
both slave and byte addresses, but the memory location
Figure 6. Byte Write Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
A
DATA
15
*
8
7
SDA LINE
S
P
X X X
A
C
K
A
C
K
A
C
K
A
C
K
24WC33/65 F08
Figure 7. Page Write Timing
S
T
A
R
T
S
T
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
–A A –A
0
O
P
A
DATA
DATA n
DATA n+31
15
*
8
7
SDA LINE
S
P
X X X
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
24WC33/65 F09
* = Don't care bit for 24WC33
X= Don't care bit
Doc. No. 1049, Rev. D
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
6
CAT24WC33/65
accessedisprotectedfromprogrammingbythedevice’s
failuretosendanacknowledgeafterthefirstbyteofdata
is received.
READ operation. The Master device first performs a
‘dummy’ write operation by sending the START condi-
tion, slave address and byte addresses of the location it
wishes to read. After CAT24WC33/65 acknowledges,
the Master device sends the START condition and the
slaveaddressagain,thistimewiththeR/Wbitsettoone.
The CAT24WC33/65 then responds with its acknowl-
edge and sends the 8-bit byte requested. The master
device does not send an acknowledge but will generate
a STOP condition.
READ OPERATIONS
The READ operation for the CAT24WC33/65 is initiated
in the same manner as the write operation with one
exception, that R/W bit is set to one. Three different
READ operations are possible: Immediate/Current Ad-
dress READ, Selective/Random READ and Sequential
READ.
Sequential Read
The Sequential READ operation can be initiated by
either the Immediate Address READ or Selective READ
operations.AftertheCAT24WC33/65sendstheinitial8-
bit byte requested, the Master will respond with an
acknowledge which tells the device it requires more
data. The CAT24WC33/65 will continue to output an 8-
bit byte for each acknowledge sent by the Master. The
operationwillterminatewhentheMasterfailstorespond
with an acknowledge, thus sending the STOP condition.
Immediate/Current Address Read
The CAT24WC33/65’s address counter contains the
address of the last byte accessed, incremented by one.
In other words, if the last READ or WRITE access was
to address N, the READ immediately following would
access data from address N+1. If N=E (where E=4095
for 24WC33 and E=8191 for 24WC65), then the counter
will ‘wrap around’ to address 0 and continue to clock out
data. After the CAT24WC33/65 receives its slave ad-
dress information (with the R/W bit set to one), it issues
anacknowledge,thentransmitsthe8bitbyterequested.
The master device does not send an acknowledge, but
will generate a STOP condition.
The data being transmitted from CAT24WC33/65 is
outputted sequentially with data from address N fol-
lowed by data from address N+1. The READ operation
address counter increments all of the CAT24WC33/65
addressbitssothattheentirememoryarraycanberead
during one operation. If more than E (where E=4095 for
24WC33 and E=8191 for 24WC65) bytes are read out,
the counter will ‘wrap around’ and continue to clock out
data bytes.
Selective/Random Read
Selective/Random READ operations allow the Master
device to select at random any memory location for a
Figure 8. Immediate Address Read Timing
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA
SDA LINE
S
P
A
C
K
N
O
A
C
K
SCL
SDA
8
9
8TH BIT
DATA OUT
NO ACK
STOP
24WC33/65 F10
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1049, Rev. D
7
CAT24WC33/65
Figure 9. Selective Read Timing
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
BYTE ADDRESS
SLAVE
ADDRESS
A
–A
A –A
DATA
15
8
7
0
SDA LINE
S
S
P
X X X *
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
24WC33/65 F11
* = Don't care for 24WC33
X= Don't care bit
Figure 10. Sequential Read Timing
S
T
O
P
BUS ACTIVITY:
MASTER
SLAVE
ADDRESS
DATA n
DATA n+1
DATA n+2
DATA n+x
SDA LINE
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
5020 FHD F12
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1049, Rev. D
8
CAT24WC33/65
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L)
0.245 (6.17)
0.295 (7.49)
0.300 (7.62)
0.325 (8.26)
0.355 (9.02)
0.400 (10.16)
0.120 (3.05)
0.180 (4.57) MAX
0.150 (3.81)
0.015 (0.38)
0.110 (2.79)
0.150 (3.81)
0.100 (2.54)
BSC
0.310 (7.87)
0.380 (9.65)
0.045 (1.14)
0.060 (1.52)
0.014 (0.36)
0.022 (0.56)
Notes:
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
8-LEAD 150 MIL WIDE SOIC (J, W)
0.1497 (3.80) 0.2284 (5.80)
0.1574 (4.00) 0.2440 (6.20)
0.1890 (4.80)
0.1968 (5.00)
0.0099 (0.25)
0.0196 (0.50)
X 45
0.0075 (0.19)
0.0098 (0.25)
0.0532 (1.35)
0.0688 (1.75)
0 —8
0.050 (1.27) BSC
0.013 (0.33)
0.020 (0.51)
0.0040 (0.10)
0.0098 (0.25)
0.016 (0.40)
0.050 (1.27)
Notes:
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.
2. All linear dimensions are in inches and parenthetically in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1049, Rev. D
9
CAT24WC33/65
8-LEAD 210 MIL WIDE SOIC (K, X)
0.205 (5.20)
0.213 (5.40)
0.303 (7.70)
0.318 (8.10)
0.0267 (0.68)
0.0303 (0.77)
0.205 (5.15)
0.210 (5.35)
0.008 (0.20)
0.080 (2.03)
MAX
4 REF
0.046 (1.17)
0.054 (1.37)
0.025 (0.65)
0.0137 (0.35)
0.0177 (0.45)
Note:
1. All linear dimensions are in inches and parenthetically in millimeters.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1049, Rev. D
10
CAT24WC33/65
ORDERING INFORMATION
Prefix
Device #
24WC33
Suffix
Rev D(2)
-1.8
TE13
CAT
K
I
Temperature Range
Product
Tape & Reel
Optional
Company ID
Blank = Commercial (0˚ to 70˚C)
I = Industrial (-40˚ to 85˚C)
A = Automotive (-40˚ to 105˚C*)
E = Extended (-40˚ to 125˚C)
Number
24WC33: 32K
24WC65: 64K
Die Revision
24WC33: B, D
24WC65: B, D
Operating Voltage
Blank: 2.5V - 5.5V
1.8: 1.8V - 5.5V
Package
P: PDIP
K: SOIC (EIAJ)
J: SOIC (JEDEC)
L: PDIP (Lead free, Halogen free)
X: SOIC (EIAJ, Lead free, Halogen free)
W: SOIC (JEDEC, Lead free, Halogen free)
Notes:
(1) The device used in the above example is a CAT24WC33KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt Operat-
ing Voltage, Tape & Reel)
(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWB). For additional
information, please contact your Catalyst sales office.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 1049, Rev. D
11
REVISION HISTORY
Date
Rev.
Reason
7/8/2004
B
Added die revision to Ordering Information
7/30/2004
C
D
Updated DC Operating Charactristics and notes
Update Ordering Information
10/31/2005
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Publication #: 1049
Revison:
D
Issue date:
10/31/05
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