CAT25640VP2I-GT3 [CATALYST]
64-Kb SPI Serial CMOS EEPROM; 64 kb的SPI串行EEPROM CMOS
| 型号： | CAT25640VP2I-GT3 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 64-Kb SPI Serial CMOS EEPROM |
| 文件： | 总16页 (文件大小：234K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25640
64-Kb SPI Serial CMOS EEPROM
FEATURES
DESCRIPTION
10 MHz SPI compatible
The CAT25640 is a 64-Kb Serial CMOS EEPROM
device internally organized as 8Kx8 bits. This features
a 64-byte page write buffer and supports the Serial
Peripheral Interface (SPI) protocol. The device is
1.8V to 5.5V supply voltage range
SPI modes (0,0) & (1,1)
¯¯
64-byte page write buffer
enabled through a Chip Select (CS) input. In addition,
the required bus signals are clock input (SCK), data
Self-timed write cycle
¯¯¯¯¯
input (SI) and data output (SO) lines. The HOLD input
Hardware and software protection
Block write protection
may be used to pause any serial communication with
the CAT25640 device. The device features software
and hardware write protection, including partial as
well as full array protection.
– Protect 1/4, 1/2 or entire EEPROM array
Low power CMOS technology
1,000,000 program/erase cycles
100 year data retention
Industrial temperature range
RoHS-compliant 8 lead PDIP, SOIC, TSSOP and
8-pad TDFN packages
PIN CONFIGURATION
FUNCTIONAL SYMBOL
VCC
PDIP (L)
SOIC (V)
TSSOP (Y)
TDFN (VP2)
SI
¯¯
1
2
3
4
8
7
6
5
VCC
CS
CS
SO
CAT25640
WP
HOLD
SCK
¯¯¯¯¯
HOLD
SO
¯¯¯
WP
SCK
SI
VSS
VSS
PIN FUNCTION
Pin Name
Function
¯¯
CS
Chip Select
For Ordering Information details, see page 15.
SO
Serial Data Output
Write Protect
¯¯¯
WP
VSS
SI
Ground
Serial Data Input
Serial Clock
SCK
¯¯¯¯¯
Hold Transmission Input
Power Supply
HOLD
VCC
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-1128 Rev. B
CAT25640
ABSOLUTE MAXIMUM RATINGS(1)
Parameters
Ratings
Units
ºC
Storage Temperature
Voltage on any Pin with Respect to Ground(2)
–65 to +150
–0.5 to + 6.5
V
RELIABILITY CHARACTERISTICS(3)
Symbol
Parameter
Min
1,000,000
100
Units
(4)
NEND
Endurance
Program/ Erase Cycles
Years
TDR
Data Retention
D.C. OPERATING CHARACTERISTICS
CC = +1.8V to +5.5V, TA=-40°C to +85°C unless otherwise specified.
V
Symbol Parameter
Test Conditions
Min
Max
Units
ICCR
Supply Current
(Read Mode)
2
mA
Read, VCC = 5.5V, fSCK = 10MHz,
SO open
ICCW Supply Current
(Write Mode)
3
1
3
mA
µA
µA
Write, VCC = 5.5V, fSCK = 10MHz,
SO open
ISB1
Standby Current
¯¯
¯¯¯
VIN = GND or VCC , CS = VCC , WP = VCC,
VCC = 5.5V
ISB2
Standby Current
¯¯
¯¯¯
VIN = GND or VCC , CS = VCC , WP = GND,
VCC = 5.5V
IL
Input Leakage Current
Output Leakage Current
Input Low Voltage
VIN = GND or VCC
-2
-1
2
1
µA
µA
V
¯¯
ILO
VIL
VIH
CS = VCC , VOUT = GND or VCC
-0.5
0.7VCC
0.3VCC
VCC + 0.5
0.4
Input High Voltage
V
VOL1 Output Low Voltage
VOH1 Output High Voltage
VOL2 Output Low Voltage
VOH2 Output High Voltage
V
VCC ≥ 2.5V, IOL = 3.0mA
VCC ≥ 2.5V, IOH = -1.6mA
VCC < 2.5V, IOL = 150µA
VCC < 2.5V, IOH = -100µA
V
CC - 0.8V
V
0.2
V
VCC - 0.2V
V
PIN CAPACITANCE(3)
TA = 25˚C, f = 1.0MHz, VCC = +5.0V
Symbol Test
Conditions
Min
Typ
Max
8
Units
pF
COUT
CIN
Output Capacitance (SO)
¯¯
VOUT = 0V
VIN = 0V
¯¯¯ ¯¯¯¯¯
Input Capacitance (CS, SCK, SI, WP, HOLD)
8
pF
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5V or higher than VCC + 0.5V. During transitions, the voltage on any pin may
undershoot to no less than -1.5V or overshoot to no more than VCC + 1.5V, for periods of less than 20ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5V, 25°C
Doc. No. MD-1128 Rev. B
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25640
A.C. CHARACTERISTICS
TA = -40°C to +85°C, unless otherwise specified.(1)
VCC = 1.8V-5.5V
VCC = 2.5V-5.5V
Symbol Parameter
Units
MHz
ns
Min.
DC
40
Max.
Min.
DC
20
Max.
fSCK
tSU
tH
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
5
10
40
20
ns
tWH
tWL
tLZ
80
40
ns
80
40
ns
¯¯¯¯¯
HOLD to Output Low Z
50
2
25
2
ns
(2)
tRI
Input Rise Time
Input Fall Time
µs
(2)
tFI
2
2
µs
¯¯¯¯¯
tHD
tCD
0
0
ns
HOLD Setup Time
¯¯¯¯¯
HOLD Hold Time
10
10
ns
tV
Output Valid from Clock Low
Output Hold Time
75
40
ns
tHO
0
0
ns
tDIS
tHZ
Output Disable Time
50
20
25
ns
¯¯¯¯¯
HOLD to Output High Z
100
ns
¯¯
tCS
50
50
50
10
10
15
15
15
10
10
ns
CS High Time
¯¯
tCSS
tCSH
tWPS
tWPH
ns
CS Setup Time
¯¯
ns
CS Hold Time
¯¯¯
ns
WP Setup Time
¯¯¯
WP Hold Time
ns
(4)
tWC
Write Cycle Time
5
5
ms
Power-Up Timing(2)(3)
Symbol Parameter
Max.
Units
ms
tPUR
tPUW
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
Notes:
(1) AC Test Conditions:
Input Pulse Voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤ 10ns
Input and output reference voltages: 0.5VCC
Output load: current source IOL max/IOH max; CL = 50pF
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
¯¯
(4) tWC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-1128 Rev. B
CAT25640
PIN DESCRIPTION
FUNCTIONAL DESCRIPTION
SI: The serial data input pin accepts op-codes,
addresses and data. In SPI modes (0,0) and (1,1)
input data is latched on the rising edge of the SCK
clock input.
The CAT25640 device supports the Serial Peripheral
Interface (SPI) bus protocol, modes (0,0) and (1,1). The
device contains an 8-bit instruction register. The
instruction set and associated op-codes are listed in
Table 1.
SO: The serial data output pin is used to transfer data
out of the device. In SPI modes (0,0) and (1,1) data is
shifted out on the falling edge of the SCK clock.
Reading data stored in the CAT25640 is accomplished
by simply providing the READ command and an
address. Writing to the CAT25640, in addition to a
WRITE command, address and data, also requires
enabling the device for writing by first setting certain bits
in a Status Register, as will be explained later.
SCK: The serial clock input pin accepts the clock
provided by the host and used for synchronizing
communication between host and CAT25640.
¯¯
CS: The chip select input pin is used to
¯¯
enable/disable the CAT25640. When CS is high, the
¯¯
After a high to low transition on the CS input pin, the
SO output is tri-stated (high impedance) and the
device is in Standby Mode (unless an internal write
operation is in progress). Every communication
session between host and CAT25640 must be
preceded by a high to low transition and concluded
CAT25640 will accept any one of the six instruction op-
codes listed in Table 1 and will ignore all other possible
8-bit combinations. The communication protocol follows
the timing from Figure 1.
¯¯
with a low to high transition of the CS input.
¯¯¯
WP: The write protect input pin will allow all write
Table 1: Instruction Set
¯¯¯
operations to the device when held high. When WP
Instruction
WREN
WRDI
Opcode
Operation
pin is tied low and the WPEN bit in the Status
Register (refer to Status Register description, later in
this Data Sheet) is set to “1”, writing to the Status
Register is disabled.
0000 0110 Enable Write Operations
0000 0100 Disable Write Operations
0000 0101 Read Status Register
0000 0001 Write Status Register
0000 0011 Read Data from Memory
0000 0010 Write Data to Memory
RDSR
¯¯¯¯¯
¯¯¯¯¯
HOLD: The HOLD input pin is used to pause trans–
mission between host and CAT25640, without
having to retransmit the entire sequence at a later
WRSR
READ
¯¯¯¯¯
time. To pause, HOLD must be taken low and to
WRITE
resume it must be taken back high, with the SCK
input low during both transitions. When not used for
¯¯¯¯¯
pausing, the HOLD input should be tied to VCC,
either directly or through a resistor.
Figure 1. Synchronous Data Timing
t
CS
V
IH
CS
V
IL
t
t
CSH
CSS
V
V
IH
t
t
WL
SCK
SI
WH
t
IL
t
H
SU
V
IH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
V
OH
HI-Z
HI-Z
SO
V
OL
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1128 Rev. B
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25640
STATUS REGISTER
The Status Register, as shown in Table 2, contains a
number of status and control bits.
non-volatile. The user is allowed to protect a quarter,
one half or the entire memory, by setting these bits
according to Table 3. The protected blocks then
become read-only.
¯¯¯¯
The RDY (Ready) bit indicates whether the device is
busy with a write operation. This bit is automatically
set to 1 during an internal write cycle, and reset to 0
when the device is ready to accept commands. For
the host, this bit is read only.
The WPEN (Write Protect Enable) bit acts as an
¯¯¯
enable for the WP pin. Hardware write protection is
¯¯¯
enabled when the WP pin is low and the WPEN bit
is 1. This condition prevents writing to the status
register and to the block protected sections of
memory. While hardware write protection is active,
only the non-block protected memory can be written.
The WEL (Write Enable Latch) bit is set/reset by the
WREN/WRDI commands. When set to 1, the device is
in a Write Enable state and when set to 0, the device
is in a Write Disable state.
¯¯¯
Hardware write protection is disabled when the WP
¯¯¯
pin is high or the WPEN bit is 0. The WPEN bit, WP
The BP0 and BP1 (Block Protect) bits determine
which blocks are currently write protected. They are
set by the user with the WRSR command and are
pin and WEL bit combine to either permit or inhibit
Write operations, as detailed in Table 4.
Table 2. Status Register
7
6
0
5
0
4
0
3
2
1
0
¯¯¯¯
RDY
WPEN
BP1
BP0
WEL
Table 3. Block Protection Bits
Status Register Bits
Array Address Protected
Protection
BP1
BP0
0
0
1
1
0
1
0
1
None
No Protection
1800-1FFF
1000-1FFF
0000-1FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
Table 4. Write Protect Conditions
Protected
Blocks
Unprotected
Status
Register
¯¯¯
WP
WPEN
WEL
Blocks
Protected
Writable
Protected
Writable
Protected
Writable
0
0
1
1
X
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-1128 Rev. B
CAT25640
WRITE OPERATIONS
The CAT25640 device powers up into a write disable
state. The device contains a Write Enable Latch
(WEL) which must be set before attempting to write to
the memory array or to the status register. In addition,
the address of the memory location(s) to be written
must be outside the protected area, as defined by
BP0 and BP1 bits from the status register.
instruction, as otherwise the Write Enable Latch will
not be properly set. WREN timing is illustrated in
Figure 2. The WREN instruction must be sent prior
any WRITE or WRSR instruction.
The internal write enable latch is reset by sending the
WRDI instruction as shown in Figure 3. Disabling write
operations by resetting the WEL bit, will protect the
device against inadvertent writes.
Write Enable and Write Disable
The internal Write Enable Latch and the correspon–
ding Status Register WEL bit are set by sending the
WREN instruction to the CAT25640. Care must be
¯¯
taken to take the CS input high after the WREN
Figure 2. WREN Timing
CS
SCK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 3. WRDI Timing
CS
SCK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1128 Rev. B
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25640
Byte Write
Page Write
Once the WEL bit is set, the user may execute a write
sequence, by sending a WRITE instruction, a 16-bit
address and data as shown in Figure 4. Only 13
significant address bits are used by the CAT25640.
The rest are don’t care bits, as shown in Table 5.
After sending the first data byte to the CAT25640, the
host may continue sending data, up to a total of 64
bytes, according to timing shown in Figure 5. After
each data byte, the lower order address bits are
automatically incremented, while the higher order
address bits (page address) remain unchanged. If
during this process the end of page is exceeded, then
loading will “roll over” to the first byte in the page, thus
possibly overwriting previoualy loaded data. Following
completion of the write cycle, the CAT25640 is
automatically returned to the write disable state.
¯¯
Internal programming will start after the low to high CS
transition. During an internal write cycle, all
commands, except for RDSR (Read Status Register)
¯¯¯¯
will be ignored. The RDY bit will indicate if the internal
¯¯¯¯
write cycle is in progress (RDY high), or the the
¯¯¯¯
device is ready to accept commands (RDY low).
Table 5. Byte Address
Device
Address Significant Bits
Address Don't Care Bits
# Address Clock Pulses
CAT25640
A12 - A0
A15 - A13
16
Figure 4. Byte WRITE Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SCK
SI
OPCODE
BYTE ADDRESS*
DATA IN
A
A
0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
N
HIGH IMPEDANCE
SO
* Please check the Byte Address Table (Table 5)
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 5. Page WRITE Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SCK
SI
DATA IN
Data Data
Byte 2 Byte 3
BYTE ADDRESS*
OPCODE
Data
Data Byte N
0
0
0
0
0
0
1
0
A
A
0
0
Byte 1
N
7..1
HIGH IMPEDANCE
SO
*Please check the Byte Address Table. (Table 5)
Note: Dashed Line = mode (1, 1) - - - - - -
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-1128 Rev. B
CAT25640
Write Protection
Write Status Register
¯¯¯
The Write Protect (WP) pin can be used to protect the
The Status Register is written by sending a WRSR
instruction according to timing shown in Figure 6. Only
bits 2, 3 and 7 can be written using the WRSR
command.
Block Protect bits BP0 and BP1 against being
inadvertently altered. When WP is low and the WPEN
bit is set to “1”, write operations to the Status Register
are inhibited. WP going low while CS is still low will
¯¯¯
¯¯¯
¯¯
interrupt a write to the status register. If the internal
¯¯¯
write cycle has already been initiated, WP going low
will have no effect on any write operation to the Status
¯¯¯
Register. The WP pin function is blocked when the
¯¯¯
WPEN bit is set to “0”. The WP input timing is shown
in Figure 7.
Figure 6. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line = mode (1, 1) - - - - - -
¯¯¯
Figure 7. WP Timing
t
t
WPH
WPS
CS
SCK
WP
WP
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1128 Rev. B
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25640
READ OPERATIONS
Read Status Register
Read from Memory Array
To read the status register, the host simply sends a
RDSR command. After receiving the last bit of the
command, the CAT25640 will shift out the contents of
the status register on the SO pin (Figure 9). The
status register may be read at any time, including
during an internal write cycle.
To read from memory, the host sends a READ
instruction followed by a 16-bit address (see Table 5 for
the number of significant address bits).
After receiving the last address bit, the CAT25640 will
respond by shifting out data on the SO pin (as shown
in Figure 8). Sequentially stored data can be read out
by simply continuing to run the clock. The internal
address pointer is automatically incremented to the
next higher address as data is shifted out. After
reaching the highest memory address, the address
counter “rolls over” to the lowest memory address,
and the read cycle can be continued indefinitely. The
¯¯
read operation is terminated by taking CS high.
Figure 8. READ Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SCK
OPCODE
BYTE ADDRESS*
A
A
0
SI
0
0
0
0
0
0
1
1
N
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
* Please check the Byte Address Table (Table 5).
Note: Dashed Line = mode (1, 1) - - - - - -
Figure 9. RDSR Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line = mode (1, 1) - - - - - -
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. MD-1128 Rev. B
CAT25640
The CAT25640 device powers up in a write disable
state and in a low power standby mode. A WREN
instruction must be issued prior any writes to the
device.
Hold Operation
¯¯¯¯¯
The HOLD input can be used to pause communication
between host and CAT25640. To pause, HOLD must
be taken low while SCK is low (Figure 10). During the
¯¯¯¯¯
¯¯
hold condition the device must remain selected (CS
¯¯
After power up, the CS pin must be brought low to
low). During the pause, the data output pin (SO) is tri-
stated (high impedance) and SI transitions are
ignored. To resume communication, HOLD must be
enter a ready state and receive an instruction. After a
successful byte/page write or status register write, the
device goes into a write disable mode. The CS input
must be set high after the proper number of clock
cycles to start the internal write cycle. Access to the
memory array during an internal write cycle is ignored
and programming is continued. Any invalid op-code
will be ignored and the serial output pin (SO) will
remain in the high impedance state.
¯¯¯¯¯
¯¯
taken high while SCK is low.
DESIGN CONSIDERATIONS
The CAT25640 device incorporates Power-On Reset
(POR) circuitry which protects the internal logic
against powering up in the wrong state. The device
will power up into Standby mode after VCC exceeds
the POR trigger level and will power down into Reset
mode when VCC drops below the POR trigger level.
This bi-directional POR behavior protects the device
against ‘brown-out’ failure following a temporary loss
of power.
¯¯¯¯¯
Figure 10. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
t
HZ
HIGH IMPEDANCE
SO
t
LZ
Note: Dashed Line = mode (1, 1) - - - - - -
Doc. No. MD-1128 Rev. B
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25640
PACKAGE OUTLINES
PDIP 8-Lead 300mils (L)
SYMBOL
MIN
NOM
MAX
A
A1
A2
b
5.33
0.38
2.92
0.36
1.14
0.20
9.02
7.62
3.30
0.46
4.95
0.56
1.78
0.36
10.16
8.25
b2
c
1.52
E1
0.25
D
9.27
E
7.87
e
2.54 BSC
6.35
E1
eB
L
6.10
7.87
2.92
7.11
10.92
3.80
PIN # 1
IDENTIFICATION
3.30
D
TOP VIEW
E
A2
A1
A
L
c
b2
eB
e
b
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-1128 Rev. B
CAT25640
SOIC 8-Lead 150mils (V)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
4.80
5.80
3.80
c
E1
E
D
E
E1
e
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
PIN # 1
IDENTIFICATION
θ
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC specification MS-012.
Doc. No. MD-1128 Rev. B
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25640
TSSOP 8-Lead 4.4mm (Y)
b
SYMBOL
MIN
NOM
MAX
1.20
0.15
1.05
0.30
0.20
3.10
6.50
4.50
A
A1
A2
b
0.05
0.80
0.19
0.09
2.90
6.30
4.30
0.90
c
D
3.00
6.40
E
E1
E
E1
e
4.40
0.65 BSC
1.00 REF
0.60
L
L1
θ1
0.50
0°
0.75
8°
e
TOP VIEW
D
c
A2
A1
A
θ1
L1
L
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC Standard MO-153
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
13
Doc. No. MD-1128 Rev. B
CAT25640
TDFN 8-Pad 2 x 3mm (VP2)
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
SYMBOL
MIN
0.70
0.00
0.45
NOM
0.75
0.02
0.55
MAX
0.80
0.05
0.65
A2
A
A1
A2
A3
b
A3
0.20 REF
0.25
FRONT VIEW
0.20
1.90
1.30
2.90
1.20
0.30
2.10
1.50
3.10
1.40
D
2.00
D2
E
1.40
3.00
E2
e
1.30
050TYP
0.30
L
0.20
0.40
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC Standard MO-229.
Doc. No. MD-1128 Rev. B
14
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT25640
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
25640
V
I
-G
T3
Package
L: PDIP
V:SOIC, JEDEC
Y: TSSOP
Temperature Range
I = Industrial (-40ºC to 85ºC)
Lead Finish
Blank: Matte-Tin
G: NiPdAu
Company ID
Product Number
25640
VP2:TDFN (2 x 3mm)
Tape & Reel
T: Tape & Reel
3: 3000 units/Reel
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu.
(3) The device used in the above example is a CAT25640VI-GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
15
Doc. No. MD-1128 Rev. B
REVISION HISTORY
Date
Rev. Comments
Initial Issue
5/18/07
10/01/07
A
B
Update Absolute Maximum Ratings table
Update all Package Outline Drawings
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Adaptive Analog™, Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, Quad-Mode™ and Quantum Charge Programmable™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal
injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: MD-1128
Revision:
B
Issue date:
10/01/07
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