CAT25C082S16I-45 [CATALYST]
EEPROM, 1KX8, Serial, CMOS, PDSO16;
| 型号： | CAT25C082S16I-45 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 1KX8, Serial, CMOS, PDSO16 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advanced
CAT25CXXX
Supervisory Circuits with SPI Serial E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
■ Watchdog Timer on CS
■ 10 MHz SPI Compatible
■ 1,000,000 Program/Erase Cycles
■ 1.8 to 6.0 Volt Operation
■ 100 Year Data Retention
■ Hardware and Software Protection
■ Self-Timed Write Cycle
■ Zero Standby Current
■ 8-Pin DIP/SOIC, 16-Pin SOIC and 14-Pin TSSOP
■ Low Power CMOS Technology
■ Page Write Buffer
■ SPI Modes (0,0 &1,1)
■ Block Write Protection
■ Commercial, Industrial and Automotive
– Protect 1/4, 1/2 or all of E2PROM Array
Temperature Ranges
■ Programmable Watchdog Timer
■ Active High or Low Reset Outputs
■ Built-in inadvertent Write Protection
– Precision Power Supply Voltage Monitoring
– 5V, 3.3V, 3V and 1.8V Options
– VCC Lock Out
DESCRIPTION
The CAT25CXXX is a single chip solution to three
popular functions of EEPROM Memory, precision reset
controllerandwatchdogtimer.TheEEPROMMemoryis
a 2K/4K/8K/16K/32K-Bit SPI Serial CMOS E2PROM
internally organized as 256x8/512x8/1024x8/2048x8/
4096x8 bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
2K/4K devices feature a 16-byte page write buffer. The
8K/16K/32K devices feature a 32-byte page write
buffer.The device operates via the SPI bus serial inter-
face and is enabled though a Chip Select (CS). In
addition to the Chip Select, the clock input (SCK), data
in (SI) and data out (SO) are required to access the
device. The reset function of the 25CXXX protects the
system during brown out and power up/down condtions.
During system failure the watchdog timer feature pro-
tects the microcontroller with a reset signal. The
CAT25CXXX is designed with software and hardware
write protection features including Block Lock protec-
tion.Thedeviceisavailablein8-pinDIP,8-pinSOIC,16-
pin SOIC and 14-pin TSSOP packages.
PIN CONFIGURATION
DIP Package (P)
SOIC Package (S16)
TSSOP Package (U14)
SOIC Package (S)
16
1
2
3
4
5
6
7
8
VCC
CS
SO
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
14
13
12
11
10
9
8
1
2
3
4
5
6
7
VCC
RESET/RESET
NC
NC
NC
SCK
SI
V
V
CC
RESET/RESET
CS
SO
NC
NC
NC
WP
CS
SO
WP
CS
SO
CC
RESET/RESET
15
14
13
12
11
10
9
RESET/RESET
NC
NC
NC
NC
WP
VSS
NC
NC
NC
NC
SCK
SI
WP
SCK
SI
SCK
SI
V
SS
V
SS
V
SS
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9-95
CAT25CXXX
Advanced
PIN FUNCTIONS
BLOCK DIAGRAM
SENSE AMPS
SHIFT REGISTERS
Pin Name
SO
Function
Serial Data Output
Serial Clock
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
SCK
WP
Write Protect
SO
SI
V
+1.8V to +6.0V Power Supply
Ground
I/O
CONTROL
CC
V
SS
E2PROM
ARRAY
CS
SPI
CONTROL
LOGIC
XDEC
CS
Chip Select
WP
SI
Serial Data Input
SCK
RESET/RESET Reset I/O
NC No Connect
BLOCK
PROTECT
LOGIC
DATA IN
STORAGE
HIGH VOLTAGE/
TIMING CONTROL
STATUS
REGISTER
Reset Controller
High Precision
CC
RESET/RESET
Watchdog
V
Monitor
25CXXX F02.1
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
(1)(2)
Power-Up Timing
Symbol
tPUR
Parameter
Max.
Units
ms
Power-up to Read Operation
Power-up to Write Operation
1
1
tPUW
ms
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
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Advanced
CAT25CXXX
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
D.C. OPERATING CHARACTERISTICS
V
= +1.8V to +6.0V, unless otherwise specified.
CC
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
5
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
ISB
Power Supply Current
(Operating Read)
0.4
0
mA
VCC = 5.5V
FCLK = 5MHz
Power Supply Current
(Standby)
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(3)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(3)
VIH
VCC x 0.7
4.5V≤V <5.5V
VOL1
VOH1
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
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CAT25CXXX
Advanced
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
A.C. CHARACTERISTICS
Limits
1.8, 2.5
4.5V-5.5V
Test
SYMBOL PARAMETER
Min.
50
Max.
Min.
Max.
UNITS Conditions
tSU
tH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
10
20
40
40
DC
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
50
tWH
tWL
fSCK
tLZ
200
200
DC
2
50
2
10
50
2
HOLD to Output Low Z
Input Rise Time
(1)
tRI
CL = 50pF
(1)
tFI
Input Fall Time
2
2
tHD
HOLD Setup Time
HOLD HOLD Time
Write Cycle Time
Output Valid from Clock Low
Output HOLD Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
40
40
tCD
tWC
tV
10
5
200
80
tHO
tDIS
tHZ
0
0
250
100
75
50
tCS
250
250
250
100
100
100
tCSS
tCSH
NOTE:
CS Setup Time
CS HOLD Time
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Stock No. 21085-01 4/98
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Advanced
CAT25CXXX
FUNCTIONAL DESCRIPTION
RESET/RESET: RESET I/O
These are open drain pins and can be used as reset
triggerinputs. Byforcingaresetconditiononthepinsthe
device will initiate and maintain a reset condition. RE-
SET pin must be connected through a pull-down and
RESET pin must be connected through a pull-up device.
The CAT25CXXX supports the SPI bus data transmis-
sion protocol. The synchronous Serial Peripheral Inter-
face (SPI) helps the CAT25CXXX to interface directly
with many of today’s popular microcontrollers. The
CAT25CXXXcontainsan8-bitinstructionregister. (The
instruction set and the operation codes are detailed in
the instruction set table)
CS: Chip Select
CSistheChipselectpin.CSlowenablestheCAT25CXXX
and CS high disables the CAT25CXXX. CS high takes
the SO output pin to high impedance and forces the
devices into a Standby Mode (unless an internal write
operation is underway) The CAT25CXXX draws ZERO
current in the Standby mode. A high to low transition on
CS is required prior to any sequence being initiated. A
low to high transition on CS after a valid write sequence
is what initiates an internal write cycle.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25CXXX. Input data is latched on the rising edge of the
serial clock.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0.
SO: Serial Output
SO is the serial data output pin. This pin is used to
transfer data out of the 25CXXX. During a read cycle,
data is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25CXXX. Opcodes, byte addresses, or data
presentontheSIpinarelatchedontherisingedgeofthe
SCK. Data on the SO pin is updated on the falling edge
of the SCK.
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 X011
0000 X010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
(1)
(1)
WRITE
Note:
(1) X=O for 25C02X/08X/16X/32X. X=A8 for 25C04X
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
WD1
WD0
BP1
BP0
WEL
RDY
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9-99
CAT25CXXX
Advanced
Status Register
The Status Register indicates the status of the device.
TheRDY(Ready)bitindicateswhethertheCAT25CXXX
isbusywithawriteoperation. Whensetto1awritecycle
is in progress and when set to 0 the device indicates it is
ready. This bit is read only.The WEL (Write Enable) bit
indicates the status of the write enable latch . When set
to 1, the device is in a Write Enable state and when set
to 0 the device is in a Write Disable state. The WEL bit
can only be set by the WREN instruction and can be
reset by the WRDI instruction.
TheWPEN(WriteProtectEnable)isanenablebitforthe
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
to the status register, (including the block protect bits
and the WPEN bit) and the block protected sections in
the memory array when the chip is hardware write
protected. Only the sections of the memory array that
are not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
The BPO and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
userissuingtheWRSRinstruction.Theuserisallowedto
protect quarter of the memory, half of the memory or the
entire memory by setting these bits. Once protectedthe
user may only read from the protected portion of the
array. These bits are non-volatile.
The watchdog timer bits, WD0 and WD1, select the
watchdog time-out period. These nonvolatile bits are
programmed with the WRSR instruction.
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
Protection
BP1
BPO
0
0
0
1
None
No Protection
25C02X: C0-FF
25C04X: 180-1FF
25C08X: 0300-03FF
25C16X: 0600-07FF
25C32X: 0C00-0FFF
Quarter Array Protection
1
1
0
1
25C02X: 80-FF
25C04X: 100-1FF
25C08X: 0200-03FF
25C16X: 0400-07FF
25C32X: 0800-0FFF
Half Array Protection
Full Array Protection
25C02X: 00-FF
25C04X: 000-1FF
25C08X: 0000-03FF
25C16X: 0000-07FF
25C32X: 0000-0FFF
WATCHDOG TIMER BITS
WD1
WD0
Watchdog Timer Time-Out (Typical)
1.4 Seconds
0
0
1
1
0
1
0
1
600 Milliseconds
200 Milliseconds
Disabled
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9-100
Advanced
CAT25CXXX
after each byte of data is shifted out. When the highest
address is reached, the address counter rolls over to
0000H allowing the read cycle to be continued indefi-
nitely.ThereadoperationisterminatedbypullingtheCS
high. To read the status register, RDSR instruction
should be sent. The contents of the status register are
shifted out on the SO line. The status register may be
read at any time even during a write cycle. Read
sequeceisillustratedinFigure4. Readingstatusregister
is illustrated in Figure 5.
DEVICE OPERATION FOR THE MEMORY
FUNCTION
Write Enable and Disable
The CAT25CXXX contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
WRITE Sequence
READ Sequence
The CAT25CXXX powers up in a Write Disable state.
Prior to any write instructions, the WREN instruction
must be sent to CAT25CXXX. The device goes into
w rite enable state by pulling the CS low and then
clocking the WREN instruction into CAT25CXXX. The
CS must be brought high after the WREN instruction to
enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25CXXX, followed
by the 16-bit address for 25C08X/16X/32X (only 10-bit
addresses are used for 25C08X, 11-bit addresses are
used for 25C16X, and 12-bit addresses are used for
25C32X. The rest of the bits are don't care bits) and 8-
bit address for 25C02X/04X (for the 25C04X, bit 3 of the
read data instruction contains address A8).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
Register
WPEN
WP
WEL
0
X
0
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
0
1
1
X
X
X
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Low
Low
High
High
Protected
Protected
Protected
Writable
Figure 2. WREN Instruction Timing
SK
CS
1
1
0
SI
0
0
0
0
0
HIGH-Z
SO
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9-101
CAT25CXXX
Advanced
Byte Write
Page Write
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address for 25C08X/16X/32X (only 10-bit ad-
dresses are used for 25C08X, 11-bit addresses are
used for 25C16X, and 12-bit addresses are used for
25C32X. The rest of the bits are don't care bits) and 8-
bit address for 25C02X/04X (for the 25C04X, bit 3 of the
read data instruction contains address A8). Program-
ming will start after the CS is brought high. The low to
high transition of the CS pin must occur during the SCK
low time, immediately after clocking the least significant
bit of the data. Figure 6 illustrates byte write sequence.
The CAT25CXXX features page write capability. After
the initial byte, the host may continue to write up to 16
bytes of data to the CAT25C02X/04X and 32 bytes of
data for 25C08X/16X/32X. After each byte of data
received, lower order address bits are internally
incremented by one; the high order bits of address will
remain constant.The only restriction is that the X (X=16
for 25C02X/04X and X=32 for 25C08X/16X/32X) bytes
must reside on the same page. If the address counter
reaches the end of the page and clock continues, the
counter will “roll over” to the first address of the page
and overwrite any data that may have been written. The
CAT25CXXX is automatically returned to the write dis-
able state at the completion of the write cycle. Figure 8
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) in-
struction.
illustrates
the
page
write
sequence.
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
The Status Register can be read to determine if the write
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction.
Figure 3. WRDI Instruction Timing
SK
CS
0
SI
0
0
0
0
1
0
0
HIGH-Z
SO
25C128 F05
Figure 4. Read Instruction Timing
RESET
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
CS
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
SO
7
6
5
4
3
2
1
0
*Please check the instruction set table for address
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Advanced
CAT25CXXX
Figure 5. RDSR Timing
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SCK
SI
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
25C128 F09
Figure 6. Write Instruction Timing
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
CS
D7 D6 D5 D4 D3 D2 D1 D0
SI
0
0
0
0
0
0
1
0
ADDRESS
SO
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
8
7
9
6
10
5
11
12
13
2
14
1
SCK
DATA IN
3
INSTRUCTION
4
0
SI
SO
25C128 F08
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CAT25CXXX
Advanced
time out period (the time out period is defined by the
watchdog timer bits WD0 an d WD1) for lack of activity.
25CXXX is designed with the Watchdog Timer feature
on the CS input. For the 25CXXX, if the microcontroller
does not toggle the CS pin within the time out period the
Watchdog Timer times out. This will generate a reset
condition on reset outputs. The Watchdog Timer is
cleared by any transition on CS.
DEVICE OPERATION FOR THE
SUPERVISORY CIRCUIT
Reset Controller Description
The CAT25CXXX provides a precision RESET control-
ler that ensures correct system operation during brown-
out and power-up/down conditions. It is configured
with open drain RESET outputs. During power-up, the
RESET outputs remain active until VCC reaches the
VTH threshold and will continue driving the outputs for
approximately 200ms (tPURST) after reaching VTH. After
the tPURST timeout interval, the device will cease to drive
reset outputs. At this point the reset outputs will be
pulled up or down by their respective pull up/pull down
devices. During power-down, the RESET outputs will
begin driving active when VCC falls below VTH. The
RESET outputs will be valid so long as VCC is >1.0V
(VRVALID).
As long as the reset signal is asserted, the Watchdog
Timer will not count and will stay cleared.
Reset Threshold Voltage
From the factory the 25CXXX is offered in six different
variations of reset threshold voltages. They are 4.50-
4.75V,4.25-4.50V,3.00-3.15V,2.85-3.00V,2.55-2.70V
and 1.7-1.8V. To provide added flexibility to design
engineers using this product, the 25CXXX is designed
with an additional feature of programming the reset
threshold voltage. This allows the user to change the
existing reset threshold voltage to one of the other five
reset threshold voltages. Once the reset threshold
voltage is selected it will not change even after cycling
the power, unless the user uses the programmer to
change the reset threshold voltage. However, the
programming function is available only through third
party programmer manufacturers. Please call Catalyst
for a list of programmer manufacturers who support this
function.
The RESET pins are I/Os; therefore, the CAT25CXXX
can act as a signal conditioning circuit for an externally
applied reset. The inputs are level triggered; that is, the
RESET input in the 25CXXX will initiate a reset timeout
after detecting a high and the RESET input in the
25CXXXwillinitiatearesettimeoutafterdetectingalow.
Watchdog Timer
The Watchdog Timer provides an independent protec-
tion for microcontrollers. During a system failure, the
CAT25CXXX will respond with a reset signal after a
Figure 8. Page Write Instruction Timing
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
CS
Data
Byte 1
Data
Byte 2 Byte 3
Data
Data
Byte N
SI
0
0
0
0
0
0
1
0
ADDRESS
SO
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Advanced
CAT25CXXX
RESET CIRCUIT CHARACTERISTICS
Symbol
tGLITCH
VRT
Parameter
Min.
Max. Units
Glitch Reject Pulse Width
Reset Threshold Hystersis
Reset Output Low Voltage (IOLRS=1mA)
Reset Output High Voltage
100
ns
mV
V
15
VOLRS
VOHRS
0.4
Vcc-0.75
4.50
V
Reset Threshold (Vcc=5V)
(25CXXX-45)
4.75
Reset Threshold (Vcc=5V)
(25CXXX-42)
4.25
3.00
4.50
3.15
V
Reset Threshold (Vcc=3.3V)
(25CXXX-30)
VTH
Reset Threshold (Vcc=3.3V)
(25CXXX-28)
2.85
2.55
1.70
3.00
2.70
1.80
Reset Threshold (Vcc=3V)
(25CXXX-25)
Reset Threshold (Vcc=1.8V)
(25CXXX-17)
t
PURST
Power-Up Reset Timeout
VTH to RESET Output Delay
RESET Output Valid
130
1
270
5
ms
µs
V
t
RPD
VRVALID
Figure 9. RESET Output Timing
t
GLITCH
V
TH
V
RVALID
V
CC
t
RPD
t
t
PURST
PURST
RESET
t
RPD
RESET
Stock No. 21085-01 4/98
9-105
CAT25CXXX
Advanced
DESIGN CONSIDERATIONS
TheCAT25CXXX powersupinawritedisablestateand
in a low power standby mode. A WREN instruction must
beissuedtoperformanywritestothedeviceafterpower
up. Also,on power up CS should be brought low to enter
a ready state and receive an instruction. After a suc-
cessful byte/page write or status register write the
CAT25CXXX goes into a write disable mode. CS must
be set high after the proper number of clock cycles to
start an internal write cycle. Access to the array during
an internal write cycle is ignored and programming is
continued. On power up,SO is in a high impedance. If
an invalid op code is received, no data will be shifted into
the CAT25CXXX, and the serial output pin (SO) will
remain in a high impedance state until the falling edge
of CS is detected again.
The VCC sense provides write protection when VCC falls
below the reset threshold value (VTH). The VCC lock out
inhibits writes to the serial EEPROM whenever VCC falls
below (power down) VTH or until VCC reaches the reset
threshold (power up) VTH
.
ORDERING INFORMATION
Prefix
Device #
Suffix
25C16
-30
CAT
TE13
1
I
S
Optional
Temperature Range
Tape & Reel
Product
Number
RESET
Company ID
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
TE13: 2000/Reel
1. RESET
2. RESET
25C32: 32K
A = Automotive (-40˚ to +105˚C)*
25C16:16K
25C08: 8K
25C04: 4K
25C02: 2K
ResetThreshold
Voltage
Package
P = PDIP
45: 4.5-4.75V
42: 4.25-4.5V
30: 3.0-3.15V
28: 2.85-3.0V
25: 2.55-2.7V
17: 1.7-1.8V
S = 8-pin SOIC
S16 = 16-pin SOIC
U14 = 14-pin TSSOP
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 25C161SI-30TE13 (RESET, SOIC, Industrial Temperature, 3.0-3.15 Reset Threshold
Voltage, Tape & Reel)
Stock No. 21085-01 4/98
9-106
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