CAT25C128VA-GT2 [CATALYST]
128K/256K-Bit SPI Serial CMOS EEPROM; 128K / 256K位的SPI串行EEPROM CMOS
| 型号： | CAT25C128VA-GT2 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 128K/256K-Bit SPI Serial CMOS EEPROM |
| 文件： | 总12页 (文件大小：444K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25C128/256
128K/256K-Bit SPI Serial CMOS EEPROM
FEATURES
I Self-Timed Write Cycle
I 64-Byte Page Write Buffer
I Block Write Protection
I 5 MHz SPI Compatible
I 1.8 to 5.5 Volt Operation
I Hardware and Software Protection
I Low Power CMOS Technology
I SPI Modes (0,0 &1,1)
– Protect 1/4, 1/2 or all of EEPROM Array
I 100,000 Program/Erase Cycles
I 100 Year Data Retention
I Industrial and Automotive
I RoHS-compliant packages
Temperature Ranges
DESCRIPTION
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS EEPROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology
substantially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface
and is enabled through a Chip Select (CS). In addition
to the Chip Select, the clock input (SCK), data in (SI)
and data out (SO) are required to access the device.
The HOLD pin may be used to suspend any serial
communication without resetting the serial sequence.
The CAT25C128/256 is designed with software and
hardware write protection features including Block Lock
protection. The device is available in 8-pin DIP, 8-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
PIN CONFIGURATION
BLOCK DIAGRAM
TSSOP Package (Y14)**
SOIC Package
1
2
3
4
5
6
7
14
13
12
11
10
9
CS
(V**, X)
V
SENSE AMPS
SHIFT REGISTERS
CC
SO
NC
NC
NC
WP
HOLD
NC
NC
NC
SCK
SI
1
2
3
4
8
7
6
5
V
CS
SO
WP
CC
HOLD
SCK
SI
COLUMN
DECODERS
WORD ADDRESS
BUFFERS
V
SS
V
8
SS
TSSOP Package (Y20)**
DIP Package (L)
SO
SI
I/O
CONTROL
1
2
3
4
5
6
20
19
18
17
16
NC
CS
NC
1
2
3
4
8
7
6
5
V
CS
SO
CC
V
CC
CS
EEPROM
ARRAY
HOLD
SCK
SI
SPI
CONTROL
LOGIC
XDEC
HOLD
HOLD
NC
SO
SO
NC
NC
WP
WP
WP
SS
HOLD
SCK
15
14
13
12
11
NC
SCK
7
**CAT25C128 only.
BLOCK
PROTECT
LOGIC
V
SI
NC
NC
8
SS
NC
NC
9
10
DATA IN
STORAGE
PIN FUNCTIONS
Pin Name
SO
Function
Serial data Output
Serial Clock
Write Protect
Power Supply
Ground
HIGH VOLTAGE/
TIMING CONTROL
SCK
WP
VCC
STATUS
REGISTER
VSS
CS
Chip Select
SI
HOLD
NC
Serial Data Input
Suspends Serial Input
No Connect
For Ordering Information details, see page 11.
© 2005 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 1018, Rev. I
1
CAT25C128/256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
thoselistedintheoperationalsectionsofthisspecification
isnotimplied.Exposuretoanyabsolutemaximumrating
for extended periods may affect device performance
and reliability.
Voltage on any Pin with
Respect to VSS1) ................... –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100,000
100
Max.
Units
Cycles/Byte
Years
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
100
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +5.5V, unless otherwise specified.
V
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
10
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
Power Supply Current
(Operating Read)
2
mA
VCC = 5.0V
FCLK = 5MHz
(5)
ISB
Power Supply Current
(Standby)
1
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(3)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(3)
VIH
VCC x 0.7
4.5V≤V <5.5V
VOL1
VOH1
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
VCC-0.2
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100 and
JEDEC test methods.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.
SB
Document No. 1018, Rev. I
2
CAT25C128/256
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Max.
Units
pF
Conditions
Output Capacitance (SO)
8
6
VOUT=0V
VIN=0V
Input Capacitance (CS, SCK, SI, WP, HOLD)
pF
A.C. CHARACTERISTICS (CAT25C128)
SYMBOL PARAMETER
Limits
Vcc=
1.8V-5.5V
VCC
2.5V-5.5V
=
VCC
4.5V-5.5V
Max. Min. Max. UNITS Conditions
=
Test
Min. Max. Min.
tSU
tH
Data Setup Time
Data Hold Time
100
100
250
250
DC
70
70
35
35
80
80
DC
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
150
150
DC
ns
SCK Low Time
ns
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
3
50
2
5
50
2
MHz
ns
(1)
tRI
µs
µs
ns
(1)
tFI
Input Fall Time
2
2
2
CL = 50pF
tHD
tCD
tWC
tV
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
250
250
250
250
40
40
ns
10
10
5
ms
ns
250
250
80
tHO
tDIS
tHZ
tCS
tCSS
0
0
0
ns
250
150
250
150
100
50
ns
ns
1000
1000
250
250
200
100
ns
CS Setup Time
ns
tCSH
tWPS
tWPH
CS Hold Time
WP Setup Time
WP Hold Time
500
50
50
250
50
50
100
50
50
ns
ns
ns
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 1018, Rev. I
3
CAT25C128/256
A.C. CHARACTERISTICS (CAT25C256)
Limits
Vcc=
1.8V-5.5V
Min. Max. Min. Max. Min. Max. Min. Max. UNITS Conditions
VCC
2.5V-5.5V
=
VCC
=
VCC=
2.7V-5.5V 4.5V-5.5V
Test
SYMBOL PARAMETER
tSU
tH
Data Setup Time
Data Hold Time
500
500
100
100
250
250
DC
70
70
35
ns
ns
35
tWH
tWL
fSCK
tLZ
SCK High Time
2500
2500
DC
150
150
2.0 DC
50
80
ns
SCK Low Time
80
ns
Clock Frequency
HOLD to Output Low Z
Input Rise Time
0.2
100
2
2.5 DC
5
50
2
MHz
ns
50
2
(3)
tRI
2
µs
µs
ns
(3)
tFI
Input Fall Time
2
2
2
2
CL = 50pF
tHD
tCD
tWC
tV
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
250
250
100
100
100
100
10
40
40
ns
10
10
5
ms
ns
250
200
0
200
0
80
tHO
tDIS
tHZ
tCS
tCSS
0
0
ns
250
150
200
100
100
100
200
100
100
100
100
50
ns
ns
100
100
100
100
ns
CS Setup Time
ns
tCSH
tWPS
tWPH
CS Hold Time
WP Setup Time
WP Hold Time
100
50
50
100
50
50
100
50
50
100
50
50
ns
ns
ns
NOTE:
(3) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 1018, Rev. I
4
CAT25C128/256
SO: Serial Output
FUNCTIONAL DESCRIPTION
SO is the serial data output pin. This pin is used to transfer
dataoutoftheCAT25C128/256. Duringareadcycle, data
is shifted out on the falling edge of the serial clock.
The CAT25C128/256 supports the SPI bus data
transmissionprotocol.ThesynchronousSerialPeripheral
Interface (SPI) helps the CAT25C128/256 to interface
directly with many of today’s popular microcontrollers.
The CAT25C128/256 contains an 8-bit instruction
register. (The instruction set and the operation codes
are detailed in the instruction set table)
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchronize
the communication between the microcontroller and the
CAT25C128/256. Opcodes, byte addresses, or data
present on the SI pin are latched on the rising edge of the
SCK. Data on the SO pin is updated on the falling edge of
the SCK.
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
CS: Chip Select
CSistheChipselectpin.CSlowenablestheCAT25C128/
256 and CS high disables the CAT25C128/256. CS high
takes the SO output pin to high impedance and forces the
devices into a Standby Mode (unless an internal write
operation is underway). The CAT25C128/256 draws
ZEROcurrentintheStandbymode.Ahightolow transition
on CS is required prior to any sequence being initiated. A
low to high transition on CS after a valid write sequence is
what initiates an internal write cycle.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C32/64. Input data is latched on the rising edge of the
serial clock.
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
H
t
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) — — — —
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
WRITE
Document No. 1018, Rev. I
5
CAT25C128/256
WP: Write Protect
9 illustrates hold timing sequence.
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0.
STATUS REGISTER
The Status Register indicates the status of the device.
TheRDY(Ready)bitindicateswhethertheCAT25C128/
256 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
writeenablelatch. Whensetto1, thedeviceisinaWrite
Enable state and when set to 0 the device is in a Write
Disablestate. TheWELbitcanonlybesetbytheWREN
instruction and can be reset by the WRDI instruction.
HOLD: Hold
The HOLD pin is used to pause transmission to the
CAT25C128/256 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK is
low. The SO pin is in a high impedance state during the
time the part is paused, and transitions on the SI pins will
be ignored. To resume communication, HOLD is brought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor. Figure
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
Protection
BP1
0
BP0
0
None
No Protection
0
1
25C128: 3000-3FFF
25C256: 6000-7FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
1
1
0
1
25C128: 2000-3FFF
25C256: 4000-7FFF
25C128: 0000-3FFF
25C256: 0000-7FFF
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
WPEN
WP
X
WEL
Register
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
Document No. 1018, Rev. I
6
CAT25C128/256
TheWPEN(WriteProtectEnable)isanenablebitforthe
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
tothestatusregister(includingtheblockprotectbitsand
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write pro-
tected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instructionistransmittedtotheCAT25C128/256,followed
by the 16-bit address(the three Most Significant Bit is
don’t care for 25C256 and four most significant bits are
don't care for 25C128).
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
atthenextaddresscanbereadsequentiallybycontinuing
to provide clock pulses. The internal address pointer is
automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address (7FFFh for 25C256 and 3FFFh for 25C128) is
reached,theaddresscounterrollsoverto0000hallowing
the read cycle to be continued indefinitely. The
readoperation is terminated by pulling the CS high.
DEVICE OPERATION
Write Enable and Disable
TheCAT25C128/256containsawriteenablelatch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WRENinstructionwillenable writes(setthelatch)tothe
device. WRDI instruction will disable writes (reset the
Figure 2. WREN Instruction Timing
CS
SK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Figure 3. WRDI Instruction Timing
CS
SK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Document No. 1018, Rev. I
7
CAT25C128/256
To read the status register, RDSR instruction should be
sent. The contents of the status register are shifted out
on the SO line. The status register may be read at any
time even during a write cycle. Read sequece is illus-
trated in Figure 4. Reading status register is illustrated in
Figure 5.
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Byte Write
WRITE Sequence
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address (the three Most Significant Bits are don’t
care for 25C256 and four most significant bits are don't
care for 25C128), and then the data to be written.
ProgrammingwillstartaftertheCSisbroughthigh. Figure
6 illustrates byte write sequence.
The CAT25C128/256 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruc-
tion must be sent to CAT25C128/256. The device goes
into Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25C128/256.
TheCSmustbebroughthighaftertheWRENinstruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register)
instruction.
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) — — — —
Figure 5. RDSR Timing
CS
0
1
2
3
4
5
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
1
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) — — — —
Document No. 1018, Rev. I
8
CAT25C128/256
address counter reaches the end of the page and clock
continues, the counter will “roll over” to the first address
of the page and overwrite any data that may have been
written. The CAT25C128/256 is automatically returned
to the write disable state at the completion of the write
cycle. Figure 8 illustrates the page write sequence.
TheStatusRegistercanbereadtodetermineifthewrite
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction.
Page Write
The CAT25C128/256 features page write capability.
After the first initial byte the host may continue to write
up to 64 bytes of data to the CAT25C128/256. After
each byte of data is received, six lower order address
bits are internally incremented by one; the high order
bits of address will remain constant. The only restriction
is that the 64 bytes must reside on the same page. If the
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30
3
SK
SI
OPCODE
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
7
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
SI
DATA IN
OPCODE
Data
Byte 1
Data
Data
Data Byte N
0
0
0
0
0
0
1
0
ADDRESS
0
Byte 2 Byte 3
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Document No. 1018, Rev. I
9
CAT25C128/256
DESIGN CONSIDERATIONS
The CAT25C128/256 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the
CAT25C128/256 goes into a write disable mode. CS
must be set high after the proper number of clock cycles
tostartaninternalwritecycle. Accesstothearrayduring
an internal write cycle is ignored and program-ming
is continued. On power up, SO is in a high impedance.
If an invalid op code is received, no data will be shifted
intotheCAT25C128/256, andtheserialoutputpin(SO)
will remain in a high impedence state until the falling
edge of CS is detected again.
Whenpoweringdown,thesupplyshouldbetakendown
to 0V, so that the CAT25C128/256 will be reset when
power is ramped back up. If this is not possible, then,
following a brown-out episode, the CAT25C128/256
can be reset by refreshing the contents of the Status
Register (See Application Note AN10).
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line= mode (1, 1) — — — —
Figure 10. WP Timing
t
t
WPH
WPS
t
CSH
SCK
WP
Note: Dashed Line= mode (1, 1) — — — —
Document No. 1018, Rev. I
10
CAT25C128/256
ORDERING INFORMATION
Prefix
Device #
25C128
Suffix
- 1.8
– G
T3
V
CAT
I
Product
Tape & Reel
T: Tape & Reel
2: 2000/Reel
3: 3000/Reel
Temperature Range
Optional
Company ID
Number
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚C to +105˚C)
25C128: 128K
25C256: 256K
E = Extended (-40˚C to +125˚C)
Package
L: PDIP
Lead Finish
Blank: Matte-Tin
G: NiPdAu
V: SOIC, JEDEC**
X: SOIC, EIAJ(4)
Y14: 14-Pin TSSOP**
Y20: 20-Pin TSSOP**
Operating Voltage
Blank (VCC = 2.5V to 5.5V
1.8 (VCC = 1.8V to 5.5V)
**CAT25C128 only
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard finish is NiPdAu pre-plated (PPF).
(3) The device used in the above example is a CAT25C128VI-1.8-GT3 (SOIC, Industrial Temperature, 1.8V to 5.5V Operating Voltage,
NiPdAu, Tape & Reel).
(4) For SOIC, EIAJ (X) package the standard finish is Matte-Tin. This package is available in 2000 pcs/reel, i.e. CAT25C256XI-T2.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Document No. 1018, Rev. I
11
REVISION HISTORY
Date
Rev.
Reason
8/5/2004
F
Updated Features
Updated DC Operating Characteristics table & notes
2/172005
05/23/2005
10/13/06
G
H
I
Updated D.C. Operating Characteristics table
Updated Reliability Characteristics table
Update Features
Update Description
Update Pin Configuration
Update Pin Funtions
Update D.C. Operating Characteristics (V Range)
CC
Update A.C. Characteristics tables (V Range)
CC
Update Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
DPPs ™ AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1018
Revison:
Issue date:
Type:
I
10/13/06
Final
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明