CAT25C256U20A-TE13 [CATALYST]
128K/256K-Bit SPI Serial CMOS E2PROM; 128K / 256K位SPI串行E2PROM CMOS
| 型号： | CAT25C256U20A-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 128K/256K-Bit SPI Serial CMOS E2PROM |
| 文件： | 总11页 (文件大小：63K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT25C128/256
128K/256K-Bit SPI Serial CMOS E2PROM
FEATURES
■ 100,000 Program/Erase Cycles
■ 100 Year Data Retention
■ Self-Timed Write Cycle
■ 5 MHz SPI Compatible
■ 1.8 to 6.0 Volt Operation
■ Hardware and Software Protection
■ Zero Standby Current
■ 8-Pin DIP/SOIC, 16-Pin SOIC, 14-Pin TSSOP
and 20-Pin TSSOP
■ Low Power CMOS Technology
■ SPI Modes (0,0 &1,1)
■ 64-Byte Page Write Buffer
■ Block Write Protection
■ Commercial, Industrial and Automotive
– Protect 1/4, 1/2 or all of E2PROM Array
Temperature Ranges
DESCRIPTION
out (SO) are required to access the device. The HOLD
pin may be used to suspend any serial communication
without resetting the serial sequence. The CAT25C128/
256 is designed with software and hardware write pro-
tection features including Block Lock protection. The
device is available in 8-pin DIP, 8-pin SOIC, 16-pin
SOIC, 14-pin TSSOP and 20-pin TSSOP packages.
The CAT25C128/256 is a 128K/256K-Bit SPI Serial
CMOS E2PROM internally organized as 16Kx8/32Kx8
bits. Catalyst’s advanced CMOS Technology substan-
tially reduces device power requirements. The
CAT25C128/256 features a 64-byte page write buffer.
The device operates via the SPI bus serial interface and
is enabled though a Chip Select (CS). In addition to the
Chip Select, the clock input (SCK), data in (SI) and data
PIN CONFIGURATION
SOIC Package (S, K) TSSOP Package (U14)
BLOCK DIAGRAM
DIP Package (P)
14
13
12
11
10
9
8
SENSE AMPS
SHIFT REGISTERS
1
2
3
4
5
6
7
VCC
HOLD
NC
NC
NC
CS
SO
NC
NC
NC
WP
1
2
3
4
8
7
6
5
V
CS
SO
WP
CC
1
2
3
4
8
7
6
5
V
CS
SO
CC
HOLD
SCK
SI
HOLD
SCK
SI
WP
V
SS
COLUMN
DECODERS
V
SS
WORD ADDRESS
BUFFERS
SCK
SI
V
SS
SOIC Package (S16)
16
1
2
3
4
5
6
7
8
VCC
HOLD
NC
CS
SO
TSSOP Package (U20)
SO
SI
I/O
CONTROL
15
14
13
12
11
10
9
1
NC
NC
CS
SO
SO
NC
NC
WP
20
19
18
17
16
15
NC
NC
NC
NC
WP
VSS
VCC
HOLD
HOLD
NC
E2PROM
ARRAY
2
CS
NC
SPI
CONTROL
LOGIC
XDEC
3
WP
NC
4
HOLD
SCK
5
NC
6
NC
SCK
SI
7
14 SCK
13 SI
BLOCK
PROTECT
LOGIC
V
8
SS
NC
9
12 NC
11 NC
10
NC
PIN FUNCTIONS
DATA IN
STORAGE
Pin Name
SO
Function
Serial Data Output
HIGH VOLTAGE/
TIMING CONTROL
SCK
WP
Serial Clock
STATUS
REGISTER
Write Protect
25C128 F02
VCC
+1.8V to +6.0V Power Supply
Ground
VSS
CS
Chip Select
SI
Serial Data Input
Suspends Serial Input
HOLD
NC
No Connect
Note: CAT25C256 not available in 8-Lead S or U packages.
Doc. No. 25088-00 1/01
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT25C128/256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to VSS(1) .................. –2.0V to +VCC +2.0V
VCC with Respect to VSS ................................ –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
100
Volts
(3)(4)
ILTH
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Symbol
Parameter
Min.
Typ.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
10
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
ISB
Power Supply Current
(Operating Read)
2
mA
VCC = 5.5V
FCLK = 5MHz
Power Supply Current
(Standby)
0
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(3)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(3)
VIH
VCC x 0.7
4.5V≤V <5.5V
VOL1
VOH1
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25088-00 1/01
2
CAT25C128/256
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1) — — — —
A.C. CHARACTERISTICS (CAT25C128)
Limits
Vcc=
VCC
=
VCC
=
1.8V-6.0V
2.5V-6.0V
4.5V-5.5V
Test
SYMBOL PARAMETER
Min.
Max.
Min.
70
Max.
Min.
Max.
UNITS
ns
Conditions
tSU
tH
Data Setup Time
Data Hold Time
100
100
250
250
DC
35
35
80
80
DC
70
ns
tWH
tWL
fSCK
tLZ
SCK High Time
150
150
DC
ns
SCK Low Time
ns
Clock Frequency
HOLD to Output Low Z
Input Rise Time
1
50
2
3
50
2
5
50
2
MHz
ns
(1)
tRI
µs
(1)
tFI
Input Fall Time
2
2
2
µs
CL = 50pF
tHD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
250
250
250
250
40
40
ns
tCD
ns
tWC
tV
10
10
5
ms
ns
250
250
80
tHO
0
0
0
ns
tDIS
tHZ
250
150
250
150
100
50
ns
ns
tCS
1000
1000
1000
50
250
250
250
50
100
100
100
50
ns
tCSS
tCSH
tWPS
tWPH
NOTE:
CS Setup Time
ns
CS Hold Time
ns
WP Setup Time
ns
WP Hold Time
50
50
50
ns
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25088-00 1/01
3
CAT25C128/256
A.C. CHARACTERISTICS (CAT25C256)
Limits
=
1.8V-6.0V 2.5V-6.0V
Vcc=
VCC
VCC
2.7V-6.0V
Min. Max. Min. Max. Min. Max. Min. Max. UNITS
=
VCC
4.5V-5.5V
=
Test
Conditions
SYMBOL PARAMETER
tSU
tH
Data Setup Time
Data Hold Time
500
500
100
100
250
250
0.2 DC
100
2
70
70
35
35
80
80
DC
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWH
tWL
fSCK
tLZ
SCK High Time
2500
2500
DC
200
200
2.0 DC
50
SCK Low Time
Clock Frequency
HOLD to Output Low Z
Input Rise Time
2.5
50
2
5
50
2
(1)
tRI
2
(1)
tFI
Input Fall Time
2
2
2
2
CL = 50pF
tHD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
250
250
100
100
10
100
100
10
40
40
tCD
tWC
tV
10
5
250
0
200
0
200
80
tHO
tDIS
tHZ
0
0
250
150
100
100
100
50
200
100
100
100
100
50
200
100
100
50
tCS
100
100
100
50
100
100
100
50
tCSS
tCSH
tWPS
tWPH
CS Setup Time
CS Hold Time
WP Setup Time
WP Hold Time
50
50
50
50
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 25088-00 1/01
4
CAT25C128/256
CS: Chip Select
FUNCTIONAL DESCRIPTION
CSistheChipselectpin.CSlowenablestheCAT25C128/
256andCS highdisablestheCAT25C128/256. CS high
takes the SO output pin to high impedance and forces
the device into a Standby Mode (unless an internal write
operation is underway) The CAT25C128/256 draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
sequence is what initiates an internal write cycle.
The CAT25C128/256 supports the SPI bus data trans-
mission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C128/256 to interface
directly with many of today’s popular microcontrollers.
TheCAT25C128/256containsan8-bitinstructionregis-
ter. (The instruction set and the operation codes are
detailed in the instruction set table)
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C128/256. Input data is latched on the rising edge of
the serial clock.
HOLD: Hold
SO: Serial Output
HOLD is the HOLD pin. The HOLD pin is used to pause
transmission to the CAT25C128/256 while in the middle
of a serial sequence without having to re-transmit entire
sequence at a later time. To pause, HOLD must be
brought low while SCK is low. The SO pin is in a high
impedance state during the time the part is paused, and
transitions on the SI pins will be ignored. To resume
communication,HOLDisbroughthigh,whileSCKislow.
(HOLD should be held high any time this function is not
beingused.)HOLDmaybetiedhighdirectlytoVcc ortied
to Vcc through a resistor. Figure 9 illustrates hold timing
sequence.
SO is the serial data output pin. This pin is used to
transferdataoutofthe25C128/256.Duringareadcycle,
data is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C128/256. Opcodes, byte addresses, or data
presentontheSIpinarelatchedontherisingedgeofthe
SCK. Data on the SO pin is updated on the falling edge
of the SCK.
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
WRITE
Doc. No. 25088-00 1/01
5
CAT25C128/256
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
array. These bits are non-volatile.
STATUS REGISTER
The Status Register indicates the status of the device.
TheRDY(Ready)bitindicateswhethertheCAT25C128/
256 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only
TheWPEN(WriteProtectEnable)isanenablebitforthe
WP pin. The WPpin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
tothestatusregister(includingtheblockprotectbitsand
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write pro-
tected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
The WEL (Write Enable) bit indicates the status of the
writeenablelatch. Whensetto1, thedeviceisinaWrite
Enable state and when set to 0 the device is in a Write
Disablestate. TheWELbit canonlybesetbytheWREN
instruction and can be reset by the WRDI instruction.
The BPO and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
Protection
BP1
BPO
25C128
25C256
None
0
0
1
1
0
1
0
1
None
No Protection
3000-3FFF
2000-3FFF
0000-3FFF
6000-7FFF
4000-7FFF
0000-7FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
WPEN
WP
X
WEL
Register
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
Doc. No. 25088-00 1/01
6
CAT25C128/256
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address (7FFFh for 25C256 and 3FFFh for 25C128) is
reached, the address counter rolls over to 0000h allow-
ing the read cycle to be continued indefinitely. The read
operation is terminated by pulling the CS high. To read
the status register, RDSR instruction should be sent.
The contents of the status register are shifted out on the
SO line. The status register may be read at any time
evenduringawritecycle.Readsequenceisillustratedin
figure 4. Reading status register is illustrated in figure 5.
DEVICE OPERATION
Write Enable and Disable
TheCAT25C128/256containsawriteenablelatch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WREN instruction will enable writes (set the latch) to the
device. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C128/256, fol-
lowed by the 16-bit address (the Most Significant Bit is
don’t care for 25C256 and the two most significant bits
are don't care for the 25C128).
Figure 2. WREN Instruction Timing
CS
SK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 3. WRDI Instruction Timing
CS
SK
SI
1
0
0
0
0
0
0
0
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 25088-00 1/01
7
CAT25C128/256
WRITE Sequence
Byte Write
The CAT25C128/256 powers up in a Write Disable
state. Prior to any write instructions, the WREN instruc-
tion must be sent to CAT25C128/256. The device goes
into Write enable state by pulling the CS low and then
clocking the WREN instruction into CAT25C128/256.
TheCSmustbebroughthighaftertheWRENinstruction
to enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address (the most significant bit is don't care for
25C256 and the two most significant bits are don't care
for the 25C128), and then the data to be written. Pro-
gramming will start after the CS is brought high. The low
to high transition of the CS pin must occur during the
SCK low time, immediately after clocking the least
significant bit of the data. Figure 6 illustrates byte write
sequence.
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the instruction set table for address
Note: Dashed Line= mode (1, 1) — — — —
Figure 5. RDSR Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 25088-00 1/01
8
CAT25C128/256
address will remain constant.The only restriction is that
the 64 bytes must reside on the same page. If the
address counter reaches the end of the page and clock
continues, the counter will “roll over” to the first address
of the page and overwrite any data that may have been
written. The CAT25C128/256 is automatically returned
to the write disable state at the completion of the write
cycle. Figure 8 illustrates the page write sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) in-
struction.
TheStatusRegistercanbereadtodetermineifthewrite
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction
Page Write
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
The CAT25C128/256 features page write capability.
After the initial byte the host may continue to write up to
64bytesof datatotheCAT25C128/256.Aftereachbyte
of data is received, six lower order address bits are
internally incremented by one; the high order bits of
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
SI
OPCODE
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
ADDRESS
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 7. WRSR Timing
CS
0
1
2
3
4
5
6
7
1
8
7
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
3
MSB
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
SI
DATA IN
Data Data
Byte 2 Byte 3
OPCODE
Data
Byte 1
Data Byte N
0
0
0
0
0
0
1
0
ADDRESS
0
7..1
HIGH IMPEDANCE
SO
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 25088-00 1/01
9
CAT25C128/256
DESIGN CONSIDERATIONS
tostartaninternalwritecycle. Accesstothearrayduring
an internal write cycle is ignored and programming
is continued. On power up, SO is in a high impedance.
If an invalid op code is received, no data will be shifted
into the CAT25C128/256, and the serial output pin (SO)
will remain in a high impedance state until the falling
edge of CS is detected again.
The CAT25C128/256 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the
CAT25C128/256 goes into a write disable mode. CS
must be set high after the proper number of clock cycles
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Note: Dashed Line= mode (1, 1) — — — —
Figure 10. WP Timing
t
t
WPH
WPS
CS
SCK
WP
t
CSH
WP
Note: Dashed Line= mode (1, 1) — — — —
Doc. No. 25088-00 1/01
10
CAT25C128/256
ORDERING INFORMATION
Prefix
Device #
25C256
Suffix
- 1.8
K
CAT
TE13
I
Product
Temperature Range
Tape & Reel
TE13: 2000/Reel
Optional
Company ID
Number
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
25C128: 128K
25C256: 256K
Package
Operating Voltage
Blank (Vcc=2.5 to 6.0V)
1.8 (Vcc=1.8 to 6.0V)
P = 8-Pin PDIP
S = 8-Pin SOIC (JEDEC)
S16 = 16-Pin SOIC (JEDEC)
K = 8-Pin SOIC (EIAJ)
U14 = 14-Pin TSSOP
U20 = 20-Pin TSSOP
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 25C256KI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating
Voltage, Tape & Reel)
Doc. No. 25088-00 1/01
11
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明