CAT25C64PA-TE13 [CATALYST]
64K/128K-Bit SPI Serial CMOS E2PROM; 64K / 128K位SPI串行E2PROM CMOS
| 型号： | CAT25C64PA-TE13 |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 64K/128K-Bit SPI Serial CMOS E2PROM |
| 文件： | 总9页 (文件大小：101K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Advance Information
CAT25C64/128
64K/128K-Bit SPI Serial CMOS E2PROM
FEATURES
■ 1,000,000 Program/Erase Cycles
■ 100 Year Data Retention
■ 5 MHz SPI Compatible
■ 1.8 to 6.0 Volt Operation
■ Hardware and Software Protection
■ Zero Standby Current
■ Self-Timed Write Cycle
■ 8-Pin DIP/SOIC, 16-Pin SOIC and 20-Pin TSSOP
■ 64-Byte Page Write Buffer
■ Low Power CMOS Technology
■ SPI Modes (0,0)
■ Block Write Protection
– Protect 1/4, 1/2 or all of E2PROM Array
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
required to access the device. The HOLD pin may be
used to suspend any serial communication without
resetting the serial sequence. The CAT25C64/128 is
designed with software and hardware write protection
features including Block write protection. The device is
available in 8-pin DIP, 8-pin SOIC, 16-pin SOIC and 20-
pin TSSOP packages.
TheCAT25C64/128isa64K/128K-BitSPISerialCMOS
E2PROM internally organized as 8Kx8/16Kx8 bits.
Catalyst’s advanced CMOS Technology substantially
reduces device power requirements. The CAT25C64/
128 features a 64-byte page write buffer. The device
operates via the SPI bus serial interface and is enabled
thoughaChipSelect(CS). InadditiontotheChipSelect,
the clock input (SCK), data in (SI) and data out (SO) are
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (S)
SOIC Package (S16)
TSSOP Package (U20)
1
2
3
4
8
7
6
5
V
CS
SO
WP
CC
16
1
2
3
4
5
6
7
8
VCC
HOLD
NC
1
NC
NC
CS
SO
SO
NC
NC
WP
SS
NC
NC
20
19
18
17
16
15
CS
SO
HOLD
SCK
SI
VCC
HOLD
HOLD
NC
2
15
14
13
12
11
10
9
3
NC
NC
NC
NC
WP
VSS
V
4
SS
SENSE AMPS
SHIFT REGISTERS
NC
5
6
NC
NC
7
14 SCK
13 SI
12 NC
11 NC
DIP Package (P)
NC
V
8
SCK
SI
9
1
2
3
4
8
7
6
5
COLUMN
DECODERS
V
WORD ADDRESS
BUFFERS
CS
SO
CC
10
HOLD
SCK
SI
WP
V
SS
SO
SI
I/O
CONTROL
PIN FUNCTIONS
Pin Name
E2PROM
ARRAY
CS
Function
SPI
XDEC
WP
CONTROL
LOGIC
SO
Serial Data Output
Serial Clock
HOLD
SCK
SCK
WP
VCC
VSS
CS
BLOCK
PROTECT
LOGIC
Write Protect
+1.8V to +6.0V Power Supply
Ground
DATA IN
STORAGE
Chip Select
SI
Serial Data Input
Suspends Serial Input
HIGH VOLTAGE/
TIMING CONTROL
HOLD
STATUS
REGISTER
NC
No Connect
25C128 F02
© 1999 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc No. 25069-00 6/99 SPI-1
1
CAT25C64/128
Advance Information
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
Units
Cycles/Byte
Years
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
NEND
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
D.C. OPERATING CHARACTERISTICS
= +1.8V to +6.0V, unless otherwise specified.
V
CC
Limits
Typ.
Symbol
Parameter
Min.
Max.
Units
Test Conditions
ICC1
Power Supply Current
(Operating Write)
10
mA
VCC = 5V @ 5MHz
SO=open; CS=Vss
ICC2
ISB
Power Supply Current
(Operating Read)
2
0
mA
VCC = 5.5V
FCLK = 5MHz
Power Supply Current
(Standby)
µA
CS = VCC
VIN = VSS or VCC
ILI
Input Leakage Current
Output Leakage Current
2
3
µA
µA
ILO
VOUT = 0V to VCC
,
CS = 0V
(3)
VIL
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
-1
VCC x 0.3
VCC + 0.5
0.4
V
V
V
V
(3)
VIH
VCC x 0.7
4.5V≤V <5.5V
VOL1
VOH1
CC
= 3.0mA
= -1.6mA
I
I
OL
OH
VCC - 0.8
VCC-0.2
VOL2
VOH2
Output Low Voltage
Output High Voltage
0.2
V
V
1.8V≤VCC<2.7V
IOL = 150µA
IOH = -100µA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25069-00 6/99 SPI-1
2
Advance Information
CAT25C64/128
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
CSH
t
CSS
VIH
VIL
t
t
WL
SCK
SI
WH
t
t
H
SU
VIH
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
A.C. CHARACTERISTICS
Limits
VCC
2.5V-6V
Min. Max. Min. Max. Min. Max. UNITS Conditions
Vcc=
1.8V-6V
=
VCC
4.5V-5.5V
=
Test
SYMBOL PARAMETER
tSU
tH
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
Clock Frequency
100
100
250
250
DC
70
70
35
35
80
80
DC
ns
ns
ns
ns
MHz
ns
µs
µs
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
tWH
tWL
fSCK
tLZ
150
150
DC
1
50
2
3
50
2
5
50
2
HOLD to Output Low Z
Input Rise Time
(1)
tRI
CL = 50pF
(1)
tFI
Input Fall Time
2
2
2
tHD
HOLD Setup Time
HOLD Hold Time
Write Cycle Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
250
250
250
250
40
40
tCD
tWC
tV
10
10
5
250
220
100
tHO
tDIS
tHZ
0
0
0
250
150
250
150
100
50
tCS
1000
1000
1000
330
100
100
200
100
100
tCSS
tCSH
NOTE:
CS Setup Time
CS Hold Time
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc No. 25069-00 6/99 SPI-1
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CAT25C64/128
Advance Information
CS: Chip Select
FUNCTIONAL DESCRIPTION
CSistheChipselectpin.CSlowenablestheCAT25C64/
128 and CS high disables the CAT25C64/128. CS high
takes the SO output pin to high impedance and forces
the devices into a Standby Mode (unless an internal
writeoperationisunderway). TheCAT25C64/128draws
ZERO current in the Standby mode. A high to low
transition on CS is required prior to any sequence being
initiated. A low to high transition on CS after a valid write
sequence is what initiates an internal write cycle.
The CAT25C64/128 supports the SPI bus data trans-
mission protocol. The synchronous Serial Peripheral
Interface (SPI) helps the CAT25C64/128 to interface
directly with many of today’s popular microcontrollers.
The CAT25C64/128 contains an 8-bit instruction regis-
ter. (The instruction set and the operation codes are
detailed in the instruction set table)
After the device is selected with CS going low, the first
byte will be received. The part is accessed via the SI pin,
with data being clocked in on the rising edge of SCK.
Thefirstbytecontainsoneofthesixop-codesthatdefine
the operation to be performed.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will
allow normal read/write operations when held high.
When WP is tied low and the WPEN bit in the status
register is set to “1”, all write operations to the status
register are inhibited. WP going low while CS is still low
will interrupt a write to the status register. If the internal
write cycle has already been initiated, WP going low will
have no effect on any write operation to the status
register.TheWPpinfunctionisblockedwhentheWPEN
bit is set to 0.
PIN DESCRIPTION
SI: Serial Input
SI is the serial data input pin. This pin is used to input all
opcodes, byte addresses, and data to be written to the
25C64/128. Input data is latched on the rising edge of
the serial clock.
HOLD: Hold
SO: Serial Output
The HOLD pin is used to pause transmission to the
CAT25C64/128 while in the middle of a serial sequence
without having to re-transmit entire sequence at a later
time. To pause, HOLD must be brought low while SCK
islow.TheSOpinisinahighimpedancestateduringthe
timethepartispaused, andtransitionsontheSIpinswill
beignored.Toresumecommunication,HOLDisbrought
high, while SCK is low. (HOLD should be held high any
time this function is not being used.) HOLD may be tied
high directly to Vcc or tied to Vcc through a resistor.
Figure 9 illustrates hold timing sequence.
SO is the serial data output pin. This pin is used to
transfer data out of the 25C64/128. During a read cycle,
data is shifted out on the falling edge of the serial clock.
SCK: Serial Clock
SCK is the serial clock pin. This pin is used to synchro-
nize the communication between the microcontroller
and the 25C64/128. Opcodes, byte addresses, or data
presentontheSIpinarelatchedontherisingedgeofthe
SCK. Data on the SO pin is updated on the falling edge
of the SCK.
INSTRUCTION SET
Instruction
WREN
WRDI
Opcode
Operation
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
Enable Write Operations
Disable Write Operations
Read Status Register
Write Status Register
Read Data from Memory
Write Data to Memory
RDSR
WRSR
READ
WRITE
Doc. No. 25069-00 6/99 SPI-1
4
Advance Information
CAT25C64/128
array. These bits are non-volatile.
STATUS REGISTER
TheWPEN(WriteProtectEnable)isanenablebitforthe
WP pin. The WP pin and WPEN bit in the status register
control the programmable hardware write protect fea-
ture. Hardware write protection is enabled when WP is
low and WPEN bit is set to high. The user cannot write
tothestatusregister(includingtheblockprotectbitsand
the WPEN bit) and the block protected sections in the
memory array when the chip is hardware write pro-
tected. Only the sections of the memory array that are
not block protected can be written. Hardware write
protection is disabled when either WP pin is high or the
WPEN bit is zero.
The Status Register indicates the status of the device.
The RDY (Ready) bit indicates whether the CAT25C64/
128 is busy with a write operation. When set to 1 a write
cycle is in progress and when set to 0 the device
indicates it is ready. This bit is read only.
The WEL (Write Enable) bit indicates the status of the
writeenablelatch. Whensetto1, thedeviceisinaWrite
Enable state and when set to 0 the device is in a Write
Disablestate. TheWELbitcanonlybesetbytheWREN
instruction and can be reset by the WRDI instruction.
The BP0 and BP1 (Block Protect) bits indicate which
blocks are currently protected. These bits are set by the
user issuing the WRSR instruction. The user is allowed
to protect quarter of the memory, half of the memory or
the entire memory by setting these bits. Once protected
the user may only read from the protected portion of the
STATUS REGISTER
7
6
5
4
3
2
1
0
WPEN
X
X
X
BP1
BP0
WEL
RDY
BLOCK PROTECTION BITS
Status Register Bits
Array Address
Protected
Protection
BP1
0
BP0
0
None
No Protection
0
1
25C128: 3000-3FFF
25C64:1800-1FFF
Quarter Array Protection
Half Array Protection
Full Array Protection
1
1
0
1
25C128: 2000-3FFF
25C64:1000-1FFF
25C128: 0000-3FFF
25C64:1000-1FFF
WRITE PROTECT ENABLE OPERATION
Protected
Blocks
Unprotected
Blocks
Status
WPEN
WP
X
WEL
Register
0
0
1
1
X
X
0
1
0
1
0
1
Protected
Protected
Protected
Protected
Protected
Protected
Protected
Writable
Protected
Writable
Protected
Writable
Protected
Writable
X
Low
Low
High
High
Protected
Protected
Protected
Writable
Doc No. 25069-00 6/99 SPI-1
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CAT25C64/128
Advance Information
After the correct read instruction and address are sent,
the data stored in the memory at the selected address is
shifted out on the SO pin. The data stored in the memory
at the next address can be read sequentially by continu-
ing to provide clock pulses. The internal address pointer
is automatically incremented to the next higher address
after each byte of data is shifted out. When the highest
address (1FFFh for 25C64 and 3FFFh for 25C128) is
reached, the address counter rolls over to 0000h allow-
ing the read cycle to be continued indefinitely. The read
operation is terminated by pulling the CS high. To read
the status register, RDSR instruction should be sent.
The contents of the status register are shifted out on the
SO line. The status register may be read at any time
even during a write cycle. Read sequece is illustrated in
Figure 4. Reading status register is illustrated in Figure 5.
DEVICE OPERATION
Write Enable and Disable
The CAT25C64/128 contains a write enable latch. This
latch must be set before any write operation. The device
powers up in a write disable state when Vcc is applied.
WRENinstructionwillenable writes(setthelatch)tothe
device. WRDI instruction will disable writes (reset the
latch) to the device. Disabling writes will protect the
device against inadvertent writes.
READ Sequence
The part is selected by pulling CS low. The 8-bit read
instruction is transmitted to the CAT25C64/128, fol-
lowed by the 16-bit address(the three Most Significant
Bits are don’t care for 25C64 and two most significant
bits are don't care for 25C128).
Figure 2. WREN Instruction Timing
CS
SK
1
1
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Figure 3. WRDI Instruction Timing
CS
SK
1
0
0
SI
0
0
0
0
0
HIGH IMPEDANCE
SO
Doc. No. 25069-00 6/99 SPI-1
6
Advance Information
CAT25C64/128
WRITE Sequence
Byte Write
The CAT25C64/128 powers up in a Write Disable state.
Prior to any write instructions, the WREN instruction
must be sent to CAT25C64/128. The device goes into
Write enable state by pulling the CS low and then
clockingtheWRENinstructionintoCAT25C64/128.The
CS must be brought high after the WREN instruction to
enable writes to the device. If the write operation is
initiated immediately after the WREN instruction without
CS being brought high, the data will not be written to the
array because the write enable latch will not have been
properly set. Also, for a successful write operation the
address of the memory location(s) to be programmed
must be outside the protected address field location
selected by the block protection level.
Once the device is in a Write Enable state, the user may
proceed with a write sequence by setting the CS low,
issuing a write instruction via the SI line, followed by the
16-bit address (the three Most Significant Bits are don’t
care for 25C64 and two most significant bits are don't
care for 25C128), and then the data to be written.
Programming will start after the CS is brought high.
Figure 6 illustrates byte write sequence.
Figure 4. Read Instruction Timing
CS
0
1
2
3
4
5
6
7
8
9
10
20 21 22 23 24 25 26 27 28 29 30
SK
OPCODE
BYTE ADDRESS*
SI
0
0
0
0
0
0
1
1
DATA OUT
HIGH IMPEDANCE
SO
7
6
5
4
3
2
1
0
MSB
*Please check the instruction set table for address
Figure 5. RDSR Instruction Timing
CS
0
1
2
3
4
5
1
6
0
7
1
8
9
10
11
12
13
14
SCK
OPCODE
0
0
0
0
0
SI
DATA OUT
HIGH IMPEDANCE
SO
5
7
6
4
3
2
1
0
MSB
Doc No. 25069-00 6/99 SPI-1
7
CAT25C64/128
Advance Information
restriction is that the 64 bytes must reside on the same
page. If the address counter reaches the end of the
page and clock continues, the counter will “roll over” to
the first address of the page and overwrite any data that
may have been written. The CAT25C64/128 is auto-
maticallyreturnedtothewritedisablestateatthecomple-
tion of the write cycle. Figure 8 illustrates the page write
sequence.
During an internal write cycle, all commands will be
ignored except the RDSR (Read Status Register) in-
struction.
TheStatusRegistercanbereadtodetermineifthewrite
cycle is still in progress. If Bit 0 of the Status Register is
set at 1, write cycle is in progress. If Bit 0 is set at 0, the
device is ready for the next instruction.
Page Write
To write to the status register, the WRSR instruction
should be sent. Only Bit 2, Bit 3 and Bit 7 of the status
register can be written using the WRSR instruction.
Figure 7 illustrates the sequence of writing to status
register.
The CAT25C64/128 features page write capability. Afer
the first initial byte the host may continue to write up to
64 bytes of data to the CAT25C64/128. After each byte
of data is received, six lower order address bits are
internally incremented by one; the high order bits of
address will remain constant. The only
Figure 6. Write Instruction Timing
CS
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31
SK
SI
OPCODE
DATA IN
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
1
0
ADDRESS
HIGH IMPEDANCE
SO
Figure 7. WRSR Instruction Timing
CS
0
1
2
3
4
5
6
7
1
8
9
6
10
5
11
4
12
13
2
14
1
15
0
SCK
OPCODE
DATA IN
SI
0
0
0
0
0
0
0
7
3
MSB
HIGH IMPEDANCE
SO
Doc. No. 25069-00 6/99 SPI-1
8
Advance Information
CAT25C64/128
DESIGN CONSIDERATIONS
The CAT25C64/128 powers up in a write disable state
and in a low power standby mode. A WREN instruction
must be issued to perform any writes to the device after
power up. Also,on power up CS should be brought low
to enter a ready state and receive an instruction. After
a successful byte/page write or status register write the
CAT25C64/128 goes into a write disable mode. CS
mustbesethighafterthepropernumberofclockcycles
to start an internal write cycle. Access to the array
duringaninternal write cycle is ignored and program-
ming is continued. On power up, SO is in a high
impedance.
Figure 8. Page Write Instruction Timing
CS
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1
0
1
2
3
4
5
6
7
8
21 22 23
32-39
24-31
SK
SI
DATA IN
Data Data
OPCODE
Data
Byte 1
Data Byte N
0
0
0
0
0
0
1
0
ADDRESS
0
Byte 2 Byte 3
7..1
HIGH IMPEDANCE
SO
Figure 9. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
ORDERING INFORMATION
Prefix
Device #
Suffix
-1.8
25C64
S
CAT
TE13
I
Product
Number
25C64: 64K
25C128: 128K
Temperature Range
Tape & Reel
TE13: 2000/Reel
Optional
Company ID
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Operating Voltage
Blank = 2.5 to 6.0V
1.8 = 1.8 to 6.0V
Package
P = PDIP
S = 8-Pin SOIC
S16 = 16-Pin SOIC
U20 = 20-Pin TSSOP
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a 25C64SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,
Tape & Reel)
Doc No. 25069-00 6/99 SPI-1
9
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