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CAT25C65PE-1.8 [CATALYST]

EEPROM, 8KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8;
CAT25C65PE-1.8
型号： CAT25C65PE-1.8
厂家： CATALYST SEMICONDUCTOR    CATALYST SEMICONDUCTOR
描述：

EEPROM, 8KX8, Serial, CMOS, PDIP8, PLASTIC, DIP-8

可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路
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中文：  中文翻译
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CAT25C33/65  
32K/64K-Bit SPI Serial CMOS EEPROM  
FEATURES  
■ 1,000,000 program/erase cycles  
■ 100 year data tetention  
■ 10 MHz SPI compatible  
■ 1.8 to 6.0 volt operation  
■ Self-timed write cycle  
■ Hardware and software protection  
■ Low power CMOS technology  
■ SPI modes (0,0 &1,1)  
■ 8-pin DIP/SOIC and 14-pin TSSOP  
■ 64-byte page write buffer  
■ Block write protection  
■ Commercial, industrial, automotive and extended  
– Protect first page, last page, any 1/4 or lower  
1/2 of EEPROM array  
temperature ranges  
DESCRIPTION  
required to access the device. The HOLD pin may be  
used to suspend any serial communication without  
resetting the serial sequence. The CAT25C32/64 is  
designed with software and hardware write protection  
features including Block write protection. The device is  
available in 8-pin DIP, 8-pin SOIC, 14-pin TSSOP and  
20-pin TSSOP packages.  
The CAT25C33/65 is a 32K/64K-Bit SPI Serial CMOS  
EEPROM internally organized as 4Kx8/8Kx8 bits.  
Catalyst’s advanced CMOS Technology substantially  
reduces device power requirements. The CAT25C33/  
65 features a 64-byte page write buffer. The device  
operates via the SPI bus serial interface and is enabled  
thoughaChipSelect(CS). InadditiontotheChipSelect,  
the clock input (SCK), data in (SI) and data out (SO) are  
PIN CONFIGURATION  
BLOCK DIAGRAM  
SOIC Package (S, V, GV) TSSOP Package (U14, Y14)  
14  
13  
12  
11  
10  
9
8
1
2
3
4
5
6
7
VCC  
HOLD  
NC  
NC  
NC  
CS  
SO  
NC  
NC  
NC  
WP  
1
2
3
4
8
7
6
5
V
CS  
SO  
WP  
CC  
SENSE AMPS  
SHIFT REGISTERS  
HOLD  
SCK  
SI  
V
SS  
SCK  
SI  
COLUMN  
DECODERS  
WORD ADDRESS  
BUFFERS  
V
SS  
DIP Package (P, L, GL)  
1
2
3
4
8
7
6
5
V
SO  
SI  
CS  
SO  
CC  
I/O  
CONTROL  
HOLD  
SCK  
SI  
E2PROM  
ARRAY  
WP  
CS  
SPI  
CONTROL  
LOGIC  
XDEC  
V
SS  
WP  
HOLD  
SCK  
PIN FUNCTIONS  
Pin Name  
BLOCK  
PROTECT  
LOGIC  
Function  
SO  
Serial Data Output  
DATA IN  
STORAGE  
SCK  
WP  
VCC  
VSS  
CS  
Serial Clock  
Write Protect  
HIGH VOLTAGE/  
TIMING CONTROL  
+1.8V to +6.0V Power Supply  
Ground  
STATUS  
REGISTER  
Chip Select  
SI  
Serial Data Input  
Suspends Serial Input  
HOLD  
NC  
No Connect  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1000, Rev. H  
1
CAT25C33/65  
ABSOLUTE MAXIMUM RATINGS*  
*COMMENT  
Temperature Under Bias ................. –55°C to +125°C  
Storage Temperature....................... –65°C to +150°C  
Stresses above those listed under “Absolute Maximum  
Ratings” may cause permanent damage to the device.  
These are stress ratings only, and functional operation  
of the device at these or any other conditions outside of  
those listed in the operational sections of this specifica-  
tion is not implied. Exposure to any absolute maximum  
rating for extended periods may affect device perfor-  
mance and reliability.  
Voltage on any Pin with  
Respect to VSS1) ................... –2.0V to +VCC +2.0V  
V
CC with Respect to VSS................................ –2.0V to +7.0V  
Package Power Dissipation  
Capability (Ta = 25°C)................................... 1.0W  
Lead Soldering Temperature (10 secs) ............ 300°C  
Output Short Circuit Current(2) ........................ 100 mA  
RELIABILITY CHARACTERISTICS  
Symbol  
Parameter  
Endurance  
Min.  
1,000,000  
100  
Typ.  
Max.  
Units  
Cycles/Byte  
Years  
(3)  
NEND  
(3)  
TDR  
Data Retention  
ESD Susceptibility  
Latch-up  
(3)  
VZAP  
2000  
Volts  
(3)(4)  
ILTH  
100  
mA  
D.C. OPERATING CHARACTERISTICS  
V
= +1.8V to +6.0V, unless otherwise specified.  
CC  
Limits  
Typ.  
Symbol  
Parameter  
Min.  
Max.  
Units  
Test Conditions  
ICC1  
Power Supply Current  
(Operating Write)  
10  
mA  
VCC = 5V @ 10MHz  
SO=open; CS=Vss  
ICC2  
Power Supply Current  
(Operating Read)  
2
1
mA  
VCC = 5.0V  
FCLK = 10MHz  
(5)  
ISB  
Power Supply Current  
(Standby)  
µA  
CS = VCC  
VIN = VSS or VCC  
ILI  
Input Leakage Current  
Output Leakage Current  
2
3
µA  
µA  
ILO  
VOUT = 0V to VCC  
,
CS = 0V  
(3)  
VIL  
Input Low Voltage  
Input High Voltage  
Output Low Voltage  
Output High Voltage  
-1  
VCC x 0.3  
VCC + 0.5  
0.4  
V
V
V
V
(3)  
VIH  
VCC x 0.7  
VOL1  
VOH1  
4.5V≤V <5.5V  
CC  
I
I
= 3.0mA  
= -1.6mA  
VCC - 0.8  
VCC-0.2  
OL  
OH  
VOL2  
VOH2  
Output Low Voltage  
Output High Voltage  
0.2  
V
V
1.8V≤VCC<2.7V  
IOL = 150µA  
IOH = -100µA  
Note:  
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC  
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.  
CC  
CC  
(2) Output shorted for no more than one second. No more than one output shorted at a time.  
(3) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100  
and JEDEC test methods.  
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.  
CC  
(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.  
SB  
Doc. No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
2
CAT25C33/65  
(1)  
PIN CAPACITANCE  
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).  
Symbol  
COUT  
CIN  
Test Conditions  
Max.  
Units  
pF  
Conditions  
VOUT=0V  
VIN=0V  
Output Capacitance (SO)  
8
6
Input Capacitance (CS, SCK, SI, WP, HOLD)  
pF  
A.C. CHARACTERISTICS  
Limits  
Vcc=  
1.8V-6.0V  
VCC  
2.5V-6.0V  
=
VCC  
4.5V-5.5V  
Max. Min. Max. UNITS Conditions  
=
Test  
SYMBOL PARAMETER  
Min. Max. Min.  
tSU  
tH  
Data Setup Time  
Data Hold Time  
50  
50  
50  
50  
20  
20  
40  
40  
DC  
ns  
ns  
ns  
ns  
MHz  
ns  
µs  
µs  
ns  
ns  
ms  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tWH  
tWL  
fSCK  
tLZ  
SCK High Time  
250  
250  
DC  
125  
125  
DC  
SCK Low Time  
Clock Frequency  
HOLD to Output Low Z  
Input Rise Time  
1
50  
2
3
50  
2
10  
50  
2
(1)  
tRI  
CL = 50pF  
(1)  
tFI  
Input Fall Time  
2
2
2
tHD  
HOLD Setup Time  
HOLD Hold Time  
Write Cycle Time  
Output Valid from Clock Low  
Output Hold Time  
Output Disable Time  
HOLD to Output High Z  
CS High Time  
100  
100  
100  
100  
40  
40  
tCD  
tWC  
tV  
10  
10  
5
250  
250  
80  
tHO  
tDIS  
tHZ  
0
0
0
250  
150  
250  
100  
75  
50  
tCS  
500  
500  
500  
250  
250  
250  
200  
100  
100  
tCSS  
tCSH  
NOTE:  
CS Setup Time  
CS Hold Time  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
Doc No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
3
CAT25C33/65  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTION  
The CAT25C33/65 supports the SPI bus data  
transmissionprotocol.ThesynchronousSerialPeripheral  
Interface (SPI) helps the CAT25C33/65 to interface  
directly with many of today’s popular microcontrollers.  
TheCAT25C33/65containsan8-bitinstructionregister.  
(Theinstructionset andtheoperationcodesaredetailed  
in the instruction set table)  
SI: Serial Input  
SI is the serial data input pin. This pin is used to input all  
opcodes, byte addresses, and data to be written to the  
25C33/65. Input data is latched on the rising edge of the  
serial clock.  
SO: Serial Output  
SO is the serial data output pin. This pin is used to  
transfer data out of the 25C33/65. During a read cycle,  
data is shifted out on the falling edge of the serial clock.  
After the device is selected with CS going low, the first  
byte will be received. The part is accessed via the SI pin,  
with data being clocked in on the rising edge of SCK.  
Thefirstbytecontainsoneofthesixop-codesthatdefine  
the operation to be performed.  
Figure 1. Sychronous Data Timing  
t
CS  
VIH  
CS  
VIL  
t
CSH  
t
CSS  
VIH  
VIL  
t
t
WL  
SCK  
SI  
WH  
t
t
H
SU  
VIH  
VALID IN  
V
IL  
t
RI  
FI  
t
t
V
t
t
HO  
DIS  
VOH  
VOL  
HI-Z  
HI-Z  
SO  
Note: Dashed Line= mode (1, 1) — — — —  
INSTRUCTION SET  
Instruction  
WREN  
WRDI  
Opcode  
Operation  
0000 0110  
0000 0100  
0000 0101  
0000 0001  
0000 0011  
0000 0010  
Enable Write Operations  
Disable Write Operations  
Read Status Register  
Write Status Register  
Read Data from Memory  
Write Data to Memory  
RDSR  
WRSR  
READ  
WRITE  
(2)(3)  
Power-Up Timing  
Symbol  
tPUR  
Parameter  
Max.  
Units  
ms  
Power-up to Read Operation  
Power-up to Write Operation  
1
1
tPUW  
ms  
Note:  
(1) X=0 for 25010, 25020. X=A8 for 25040  
(2) This parameter is tested initially and after a design or process change that affects the parameter.  
(3) t and t are the delays required from the time V is stable until the specified operation can be initiated.  
PUR  
PUW  
CC  
Doc. No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
4
CAT25C33/65  
SCK: Serial Clock  
WP: Write Protect  
SCK is the serial clock pin. This pin is used to synchro- WP is the Write Protect pin. The Write Protect pin will allow  
nize the communication between the microcontroller normal read/write operations when held high. When WP is  
and the 25C33/65. Opcodes, byte addresses, or data tied low and the WPEN bit in the status register is set to “1”,  
presentontheSIpinarelatchedontherisingedgeofthe all write operations to the status register are inhibited. WP  
SCK. Data on the SO pin is updated on the falling edge goinglowwhileCSisstilllowwillinterruptawritetothestatus  
of the SCK.  
register. If the internal write cycle has already been initiated,  
WPgoinglowwillhavenoeffectonanywriteoperationtothe  
status register. The WP pin function is blocked when the  
WPEN bit is set to 0.  
CS: Chip Select  
HOLD: Hold  
CSistheChipselectpin.CSlowenablestheCAT25C33/  
65 and CS high disables the CAT25C33/65. CS high  
takes the SO output pin to high impedance and forces  
the devices into a Standby Mode (unless an internal  
write operation is underway). The CAT25C33/65 draws  
ZERO current in the Standby mode. A high to low  
transition on CS is required prior to any sequence being  
initiated. A low to high transition on CS after a valid write  
sequence is what initiates an internal write cycle.  
The HOLD pin is used to pause transmission to the  
CAT25C33/65 while in the middle of a serial sequence  
without having to re-transmit entire sequence at a later time.  
To pause, HOLD must be brought low while SCK is low. The  
SO pin is in a high impedance state during  
the time the part is paused, and transitions on the SI pins  
willbeignored. Toresumecommunication, HOLDisbrought  
high, while SCK is low. (HOLD should be held high any time  
this function is not being used.) HOLD may be tied high  
STATUS REGISTER  
7
6
5
4
3
2
1
0
WPEN  
X
X
BP2  
BP1  
BP0  
WEL  
RDY  
MEMORY PROTECTION  
MEMORY PROTECTION  
CAT25C33  
BP2  
0
BP1  
0
BP0  
0
CAT25C65  
0000-07FF  
0800-0FFF  
1000-17FF  
1800-1FFF  
0000-0FFF  
0000-003F  
0FC0-1FFF  
Non-Protection  
Q1 Protected  
Q2 Protected  
Q3 Protected  
Q4 Protected  
H1 Protected  
P0 Protected  
Pn Protected  
Q1  
Q2  
Q3  
Q4  
H1  
P0  
Pn  
0000-03FF  
0400-07FF  
0800-0BFF  
0C00-0FFF  
0000-07FF  
0000-003F  
0FC0-0FFF  
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
WRITE PROTECT ENABLE OPERATION  
Protected  
Unprotected  
Status  
WPEN  
WP  
X
WEL  
Blocks  
Blocks  
Protected  
Writable  
Protected  
Writable  
Protected  
Writable  
Register  
Protected  
Writable  
0
0
1
1
X
X
0
1
0
1
0
1
Protected  
Protected  
Protected  
Protected  
Protected  
Protected  
X
Low  
Low  
High  
High  
Protected  
Protected  
Protected  
Writable  
Doc No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
5
CAT25C33/65  
directly to Vcc or tied to Vcc through a resistor. Figure  
9 illustrates hold timing sequence.  
lower half of the memory, the first page or the last page by  
setting these bits. Once protected the user may only  
read from the protected portion of the array. These bits are  
non-volatile.  
STATUS REGISTER  
The Status Register indicates the status of the device.  
TheWPEN(WriteProtectEnable)isanenablebitfortheWP  
pin. The WP pin and WPEN bit in the status register control  
theprogrammablehardwarewriteprotectfeature.Hardware  
write protection is enabled when WP is low and WPEN bit  
is set to high. The user cannot write to the status register  
(including the block protect bits and the WPEN bit) and the  
block protected sections in thememory array when the chip  
is hardware write protected. Only the sections of the  
memory array that are not block protected can be written.  
Hardware write protection is disabled when either WP pin is  
high or the WPEN bit is zero.  
TheRDY(Ready)bitindicateswhethertheCAT25C33/  
65 is busy with a write operation. When set to 1 a write  
cycle is in progress and when set to 0 the device  
indicates it is ready. This bit is read only.  
The WEL (Write Enable) bit indicates the status of the  
write enable latch . When set to 1, the device is in a  
Write Enable state and when set to 0 the device is in  
a Write Disable state. The WEL bit can only be set by  
the WREN instruction and can be reset by the WRDI  
instruction.  
DEVICE OPERATION  
The BP0, BP1 and BP2 (Block Protect) bits indicate  
which blocks are currently protected. These bits are  
setbytheuserissuingtheWRSRinstruction. Theuser  
is allowed to protect any quarter of the memory, the  
Write Enable and Disable  
The CAT25C33/65 contains a write enable latch. This latch  
must be set before any write operation. The device powers  
Figure 2. WREN Instruction Timing  
CS  
SK  
1
1
0
SI  
0
0
0
0
0
HIGH IMPEDANCE  
SO  
Note: Dashed Line= mode (1, 1) — — — —  
Figure 3. WRDI Instruction Timing  
CS  
SK  
SI  
1
0
0
0
0
0
0
0
HIGH IMPEDANCE  
SO  
Note: Dashed Line= mode (1, 1) — — — —  
Doc. No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
6
CAT25C33/65  
up in a write disable state when Vcc is applied. WREN and FFFh for 25C33) is reached, the address counter rolls  
instruction will enable writes (set the latch) to the device. over to 0000h allowing the read cycle to be continued  
WRDI instruction will disable writes (reset the latch) to indefinitely. The read operation is terminated by pulling the  
the device. Disabling writes will protect the device CS high. To read the status register, RDSR instruction  
against inadvertent writes.  
should be sent. The contents of the status register are  
shifted out on the SO line. The status register may be read  
at any time even during a write cycle. Read sequece is  
illustrated in Figure 4. Reading status register is illustrated  
in Figure 5.  
READ Sequence  
The part is selected by pulling CS low. The 8-bit read  
instruction is transmitted to the CAT25C33/65, followed  
by the 16-bit address(the three Most Significant Bits are  
don’t care for 25C65 and four most significant bits are WRITE Sequence  
don't care for 25C33). After the correct read instruction TheCAT25C33/65powersupinaWriteDisablestate.Prior  
and address are sent, the data stored in the memory at to any write instructions, the WREN instruction must be  
the selected address is shifted out on the SO pin. The sent to CAT25C33/65. The device goes into Write enable  
data stored in the memory at the next address can be state by pulling the CS low and then clocking the WREN  
read sequentially by continuing to provide clock pulses. instruction into CAT25C33/65. The CS must be brought  
Theinternaladdresspointerisautomaticallyincremented high after the WREN instruction to enable writes to the  
to the next higher address after each byte of data is device.  
shifted out. When the highest address (1FFFh for 25C65  
Figure 4. Read Instruction Timing  
CS  
0
1
2
3
4
5
6
7
8
9
10  
20 21 22 23 24 25 26 27 28 29 30  
SK  
OPCODE  
BYTE ADDRESS*  
SI  
0
0
0
0
0
0
1
1
DATA OUT  
HIGH IMPEDANCE  
SO  
7
6
5
4
3
2
1
0
MSB  
*Please check the instruction set table for address  
Note: Dashed Line= mode (1, 1) — — — —  
Figure 5. RDSR Instruction Timing  
CS  
0
1
2
3
4
5
1
6
0
7
1
8
9
10  
11  
12  
13  
14  
SCK  
OPCODE  
0
0
0
0
0
SI  
DATA OUT  
HIGH IMPEDANCE  
SO  
5
7
6
4
3
2
1
0
MSB  
Note: Dashed Line= mode (1, 1) — — — —  
Doc No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
7
CAT25C33/65  
If the write operation is initiated immediately after the The Status Register can be read to determine if the write cycle  
WREN instruction without CS being brought high, is still in progress. If Bit 0 of the Status Register is set at 1, write  
the data will not be written to the array because the cycle is in progress. If Bit 0 is set at 0, the device is ready for  
write enable latch will not have been properly set. the next instruction.  
Also, for a successful write operation the address of  
the memory location(s) to be programmed must be  
Page Write  
The CAT25C33/65 features page write capability. After the first  
outside the protected address field location selected  
initial byte the host may continue to write up to 64 bytes of data  
by the block protection level.  
to the CAT25C33/65. After each byte of data is received, six  
lower order address bits are internally incremented by one; the  
high order bits of address will remain constant. The only  
restriction is that the 64 bytes must reside on the same page.  
If the address counter reaches the end of the page and clock  
continues, the counter will “roll over” to the first address of the  
page and overwrite any data that may have been written. The  
CAT25C33/65 is automatically returned to the write disable  
state at the completion of the write cycle. Figure 8 illustrates the  
Byte Write  
Once the device is in a Write Enable state, the user  
mayproceedwithawritesequencebysettingtheCS  
low,issuingawriteinstructionviatheSIline,followed  
by the 16-bit address (the three Most Significant Bits  
aredon’tcarefor25C65andfourmostsignificantbits  
are don't care for 25C33), and then the data to be  
written. Programming will start after the CS is  
brought high. Figure 6 illustrates byte write se-  
page write sequence.  
quence.  
To write to the status register, the WRSR instruction should be  
sent. Only Bit 2, Bit 3 and Bit 7 of the status register can be  
During an internal write cycle, all commands will be  
written using the WRSR instruction. Figure 7 illustrates the  
ignored except the RDSR (Read Status Register)  
sequence of writing to status register.  
instruction.  
Figure 6. Write Instruction Timing  
CS  
0
1
2
3
4
5
6
7
8
21 22 23 24 25 26 27 28 29 30 31  
SK  
SI  
OPCODE  
DATA IN  
D7 D6 D5 D4 D3 D2 D1 D0  
0
0
0
0
0
0
1
0
ADDRESS  
HIGH IMPEDANCE  
SO  
Note: Dashed Line= mode (1, 1) – – – –  
Figure 7. WRSR Instruction Timing  
CS  
0
1
2
3
4
5
6
7
1
8
7
9
6
10  
5
11  
4
12  
13  
2
14  
1
15  
0
SCK  
OPCODE  
DATA IN  
SI  
0
0
0
0
0
0
0
3
MSB  
HIGH IMPEDANCE  
SO  
Note: Dashed Line= mode (1, 1) — — — —  
Doc. No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
8
CAT25C33/65  
DESIGN CONSIDERATIONS  
The CAT25C33/65 powers up in a write disable state  
and in a low power standby mode. A WREN instruction  
must be issued to perform any writes to the device after  
power up. Also,on power up CS should be brought low  
to enter a ready state and receive an instruction. After  
a successful byte/page write or status register write the  
CAT25C33/65 goes into a write disable mode. CS must  
be set high after the proper number of clock cycles to  
start an internal write cycle. Access to the array during  
an internal write cycle is ignored and program-ming  
is continued. On power up, SO is in a high impedance.  
When powering down, the supply should be taken down  
to 0V, so that the CAT25C33/65 will be reset when power  
is ramped back up. If this is not possible, then, following  
a brown-out episode, the CAT25C33/65 can be reset by  
refreshing the contents of the Status Register (See Appli-  
cation Note AN10).  
Figure 8. Page Write Instruction Timing  
CS  
24+(N-1)x8-1..24+(N-1)x8 24+Nx8-1  
0
1
2
3
4
5
6
7
8
21 22 23  
32-39  
24-31  
SK  
SI  
DATA IN  
Data Data  
Byte 2 Byte 3  
OPCODE  
Data  
Byte 1  
Data Byte N  
0
0
0
0
0
0
1
0
ADDRESS  
0
7..1  
HIGH IMPEDANCE  
SO  
Note: Dashed Line = mode (1, 1) – – – –  
Figure 9. HOLD Timing  
CS  
t
t
CD  
CD  
SCK  
t
HD  
t
HD  
HOLD  
SO  
t
HZ  
HIGH IMPEDANCE  
t
LZ  
Note: Dashed Line= mode (1, 1) — — — —  
Doc No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
9
CAT25C33/65  
ORDERING INFORMATION  
Prefix  
Device #  
25C65  
Suffix  
-1.8  
S
CAT  
TE13  
I
Product  
Temperature Range  
Tape & Reel  
Optional  
Company ID  
Number  
25C33: 32K  
25C65: 64K  
Operating Voltage  
Blank = 2.5 to 6.0V  
1.8 = 1.8 to 6.0V  
Package  
P: PDIP  
S: SOIC  
U14: 14-pin TSSOP  
L: PDIP (Lead free, Halogen free)  
V: SOIC (Lead free, Halogen free)  
Y14: 14-pin TSSOP (Lead free, Halogen free)  
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)  
GV: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)  
Notes:  
(1) The device used in the above example is a 25C65SI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating Voltage,  
Tape & Reel)  
Doc. No. 1000, Rev. H  
© 2005 by Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
10  
REVISION HISTORY  
Date  
Rev.  
Reason  
8/5/2004  
F
Updated Features  
Updated DC Operating Characteristics table & notes  
07/11/2005  
09/22/2005  
G
H
Update Reliability Characteristic  
Update Ordering Information  
Update Pin Configuration  
Copyrights, Trademarks and Patents  
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:  
DPP ™  
AE2 ™  
MiniPot™  
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents  
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.  
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS  
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE  
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING  
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.  
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or  
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a  
situation where personal injury or death may occur.  
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets  
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.  
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate  
typical semiconductor applications and may not be complete.  
Catalyst Semiconductor, Inc.  
Corporate Headquarters  
1250 Borregas Avenue  
Sunnyvale, CA 94089  
Phone: 408.542.1000  
Publication #: 1000  
Fax: 408.542.1200  
Revison:  
H
www.caalyst-semiconductor.com  
Issue date:  
09/22/05  

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