CAT28F512NA-15T [CATALYST]
512K-Bit CMOS Flash Memory; 512K位CMOS闪存
| 型号： | CAT28F512NA-15T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | 512K-Bit CMOS Flash Memory |
| 文件： | 总15页 (文件大小：428K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT28F512
512K-Bit CMOS Flash Memory
Licensed Intel second source
TM
FEATURES
I Commercial, Industrial and Automotive
I Fast Read Access Time: 90/120/150 ns
Temperature Ranges
I Low Power CMOS Dissipation:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100 µA max (CMOS levels)
I Stop Timer for Program/Erase
I On-Chip Address and Data Latches
I JEDEC Standard Pinouts:
–32-pin DIP
I High Speed Programming:
–10 µs per byte
–32-pin PLCC
–32-pin TSOP ( 8 x 20)
–1 Sec Typ Chip Program
I 12.0V 5% Programming and Erase Voltage
I Electronic Signature
I 100,000 Program/Erase Cycles
I 10 Year Data Retention
I "Green" Package Options Available
DESCRIPTION
two write cycle scheme. Address and Data are latched
to free the I/O bus and address bus during the write
operation.
The CAT28F512 is a high speed 64K x 8-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
The CAT28F512 is manufactured using Catalyst’s ad-
vanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 32-pin plastic DIP, 32-pin PLCC or 32-pin
TSOP packages.
It is pin and Read timing compatible with standard
EPROMandEEPROMdevices.ProgrammingandErase
are performed through an operation and verify algo-
rithm. The instructions are input via the I/O bus, using a
BLOCK DIAGRAM
I/O –I/O
0
7
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
DATA
LATCH
SENSE
AMP
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
CE
OE
Y-GATING
Y-DECODER
524,288 BIT
MEMORY
ARRAY
A –A
0
15
X-DECODER
VOLTAGE VERIFY
SWITCH
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1084, Rev. H
1
CAT28F512
PIN CONFIGURATION
PIN FUNCTIONS
Pin Name
Type
Function
A0–A15
Input
Address Inputs for
memory addressing
DIP Package (P, L)
PLCC Package (N, G)
I/O0–I/O7
CE
I/O
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
Input
Input
Input
V
1
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
PP
NC
2
WE
OE
4
3 2 1 32 31 30
A
3
N/C
15
12
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
7
6
5
4
3
2
1
0
0
14
13
8
A
4
A
A
A
A
A
14
13
8
WE
A
5
7
6
A
A
6
A
9
11
A
7
VCC
5
9
A
A
8
4
11
10
11
12
13
A
OE
A
9
OE
3
VSS
A
A
10
CE
A
10
11
12
13
14
15
16
A
2
10
CE
A
I/O
A
1
I/O
7
VPP
Program/Erase
Voltage Supply
14 15 16 17 18 19 20
A
I/O
I/O
I/O
I/O
I/O
0
7
6
5
4
3
I/O
I/O
I/O
0
1
2
V
SS
28F512 F01
TSOP Package (Standard Pinout 8mm x 20mm) (T, H)
A
A
A
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
11
9
8
A
A
NC
I/O
I/O
I/O
I/O
I/O
13
14
7
6
5
4
3
WE
V
V
CC
PP
NC
9
V
SS
10
11
12
13
14
15
16
I/O
I/O
I/O
2
1
0
A
A
15
12
A
A
A
A
A
A
A
A
7
6
5
4
0
1
2
3
TSOP Package (Reverse Pinout) (TR, HR)
OE
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
A
A
A
NC
WE
V
11
9
8
13
14
A
CE
10
I/O
7
6
5
4
3
I/O
I/O
I/O
I/O
CC
9
V
V
PP
NC
SS
10
11
12
13
14
15
16
I/O
I/O
I/O
A
A
A
2
1
0
0
1
2
3
A
A
A
A
A
A
15
12
7
6
5
A
4
28F512 F03
Doc. No. 1084, Rev. H
2
CAT28F512
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................... –55°C to +95°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground(1) ................... –2.0V to +13.5V
V
PP with Respect to Ground
during Program/Erase(1) .............. –2.0V to +14.0V
VCC with Respect to Ground(1) ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100K
10
Max.
Units
Cycles/Byte
Years
Test Method
(3)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
100
Volts
(3)(4)
ILTH
mA
CAPACITANCE T = 25°C, f = 1.0 MHz
A
Limits
Max.
6
Symbol
Test
Min
Units
pF
Conditions
VIN = 0V
(3)
CIN
Input Pin Capacitance
Output Pin Capacitance
VPP Supply Capacitance
(3)
COUT
10
25
pF
VOUT = 0V
VPP = 0V
(3)
CVPP
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1084, Rev. H
3
CAT28F512
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V 10%, unless otherwise specified.
Limits
Max.
1
Symbol
Parameter
Min.
Unit
Test Conditions
ILI
Input Leakage Current
µA
VIN = VCC or VSS
VCC = 5.5V, OE = VIH
ILO
Output Leakage Current
1
µA
µA
VOUT = VCC or VSS,
VCC = 5.5V, OE = VIH
ISB1
VCC Standby Current CMOS
100
CE = VCC 0.5V,
VCC = 5.5V
ISB2
ICC1
VCC Standby Current TTL
VCC Active Read Current
1
mA
mA
CE = VIH, VCC = 5.5V
30
VCC = 5.5V, CE = VIL,
IOUT = 0mA, f = 6 MHz
(1)
ICC2
VCC Programming Current
VCC Erase Current
15
15
15
mA
mA
mA
VCC = 5.5V,
Programming in Progress
(1)
ICC3
VCC = 5.5V,
Erasure in Progress
(1)
ICC4
VCC Prog./Erase Verify Current
VCC = 5.5V, Program or
Erase Verify in Progress
IPPS
IPP1
VPP Standby Current
VPP Read Current
10
200
30
µA
µA
VPP = VPPL
VPP = VPPH
(1)
IPP2
VPP Programming Current
mA
VPP = VPPH
,
Programming in Progress
(1)
IPP3
VPP Erase Current
30
5
mA
mA
VPP = VPPH,
Erasure in Progress
(1)
IPP4
VPP Prog./Erase Verify Current
VPP = VPPH, Program or
Erase Verify in Progress
VIL
Input Low Level TTL
–0.5
–0.5
0.8
0.8
V
V
VILC
VOL
VIH
Input Low Level CMOS
Output Low Level
0.45
V
IOL = 5.8mA, VCC = 4.5V
Input High Level TTL
Input High Level CMOS
Output High Level TTL
Output High Level CMOS
A9 Signature Voltage
A9 Signature Current
VCC Erase/Prog. Lockout Voltage
2
VCC+0.5
VCC+0.5
V
VIHC
VOH1
VOH2
VID
VCC*0.7
2.4
V
V
IOH = –2.5mA, VCC = 4.5V
IOH = –400µA, VCC = 4.5V
A9 = VID
VCC–0.4
11.4
V
13
V
(1)
IID
200
µA
V
A9 = VID
VLO
2.5
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. 1084, Rev. H
4
CAT28F512
SUPPLY CHARACTERISTICS
Symbol
Limits
Parameter
Min
4.5
0
Max.
5.5
Unit
V
VCC
VCC Supply Voltage
VPPL
VPPH
VPP During Read Operations
6.5
V
VPP During Read/Erase/Program
11.4
12.6
V
A.C. CHARACTERISTICS, Read Operation
= +5V 10%, unless otherwise specified.
V
CC
JEDEC Standard
Symbol Symbol
28F512-90 28F512-12 28F512-15
Parameter
Min. Max. Min. Max. Min. Max. Unit
tAVAV
tELQV
tAVQV
tGLQV
tAXQX
tGLQX
tELQX
tGHQZ
tEHQZ
tWHGL
tRC
tCE
Read Cycle Time
90
120
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
CE Access Time
90
90
35
120
120
50
150
150
55
tACC
tOE
tOH
Address Access Time
OE Access Time
Output Hold from Address OE/CE Change
OE to Output in Low-Z
CE to Output in Low-Z
OE High to Output High-Z
CE High to Output High-Z
Write Recovery Time Before Read
0
0
0
0
0
0
0
0
0
(1)(6)
tOLZ
(1)(6)
tLZ
tDF
tDF
-
(1)(2)
(1)(2)
20
30
30
40
35
45
(1)
6
6
6
(3)(4)(5)
Figure 1. A.C. Testing Input/Output Waveform
2.4 V
2.0 V
0.8 V
INPUT PULSE LEVELS
0.45 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
= 100 pF
L
C
INCLUDES JIG CAPACITANCE
L
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V.
(5) Input and Output Timing Reference = 0.8V and 2.0V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
Doc. No. 1084, Rev. H
5
CAT28F512
A.C. CHARACTERISTICS, Program/Erase Operation
V
CC
= +5V 10%, unless otherwise specified.
JEDEC Standard
Symbol Symbol
28F512-90 28F512-12 28F512-15
Parameter
Min. Max. Min. Max. Min. Max. Unit
tAVAV
tWC
tAS
tAH
tDS
tDH
tCS
tCH
tWP
tWPH
-
Write Cycle Time
90
0
120
0
150
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
µs
µs
ns
tAVWL
tWLAX
tDVWH
tWHDX
tELWL
Address Setup Time
Address Hold Time
Data Setup Time
40
40
10
0
40
40
10
0
40
40
10
0
Data Hold Time
CE Setup Time
tWHEH
tWLWH
tWHWL
tWHWH1
tWHWH2
tWHGL
tGHWL
tVPEL
CE Hold Time
0
0
0
WE Pulse Width
40
20
10
9.5
6
40
20
10
9.5
6
40
20
10
9.5
6
WE High Pulse Width
Program Pulse Width
Erase Pulse Width
Write Recovery Time Before Read
Read Recovery Time Before Write
VPP Setup Time to CE
(2)
(2)
-
-
-
0
0
0
-
100
100
100
(1)
ERASE AND PROGRAMMING PERFORMANCE
28F512-90
28F512-12
28F512-15
Parameter
Min. Typ. Max.
Min. Typ. Max.
Min. Typ. Max.
Unit
sec
sec
Chip Erase Time(3)(5)
Chip Program Time(3)(4)
0.5
1
10
6
0.5
1
10
6
0.5
1
10
6
Note:
(1) Please refer to Supply characteristics for the value of V
and V
. The V supply can be either hardwired or switched. If V is switched,
PPL PP PP
PPH
V
can be ground, less than V + 2.0V or a no connect with a resistor tied to ground.
PPL
CC
(2) Program and Erase operations are controlled by internal stop timers.
(3) ‘Typicals’ are not guaranteed, but based on characterization data. Data taken at 25°C, 12.0V V
.
PP
(4) Minimum byte programming time (excluding system overhead) is 16 µs (10 µs program + 6 µs write recovery), while maximum is 400 µs/
byte (16 µs x 25 loops). Max chip programming time is specified lower than the worst case allowed by the programming algorithm since
most bytes program significantly faster than the worst case byte.
(5) Excludes 00H Programming prior to Erasure.
Doc. No. 1084, Rev. H
6
CAT28F512
(1)
FUNCTION TABLE
Pins
WE
VIH
Mode
Read
CE
VIL
VIL
VIH
VIL
VIL
VIL
VIL
VIL
OE
VIL
VIH
X
VPP
VPPL
X
I/O
DOUT
High-Z
High-Z
31H
Notes
Output Disable
Standby
VIH
X
VPPL
X
Signature (MFG)
Signature (Device)
Program/Erase
Write Cycle
VIL
VIL
VIH
VIH
VIL
VIH
VIH
VIL
VIL
VIH
A0 = VIL, A9 = 12V
A0 = VIH, A9 = 12V
See Command Table
During Write Cycle
During Write Cycle
X
B8H
VPPH
VPPH
VPPH
DIN
DIN
Read Cycle
DOUT
WRITE COMMAND TABLE
Commands are written into the command register in one or two write cycles. The command register can be altered
only when V is high and the instruction byte is latched on the rising edge of WE. Write cycles also internally latch
PP
addresses and data required for programming and erase operations.
Pins
First Bus Cycle
Second Bus Cycle
Mode
Set Read
Operation
Address
DIN
00H
90H
90H
20H
A0H
40H
C0H
FFH
Operation
Read
Address
DIN
DOUT
DOUT
31H
Write
Write
Write
Write
Write
Write
Write
Write
X
X
AIN
00
01
X
Read Sig. (MFG)
Read Sig. (Device)
Erase
Read
X
Read
B8H
X
Write
20H
DIN
Erase Verify
Program
AIN
X
Read
X
DOUT
Write
AIN
X
Program Verify
Reset
X
Read
DOUT
X
Write
X
FFH
Note:
(1) Logic Levels: X = Logic ‘Do not care’ (V , V , V
, V )
PPL PPH
IH
IL
Doc. No. 1084, Rev. H
7
CAT28F512
READ OPERATIONS
Read Mode
The conventional mode is entered as a regular READ
mode by driving the CE and OE pins low (with WE high),
andapplyingtherequiredhighvoltageonaddresspinA9
while all other address lines are held at VIL.
A Read operation is performed with both CE and OE low
and with WE high. VPP can be either high or low,
however, if VPP is high, the Set READ command has to
be sent before reading data (see Write Operations). The
data retrieved from the I/O pins reflects the contents of
thememorylocationcorrespondingtothestateofthe16
address pins. The respective timing waveforms for the
read operation are shown in Figure 3. Refer to the AC
Read characteristics for specific timing parameters.
A Read cycle from address 0000H retrieves the binary
code for the IC manufacturer on outputs I/O0 to I/O7:
CATALYST Code = 00110001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
Signature Mode
The signature mode allows the user to identify the IC
manufacturer and the type of device while the device
residesinthetargetsystem. Thismodecanbeactivated
in either of two ways; through the conventional method
of applying a high voltage (12V) to address pin A9 or by
sending an instruction to the command register (see
Write Operations).
28F512 Code = 1011 1000 (B8H)
Standby Mode
With CE at a logic-high level, the CAT28F512 is placed
in a standby mode where most of the device circuitry is
disabled, thereby substantially reducing power con-
sumption. The outputs are placed in a high-impedance
state.
Figure 3. A.C. Timing for Read Operation
STANDBY
DEVICE AND
OUPUTS
DATA VALID
STANDBY
POWER DOWN
POWER UP
ADDRESS SELECTION
ENABLED
ADDRESS STABLE
ADDRESSES
CE (E)
t
(t
AVAV RC
)
t
(t
)
)
EHQZ DF
OE (G)
t
t
(t
WHGL
GHQZ DF
t
(t
)
WE (W)
GLQV OE
t
(t
ELQV CE
)
t
(t
AXQX OH
)
t
(t
)
GLQX OLZ
t
(t
)
ELQX LZ
HIGH-Z
HIGH-Z
OUTPUT VALID
DATA (I/O)
t
(t
)
AVQV ACC
Doc. No. 1084, Rev. H
8
CAT28F512
Erase Mode
WRITE OPERATIONS
During the first Write cycle, the command 20H is written
into the command register. In order to commence the
eraseoperation,theidenticalcommandof20Hhastobe
written again into the register. This two-step process
ensures against accidental erasure of the memory con-
tents. The final erase cycle will be stopped at the rising
edge of WE, at which time the Erase Verify command
(A0H)issenttothecommandregister. Duringthiscycle,
the address to be verified is sent to the address bus and
latched when WE goes low. An integrated stop timer
allows for automatic timing control over this operation,
eliminating the need for a maximum erase timing speci-
fication. Refer to AC Characteristics (Program/Erase)
for specific timing parameters.
The following operations are initiated by observing the
sequence specified in the Write Command Table.
Read Mode
The device can be put into a standard READ mode by
initiating a write cycle with 00H on the data bus. The
subsequent read cycles will be performed similar to a
standard EPROM or EEPROM Read.
Signature Mode
An alternative method for reading device signature (see
Read Operations Signature Mode), is initiated by writing
the code 90H into the command register while keeping
VPP high. A read cycle from address 0000H with CE and
OE low (and WE high) will output the device signature.
CATALYST Code = 00110001 (31H)
A Read cycle from address 0001H retrieves the binary
code for the device on outputs I/O0 to I/O7.
28F512 Code = 1011 1000 (B8H)
Figure 4. A.C. Timing for Erase Operation
SETUP ERASE
COMMAND
ERASE
COMMAND
ERASING
ERASE VERIFY
COMMAND
ERASE
VERIFICATION
V
POWER-DOWN/
STANDBY
V
POWER-UP
CC
CC
& STANDBY
ADDRESSES
CE (E)
t
t
t
t
WC
WC
WC
RC
t
t
AS
AH
t
t
CH
CS
t
t
CH
EHQZ
t
t
CS
CH
OE (G)
t
GHWL
t
t
t
WHGL
DF
WHWH2
t
WPH
WE (W)
t
t
t
t
OE
WP
WP
WP
t
t
t
t
t
DH
DH
DH
OH
t
t
OLZ
t
DS
DS
DS
HIGH-Z
DATA IN
= 20H
DATA IN
= 20H
DATA IN
= A0H
DATA (I/O)
VALID
t
t
LZ
CE
DATA OUT
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
Doc. No. 1084, Rev. H
9
CAT28F512
(1)
Figure 5. Chip Erase Algorithm
BUS
OPERATION
START ERASURE
COMMAND
COMMENTS
RAMPS TO V
V
PP
(OR V
PPH
APPLY V
PPH
HARDWIRED)
PP
ALL BYTES SHALL BE
PROGRAMMED TO 00
BEFORE AN ERASE
OPERATION
PROGRAM ALL
BYTES TO 00H
STANDBY
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE
PLSCNT = 0
PLSCNT = PULSE COUNT
WRITE ERASE
SETUP COMMAND
WRITE
WRITE
ERASE
ERASE
DATA = 20H
WRITE ERASE
COMMAND
DATA = 20H
WAIT
TIME OUT 10ms
ADDRESS = BYTE TO VERIFY
WRITE ERASE
VERIFY COMMAND
ERASE
VERIFY
WRITE
DATA =
A0H
STOPS ERASE OPERATION
TIME OUT 6µs
WAIT
INCREMENT
ADDRESS
READ DATA
FROM DEVICE
READ
READ BYTE TO
VERIFY ERASURE
NO
NO
DATA =
FFH?
INC PLSCNT
1000
= 30 ?
COMPARE OUTPUT TO FF
INCREMENT PULSE COUNT
STANDBY
YES
YES
LAST
NO
ADDRESS?
YES
DATA = 00H
RESETS THE REGISTER
FOR READ OPERATION
WRITE READ
COMMAND
WRITE
READ
V
RAMPS TO V
PPL
PP
(OR V
APPLY V
PPL
APPLY V
PPL
STANDBY
HARDWIRED)
PP
ERASURE
COMPLETED
ERASE
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 1084, Rev. H
10
CAT28F512
Erase-Verify Mode
Program-Verify Mode
The Erase-verify operation is performed on every byte
after each erase pulse to verify that the bits have been
erased.
A Program-verify cycle is performed to ensure that all
bits have been correctly programmed following each
byte programming operation. The specific address is
already latched from the write cycle just completed, and
stayslatcheduntiltheverifyiscompleted. TheProgram-
verify operation is initiated by writing C0H into the
command register. An internal reference generates the
necessary high voltages so that the user does not need
to modify VCC. Refer to AC Characteristics (Program/
Erase) for specific timing parameters.
Programming Mode
The programming operation is initiated using the pro-
gramming algorithm of Figure 7. During the first write
cycle, the command 40H is written into the command
register. During the second write cycle, the address of
thememorylocationtobeprogrammedislatchedonthe
falling edge of WE, while the data is latched on the rising
edge of WE. The program operation terminates with the
next rising edge of WE. An integrated stop timer allows
forautomatictimingcontroloverthisoperation, eliminat-
ing the need for a maximum program timing specifica-
tion. Refer to AC Characteristics (Program/Erase) for
specific timing parameters.
Figure 6. A.C. Timing for Programming Operation
SETUP PROGRAM LATCH ADDRESS
POWER-UP
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
V
POWER-DOWN/
STANDBY
V
CC
CC
& STANDBY
COMMAND
& DATA
PROGRAMMING
ADDRESSES
CE (E)
t
t
t
WC
WC
RC
t
t
AS
AH
t
t
CH
CS
t
t
CH
EHQZ
t
t
CS
CH
OE (G)
t
GHWL
t
t
t
DF
WHWH1
WHGL
t
WPH
WE (W)
t
t
t
t
WP
WP
WP
t
OE
t
t
t
t
DH
DH
DH
OH
t
t
t
DS
DS
OLZ
DS
HIGH-Z
DATA IN
= 40H
DATA IN
= C0H
DATA (I/O)
DATA IN
VALID
t
t
LZ
CE
DATA OUT
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
Doc. No. 1084, Rev. H
11
CAT28F512
(1)
Figure 7. Programming Algorithm
START
PROGRAMMING
BUS
OPERATION
COMMAND
COMMENTS
RAMPS TO V
V
APPLY V
PPH
PP
(OR V
PPH
STANDBY
HARDWIRED)
PP
INITIALIZE
ADDRESS
INITIALIZE ADDRESS
INITIALIZE PULSE COUNT
PLSCNT = PULSE COUNT
PLSCNT = 0
WRITE SETUP
PROG. COMMAND
1ST WRITE
CYCLE
WRITE
SETUP
DATA = 40H
WRITE PROG. CMD
ADDR AND DATA
2ND WRITE
CYCLE
PROGRAM VALID ADDRESS AND DATA
TIME OUT 10µs
WAIT
WRITE PROGRAM
VERIFY COMMAND
1ST WRITE
CYCLE
PROGRAM
DATA = C0H
VERIFY
TIME OUT 6µs
WAIT
READ DATA
FROM DEVICE
READ BYTE TO VERIFY
PROGRAMMING
READ
NO
INC
PLSCNT
= 25 ?
NO
VERIFY
DATA ?
COMPARE DATA OUTPUT
TO DATA EXPECTED
STANDBY
YES
YES
LAST
ADDRESS?
NO
INCREMENT
ADDRESS
YES
DATA = 00H
SETS THE REGISTER FOR
READ OPERATION
WRITE READ
COMMAND
1ST WRITE
CYCLE
READ
V
RAMPS TO V
APPLY V
PPL
APPLY V
PPL
PP
(OR V
PPL
STANDBY
HARDWIRED)
PP
PROGRAMMING
COMPLETED
PROGRAM
ERROR
Note:
(1) The algorithm MUST BE FOLLOWED to ensure proper and reliable operation of the device.
Doc. No. 1084, Rev. H
12
CAT28F512
Abort/Reset
POWER UP/DOWN PROTECTION
An Abort/Reset command is available to allow the user
to safely abort an erase or program sequence. Two
consecutive program cycles with FFH on the data bus
will abort an erase or a program operation. The abort/
reset operation can interrupt at any time in a program or
erase operation and the device is reset to the Read
Mode.
The CAT28F512 offers protection against inadvertent
programming during VPP and VCC power transitions.
When powering up the device there is no power-on
sequencing necessary. In other words, VPP and VCC
may power up in any order. Additionally VPP may be
hardwired to VPPH independent of the state of VCC and
any power up/down cycling. The internal command
register of the CAT28F512 is reset to the Read Mode on
power up.
POWER SUPPLY DECOUPLING
To reduce the effect of transient power supply voltage
spikes, it is good practice to use a 0.1µF ceramic
capacitorbetweenVCC andVSS andVPP andVSS.These
high-frequency capacitors should be placed as close as
possible to the device for optimum decoupling.
Figure 8. Alternate A.C. Timing for Program Operation
SETUP PROGRAM LATCH ADDRESS
POWER-UP
PROGRAM
VERIFY
COMMAND
PROGRAM
VERIFICATION
V
POWER-DOWN/
STANDBY
V
CC
CC
& STANDBY
COMMAND
& DATA
PROGRAMMING
ADDRESSES
WE (E)
t
t
t
WC
WC
RC
t
t
ELAX
AVEL
t
t
WLEL
EHWH
t
t
t
EHWH
EHQZ
WLEL
t
t
WLEL
EHWH
OE (G)
CE (W)
t
t
t
t
EHEH
EHGL
DF
GHEL
t
EHEL
t
t
t
ELEH
ELEH
EHDX
OE
t
t
t
t
t
EHDX
EHDX
OLZ
OH
t
t
t
DVEH
DVEH
DVEH
HIGH-Z
DATA IN
= 40H
DATA IN
= C0H
DATA (I/O)
DATA IN
VALID
t
t
LZ
CE
DATA OUT
5.0V
0V
V
CC
t
VPEL
V
V
PPH
PPL
V
PP
Doc. No. 1084, Rev. H
13
CAT28F512
ALTERNATE CE-CONTROLLED WRITES
JEDEC Standard
28F512-90 28F512-12 28F512-15
Symbol Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tAVAV
tAVEL
tELAX
tDVEH
tEHDX
tEHGL
tGHEL
tWLEL
tEHWH
tELEH
tEHEL
tVPEL
tWC
tAS
tAH
tDS
tDH
-
Write Cycle Time
90
0
120
0
120
0
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
Address Setup Time
Address Hold Time
40
40
10
6
40
40
10
6
40
40
10
6
Data Setup Time
Data Hold Time
Write Recovery Time Before Read
Read Recovery Time Before Write
WE Setup Time Before CE
WE Hold Time After CE
Write Pulse Width
-
0
0
0
tWS
-
0
0
0
0
0
0
tCP
tCPH
-
40
20
100
40
20
100
40
20
100
Write Pulse Width High
VPP Setup Time to CE Low
ORDERING INFORMATION
Prefix
Device #
Suffix
CAT
28F512
N
-90
T
I
Product
Number
Temperature Range
Tape & Reel
T: 500/Reel
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚C to +105˚C)*
Package
N: PLCC
P: PDIP
Speed
Optional
Company ID
90: 90ns
12: 120ns
15: 150ns
T: TSOP (8mmx20mm)
TR: TSOP (Reverse Pinout)
G: PLCC (Lead free, Halogen free)
L: PDIP (Lead free, Halogen free)
H: TSOP (Lead free, Halogen free)
HR: TSOP (Reverse Pinout)
(Lead free, Halogen free)
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a CAT28F512NI-90T (PLCC, Industrial Temperature, 90ns Access Time, Tape & Reel)
Doc. No. 1084, Rev. H
14
REVISION HISTORY
Date
Revision Comments
04/20/04
G
Added Green packages in all areas.
Delete data sheet designation
Update Features
Update Description
Update Pin Configuration
Update Write Operations
Update Ordering Information
Update Revision History
Update Rev Number
07/02/04
H
Update Ordering Information
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP ™
AE2 ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Publication #: 1084
Revison:
H
Issue date:
7/2/04
www.catalyst-semiconductor.com
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