CAT28LV256NA-25T [CATALYST]
x8 EEPROM ; X8 EEPROM\n
| 型号： | CAT28LV256NA-25T |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | x8 EEPROM
|
| 文件： | 总10页 (文件大小：56K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CAT28LV256
256K-Bit CMOS PARALLEL E2PROM
FEATURES
■ CMOS and TTL Compatible I/O
■ 3.0V to 3.6V Supply
■ Automatic Page Write Operation:
– 1 to 64 Bytes in 10ms
■ Read Access Times: 200/250/300 ns
■ Low Power CMOS Dissipation:
– Active: 15 mA Max.
– Page Load Timer
■ End of Write Detection:
– Toggle Bit
– Standby: 150 µA Max.
■ Simple Write Operation:
– DATA Polling
– On-Chip Address and Data Latches
– Self-Timed Write Cycle with Auto-Clear
■ Hardware and Software Write Protection
■ 100,000 Program/Erase Cycles
■ 100 Year Data Retention
■ Fast Write Cycle Time:
– 10ms Max.
■ Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28LV256 is manufactured using Catalyst’s
advancedCMOSfloatinggatetechnology.Itisdesigned
to endure 100,000 program/erase cycles and has a data
retentionof100years.ThedeviceisavailableinJEDEC–
approved 28-pin DIP, 28-pin TSOP or 32-pin PLCC
packages.
The CAT28LV256 is a fast, low power, low voltage
CMOS Parallel E2PROM organized as 32K x 8-bits. It
requires a simple interface for in-system programming.
On-chipaddressanddatalatches, self-timedwritecycle
with auto-clear and VCC power up/down write protection
eliminate additional timing and protection hardware.
DATA Polling and Toggle status bits signal the start and
end of the self-timed write cycle. Additionally, the
CAT28LV256 features hardware and software write
protection.
BLOCK DIAGRAM
32,768 x 8
E2PROM
ARRAY
ROW
DECODER
ADDR. BUFFER
A –A
6
14
& LATCHES
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
64 BYTE PAGE
REGISTER
V
CC
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING
AND
TIMER
TOGGLE BIT
I/O –I/O
0
7
ADDR. BUFFER
& LATCHES
A –A
COLUMN
DECODER
0
5
28LV256 F01
Doc. No. 25040-00 4/01 P-1
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT28LV256
PIN CONFIGURATION
PLCC Package (N)
DIP Package (P)
A
A
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
14
12
2
A
3
A
4
3 2 1 32 31 30
7
6
5
4
3
2
1
0
0
1
2
13
5
6
7
8
9
29
28
27
26
25
24
23
22
21
A
A
A
A
A
A
A
A
A
A
A
4
A
8
A
9
6
5
4
3
2
1
0
8
A
5
9
A
6
A
11
11
NC
OE
A
A
7
OE
TOP VIEW
A
8
A
10
10
11
12
13
A
9
CE
10
CE
I/O
A
10
11
12
13
14
I/O
7
I/O
6
I/O
5
I/O
4
NC
I/O
I/O
I/O
I/O
V
7
I/O
0
6
14 15 16 17 18 19 20
I/O
3
SS
28LV256 F02
TSOP Top View (8mm X 13.4mm) (T13)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE
1
2
3
4
5
6
7
8
A
10
A
A
A
A
13
WE
CE
I/O
I/O
I/O
I/O
I/O
11
9
8
7
6
5
4
3
V
CC
A
GND
14
12
7
A
A
9
I/O
I/O
1
I/O
2
10
11
12
13
14
A
A
A
A
6
5
4
3
0
A
0
A
1
A
2
28LV256 F03
PIN FUNCTIONS
Pin Name
Function
Pin Name
WE
Function
A0–A14
I/O0–I/O7
CE
Address Inputs
Data Inputs/Outputs
Chip Enable
Write Enable
3.0 to 3.6 V Supply
Ground
VCC
VSS
OE
Output Enable
NC
No Connect
Doc. No. 25040-00 4/01 P-1
2
CAT28LV256
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
Voltage on Any Pin with
Respect to Ground(2) ........... –2.0V to +VCC + 2.0V
V
CC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(3) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
100,000
100
Max.
Units
Cycles/Byte
Years
Test Method
(1)
NEND
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
100
Volts
(1)(4)
ILTH
mA
CAPACITANCE T = 25°C, f = 1.0 MHz
A
Symbol
Test
Max.
Units
Conditions
VI/O = 0V
VIN = 0V
(1)
CI/O
Input/Output Capacitance
Input Capacitance
10
6
pF
pF
(1)
CIN
MODE SELECTION
Mode
CE
WE
OE
L
I/O
DOUT
DIN
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Read
L
H
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
L
H
L
X
H
H
DIN
H
X
X
High-Z
High-Z
H
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V +1V.
CC
Doc. No. 25040-00 4/01 P-1
3
CAT28LV256
D.C. OPERATING CHARACTERISTICS
VCC = 3.0V to 3.6V, unless otherwise specified
Limits
Typ.
Symbol Parameter
Min.
Max. Units
Test Conditions
ICC
VCC Current (Operating, TTL)
15
mA
CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
(2)
ISBC
VCC Current (Standby, CMOS)
150
µA
CE = VIHC,
All I/O’s Open
ILI
Input Leakage Current
Output Leakage Current
–1
–5
1
5
µA
µA
VIN = GND to VCC
ILO
VOUT = GND to VCC,
CE = VIH
(2)
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
2
–0.3
2
VCC +0.3
0.6
V
V
V
V
V
VOH
VOL
VWI
IOH = –100µA
0.3
IOL = 1.0mA
2
A.C. CHARACTERISTICS, Read Cycle
VCC = 3.0V to 3.6V, unless otherwise specified
28LV256-20
28LV256-25
28LV256-30
Symbol
tRC
Parameter
Min.
Max. Min. Max.
Min. Max. Units
Read Cycle Time
200
250
300
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCE
CE Access Time
200
200
80
250
250
100
300
300
110
tAA
Address Access Time
OE Access Time
tOE
(1)
tLZ
CE Low to Active Output
OE Low to Active Output
CE High to High-Z Output
OE High to High-Z Output
0
0
0
0
0
0
(1)
tOLZ
(1)(3)
tHZ
50
50
55
55
60
60
(1)(3)
tOHZ
(1)
tOH
Output Hold from Address Change
0
0
0
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) V = V –0.3V to V +0.3V.
IHC
CC
CC
(3) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.
Doc. No. 25040-00 4/01 P-1
4
CAT28LV256
(2)
Figure 1. A.C. Testing Input/Output Waveform
V
- 0.3V
CC
2.0 V
0.6 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.0 V
28LV256 F04
Figure 2. A.C. Testing Load Circuit (example)
Vcc
1.8K
DEVICE
UNDER
TEST
OUTPUT
= 100 pF
1.3K
C
L
C
L
INCLUDES JIG CAPACITANCE
28LV256 F05
A.C. CHARACTERISTICS, Write Cycle
V
CC = 3.0V to 3.6V, unless otherwise specified
28LV256-20 28LV256-25 28LV256-30
Symbol
tWC
Parameter
Min. Max. Min. Max. Min. Max. Units
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
10
10
10
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
tAS
0
100
0
0
100
0
0
100
0
tAH
tCS
tCH
CE Hold Time
0
0
0
(3)
tCW
CE Pulse Time
150
0
150
0
150
0
tOES
tOEH
OE Setup Time
OE Hold Time
0
0
0
(3)
tWP
WE Pulse Width
Data Setup Time
Data Hold Time
150
50
0
150
50
0
150
50
0
tDS
tDH
(1)
tINIT
Write Inhibit Period After Power-up
Byte Load Cycle Time
5
10
5
10
5
10
(1)(4)
tBLC
0.15
100 0.15
100 0.15 100
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Input rise and fall times (10% and 90%) < 10 ns.
(3) A write pulse of less than 20ns duration will not initiate a write cycle.
(4) A timer of duration t
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;
BLC
however a transition from HIGH to LOW within t
max. stops the timer.
BLC
Doc. No. 25040-00 4/01 P-1
5
CAT28LV256
Byte Write
DEVICE OPERATION
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either
WE or CE, with the address input being latched on the
falling edge of WE or CE, whichever occurs last. Data,
conversely, is latched on the rising edge of WE or CE,
whichever occurs first. Once initiated, a byte write cycle
automatically erases the addressed byte and the new
data is written within 10 ms.
Read
Data stored in the CAT28LV256 is transferred to the
data bus when WE is held high, and both OE and CE are
held low. The data bus is set to a high impedance state
when either CE or OE goes high. This 2-line control
architecture can be used to eliminate bus contention in
a system environment.
Figure 3. Read Cycle
t
RC
ADDRESS
CE
t
CE
t
OE
OE
V
IH
t
WE
LZ
t
OHZ
t
t
HZ
DATA VALID
t
OH
OLZ
HIGH-Z
DATA OUT
DATA VALID
t
AA
28LV256 F06
Figure 4. Byte Write Cycle [WE Controlled]
t
WC
ADDRESS
t
t
AH
AS
t
t
CH
CS
CE
OE
WE
t
t
t
OEH
OES
WP
t
BLC
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
28LV256 F07
Doc. No. 25040-00 4/01 P-1
6
CAT28LV256
Page Write
(which can be loaded in any order) during the first and
subsequent write cycles. Each successive byte load
cycle must begin within tBLC MAX of the rising edge of the
preceding WE pulse. There is no page write window
The page write mode of the CAT28LV256 (essentially
an extended BYTE WRITE mode) allows from 1 to 64
bytesofdatatobeprogrammedwithinasingleE2PROM
write cycle. This effectively reduces the byte-write time
by a factor of 64.
limitation as long as WE is pulsed low within tBLC MAX
.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal auto-
matic program cycle to commence. This programming
cycle consists of an erase cycle, which erases any data
that existed in each addressed cell, and a write cycle,
whichwritesnewdatabackintothecell. Apagewritewill
only write data to the locations that were addressed and
will not rewrite the entire page.
FollowinganinitialWRITEoperation(WEpulsedlow,for
tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address
anddatabytesintoa64bytetemporarybuffer. Thepage
address where data is to be written, specified by bits A6
to A14, is latched on the last falling edge of WE. Each
byte within the page is defined by address bits A0 to A5
Figure 5. Byte Write Cycle [CE Controlled]
t
WC
ADDRESS
t
t
t
BLC
AS
AH
t
CW
CE
OE
WE
t
OEH
t
OES
t
t
CH
CS
HIGH-Z
DATA OUT
DATA IN
DATA VALID
DS
t
t
DH
28LV256 F08
Figure 6. Page Mode Write Cycle
OE
CE
WE
t
t
BLC
WP
ADDRESS
I/O
t
WC
LAST BYTE
BYTE n+2
BYTE 0 BYTE 1
BYTE 2
7
BYTE n
BYTE n+1
28LV256 F09
Doc. No. 25040-00 4/01 P-1
CAT28LV256
DATA Polling
Toggle Bit
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is
initiated, attempting to read the last byte written will
output the complement of that data on I/O7 (I/O0–I/O6
are indeterminate) until the programming cycle is com-
plete. Upon completion of the self-timed write cycle, all
I/O’s will output true data during a read cycle.
In addition to the DATA Polling feature, the device can
determine the completion of a write cycle, while a write
cycle is in progress, by reading data from the device.
ThisresultsinI/O6 togglingbetweenoneandzero.Once
the write is complete, however, I/O6 stops toggling and
valid data can be read from the device.
Figure 7. DATA Polling
ADDRESS
CE
WE
t
OEH
t
OES
t
OE
OE
t
WC
I/O
D
= X
D
= X
D
= X
OUT
7
IN
OUT
28LV256 F10
Figure 8. Toggle Bit
WE
CE
OE
t
OEH
t
OES
t
OE
(1)
(1)
I/O
6
t
WC
28LV256 F11
Note:
(1) Beginning and ending state of I/O is indeterminate.
6
Doc. No. 25040-00 4/01 P-1
8
CAT28LV256
HARDWARE DATA PROTECTION
The following hardware data protection features are
incorporated into the CAT28LV256.
(4) Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
(1) VCC sense provides write protection when VCC falls
below 2.0V min.
SOFTWARE DATA PROTECTION
The CAT28LV256 features a software controlled data
protectionschemewhich, onceenabled, requiresadata
algorithmtobeissuedtothedevicebeforeawritecanbe
performed. The device is shipped from Catalyst with the
software protection NOT ENABLED (the CAT28LV256
is in the standard operating mode).
(2) A power on delay mechanism, tINIT (see AC charac-
teristics), provides a 5 to 10 ms delay before a write
sequence, after VCC has reached 2.4V min.
(3) Write inhibit is activated by holding any one of OE
low, CE high, or WE high.
Figure 9. Write Sequence for Activating Software
Data Protection
Figure 10. Write Sequence for Deactivating
Software Data Protection
WRITE DATA:
ADDRESS:
AA
WRITE DATA:
ADDRESS:
AA
5555
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
ADDRESS:
55
2AAA
2AAA
WRITE DATA:
ADDRESS:
80
WRITE DATA:
ADDRESS:
A0
5555
5555
WRITE DATA:
ADDRESS:
AA
SOFTWARE DATA
PROTECTION ACTIVATED
(1)
5555
WRITE DATA:
ADDRESS:
55
WRITE DATA:
XX
2AAA
TO ANY ADDRESS
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
ADDRESS:
20
5555
28LV256 F12
28LV256 F13
Note:
(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within t
Max., after SDP activation.
BLC
Doc. No. 25040-00 4/01 P-1
9
CAT28LV256
Toactivatethesoftwaredataprotection,thedevicemust
besentthreewritecommandstospecificaddresseswith
specific data (Figure 9). This sequence of commands
(along with subsequent writes) must adhere to the page
writetimingspecifications(Figure11).Oncethisisdone,
all subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued, regardless of power on/off transi-
tions. This gives the user added inadvertent write pro-
tection on power-up in addition to the hardware protec-
tion provided.
To allow the user the ability to program the device with
an E2PROM programmer (or for testing purposes) there
is a software command sequence for deactivating the
data protection. The six step algorithm (Figure 10) will
reset the internal protection circuitry, and the device will
return to standard operating mode (Figure 12 provides
reset timing). After the sixth byte of this reset sequence
has been issued, standard byte or page writing can
commence.
Figure 11. Software Data Protection Timing
t
WC
DATA
ADDRESS
AA
5555
55
2AAA
A0
5555
BYTE OR
PAGE
CE
WRITES
ENABLED
t
t
BLC
WP
WE
28LV256 F14
Figure 12. Resetting Software Data Protection Timing
t
DATA
ADDRESS
AA
5555
55
2AAA
80
5555
AA
5555
55
2AAA
20
5555
WC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
28LV256 F15
ORDERING INFORMATION
Prefix
Device #
Suffix
T
CAT
28LV256
N
I
-25
Optional
Company
ID
Temperature Range
Tape & Reel
T: 500/Reel
Blank = Commercial (0˚C to +70˚C)
I = Industrial (-40˚C to +85˚C)
A = Automotive (-40˚ to +105˚C)*
Package
P: PDIP
N: PLCC
Speed
Product
Number
20: 200ns
25: 250ns
30: 300ns
28LV256 F16
T13: TSOP (8mmx13.4mm)
* -40˚C to +125˚C is available upon request
Notes:
(1) The device used in the above example is a CAT28LV256NI-25T (100,000 Cycle Endurance, PLCC, Industrial temperature, 250 ns
Access Time, Tape & Reel).
Doc. No. 25040-00 4/01 P-1
10
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