CAT5111P-10TSSOP [CATALYST]

100-Tap Digitally Programmable Potentiometer (DPP) with Buffered Wiper; 100抽头数字可编程电位计（ DPP）与缓冲刷


型号：	CAT5111P-10TSSOP
厂家：	CATALYST SEMICONDUCTOR
描述：	100-Tap Digitally Programmable Potentiometer (DPP) with Buffered Wiper 100抽头数字可编程电位计（ DPP）与缓冲刷
文件：	总7页 (文件大小：70K)
中文：	中文翻译
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CAT5111

100-Tap Digitally Programmable Potentiometer (DPP™)

with Buffered Wiper

FEATURES

APPLICATIONS

■ 100-position linear taper potentiometer

■ Automated product calibration

■ Remote control adjustments

■ Offset, gain and zero control

■ Tamper-proof calibrations

■ Non-volatile NVRAM wiper storage;

buffered wiper

■ Low power CMOS technology

■ Single supply operation: 2.5V-6.0V

■ Increment up/down serial interface

■ Resistance values: 10kΩ, 50kΩ and 100kΩ

■ Available in PDIP, SOIC, TSSOP and MSOP packages

■ Contrast, brightness and volume controls

■ Motor controls and feedback systems

■ Programmable analog functions

DESCRIPTION

system values without effecting the stored

setting. Wiper-control of the CAT5111 is

accomplished with three input control pins, CS, U/D,

and INC. The INC input increments the wiper in the

direction which is determined by the logic state of

the U/D input. The CS input is used to select the

device and also store the wiper position prior to

power down.

The CAT5111 is a single digitally programmable

potentiometer (DPP™) designed as a electronic

replacement for mechanical potentiometers and trim

pots. Ideal for automated adjustments on high volume

production lines, they are also well suited for

applications where equipment requiring periodic

adjustment is either difficult to access or located in a

hazardous or remote environment.

The digitally programmable potentiometer can be

used as a buffered voltage divider. For applications

wherethepotentiometerisusedasa2-terminalvariable

resistor, please refer to the CAT5113. The buffered

wiper of the CAT5111 is not compatible with that

application. DPPs bring variability and programmability

to a broad range of applications and are used primarily

tocontrol,regulateoradjustacharacteristicorparameter

of an analog circuit.

The CAT5111 contains a 100-tap series resistor array

connected between two terminals R_Hand R_L. An up/

down counter and decoder that are controlled by three

input pins, determines which tap is connected to the

wiper, R_WB. The CAT5111 wiper is buffered by an op

amp that operates rail to rail. The wiper setting, stored in

non-volatileNVRAMmemory,isnotlostwhenthedevice

is powered down and is automatically recalled when

powerisreturned. Thewipercanbeadjustedtotestnew

FUNCTIONAL DIAGRAM

U/D

–

Control

and

Memory

INC

Power On Recall

Electronic Potentiometer

Implementation

GND

Characteristics subject to change without notice

Doc. No. 2008, Rev. O

CAT5111

PIN CONFIGURATION

PDIP Package (P, L)

PIN FUNCTIONS

TSSOP Package (U, Y)

Pin Name

Function

INC

Increment Control

Up/Down Control

Potentiometer High Terminal

Ground

INC

U/D

GND

INC

GND

U/D

GND

SOIC Package (S, V)

MSOP Package (R, Z)

Buffered Wiper Terminal

Potentiometer Low Terminal

Chip Select

INC

V_CC

U/D

GND

V_CC

Supply Voltage

PIN DESCRIPTIONS

INC: Increment Control Input

of the CAT5111 and is active low. When in a high

state, activity on the INC and U/D inputs will not

affect or change the position of the wiper.

TheINCinput(onthefallingedge)movesthewiperinthe

up or down direction determined by the condition of the

U/D input.

DEVICE OPERATION

U/D: Up/Down Control Input

The CAT5111 operates like a digitally controlled

potentiometer with R_Hand R_Lequivalent to the high

andlowterminalsandR_WBequivalentto themechanical

potentiometer's wiper. There are 100 available tap

positions including the resistor end points, R_Hand R_L.

There are 99 resistor elements connected in series

between the R_Hand R_Lterminals. The wiper terminal is

connectedtooneofthe100 tapsandcontrolledbythree

inputs, INC, U/D and CS. These inputs control a seven-

bit up/down counter whose output is decoded to select

the wiper position. The selected wiper position can be

stored in nonvolatile memory using the INC and

CS inputs.

The U/D input controls the direction of the wiper

movement. When in a high state and CS is low, any high-

to-low transition on INC will cause the wiper to move one

increment toward the R_Hterminal. When in a low state

and CS is low, any high-to-low transition on INC will

cause the wiper to move one increment towards the

R_Lterminal.

R_H:High End Potentiometer Terminal

R_His the high end terminal of the potentiometer. It is not

required that this terminal be connected to a potential

greater than the R_Lterminal. Voltage applied to the R_H

terminal cannot exceed the supply voltage, V_CCor go

below ground, GND.

With CS set LOW the CAT5111 is selected and will

respond to the U/D and INC inputs. HIGH to LOW

transitions on INC wil increment or decrement the

wiper (depending on the state of the U/D input and

seven-bit counter). The wiper, when at either fixed

terminal, acts like its mechanical equivalent and does

not move beyond the last position. The value of the

counter is stored in nonvolatile memory whenever CS

transitionsHIGHwhiletheINCinputisalsoHIGH. When

the CAT5111 is powered-down, the last stored wiper

counterpositionismaintainedinthenonvolatilememory.

When power is restored, the contents of the memory are

recalled and the counter is set to the value stored.

R_WB: Wiper Potentiometer Terminal (Buffered)

R_WBis the buffered wiper terminal of the potentiometer. Its

position on the resistor array is controlled by the control

inputs, INC, U/D and CS.

R_L: Low End Potentiometer Terminal

R_Lis the low end terminal of the potentiometer. It is not

required that this terminal be connected to a potential

less than the R_Hterminal. Voltage applied to the R_L

terminal cannot exceed the supply voltage, V_CCor go

below ground, GND. R_Land R_Hare electrically

interchangeable.

With INC set low, the CAT5111 may be de-selected

and powered down without storing the current wiper

position in nonvolatile memory. This allows the

system to always power up to a preset value stored

in nonvolatile memory.

CS: Chip Select

The chip select input is used to activate the control input

Doc. No. 2008, Rev. O

CAT5111

OPERATING MODES

R_H

INCC

High to Low

High

CSC

U/DC

High

Operation

C_H

R_wi

Low

Wiper toward R

R_WB

C_W

Low

Low to High

High

Store Wiper Position

No Store, Return to Standby

Standby

Low

C_L

Potentiometer

Equivalent Circuit

R_L

Operating Ambient Temperature

ABSOLUTE MAXIMUM RATINGS

Commercial (‘C’ or Blank suffix)

Industrial (‘I’ suffix)

Junction Temperature

Storage Temperature

Lead Soldering (10 sec max)

0°C to +70°C

– 40°C to +85°C

+150°C

–65°C to +150°C

+300°C

Supply Voltage

V_CCto GND

Inputs

–0.5V to +7V

CS to GND

INC to GND

U/D to GND

R_Hto GND

R_Lto GND

R_WBto GND

–0.5V to V_CC+0.5V

* Stresses above those listed under Absolute Maximum Ratings may

cause permanent damage to the device. Absolute Maximum Ratings

are limited values applied individually while other parameters are

within specified operating conditions, and functional operation at any

of these conditions is NOT implied. Device performance and reliability

maybeimpairedbyexposuretoabsoluteratingconditionsforextended

periods of time.

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Test

MethodMin

Typ

Max

Units

(1)

V_ZAP

ESD Susceptibility

Latch-Up

MIL-STD-883, Test Method 3015

JEDEC Standard 17

2000

100

Volts

(1)(2)

I_LTH

T_DR

Data Retention

Endurance

MIL-STD-883, Test Method 1008

100

Years

Stores

N_END

MIL-STD-883, Test Method 1003 1,000,000

DC Electrical Characteristics: V_CC= +2.5V to +6.0V unless otherwise specified

Power Supply

Symbol Parameter

Conditions

Min

2.5

Typ

—

Max

6.0

Units

V_CC

I_CC1

Operating Voltage Range

Supply Current (Increment)

V_CC= 6V, f = 1MHz, I_W=0

V_CC= 6V, f = 250kHz, I_W=0

—

200

100

µA

I_CC2

Supply Current (Write)

Programming, V_CC= 6V

V_CC= 3V

—

500

µA

(2)

ISB₁

Supply Current (Standby)

CS=V_CC-0.3V

—

150

µA

U/D, INC=V_CC-0.3V or GND

Logic Inputs

Symbol Parameter

Conditions

Min

Typ

Max

Units

I_IH

Input Leakage Current

V_IN= V_CC

—

–10

µA

I_IL

Input Leakage Current

V_IN= 0V

—

V_IH1

V_IL1

V_IH2

V_IL2

TTL High Level Input Voltage

TTL Low Level Input Voltage

CMOS High Level Input Voltage

CMOS Low Level Input Voltage

4.5V ≤ V_CC≤ 5.5V

V_CC

0.8

2.5V ≤ V_CC≤ 6V

V_CCx 0.7

-0.3

V_CC+ 0.3

V_CCx 0.2

NOTES: (1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V_CC+ 1V

(3) I_W=source or sink

(4) These parameters are periodically sampled and are not 100% tested.

Doc. No. 2008, Rev. O

CAT5111

Potentiometer Parameters

Symbol

Parameter

Conditions

Min

Typ

Max Units

R_POT

Potentiometer Resistance

-10 Device

-50 Device

-00 Device

kΩ

100

Pot Resistance Tolerance

Voltage on R_Hpin

±20

V_CC

V_RH

V_RL

Voltage on R_Lpin

Resolution

INL

DNL

Integral Linearity Error

Differential Linearity Error

Buffer Output Resistance

Buffer Output Current

TC of Pot Resistance

Ratiometric TC

_W≤ 2µA

0.5

0.25

0.5

LSB

Ω

R_OUT

I_OUT

.05V_CC≤ V_WB≤ .95V_CC, V_CC=5V

ppm/^oC

Ω

TC_RPOT

TC_RATIO

R_ISO

300

TBD

8/8/25

1.7

Isolation Resistance

C_RH/C_RL/C_RWPotentiometer Capacitances

fc Frequency Response

Passive Attenuator, 10kΩ

MHz

V_WB(SWING)Output Voltage Range

_OUT≤100µA, V_CC=5V

0.01V_CC

.99V_CC

Doc. No. 2008, Rev. O

CAT5111

AC CONDITIONS OF TEST

Range

2.5V ≤ V

≤ 6V

Input Pulse Levels

0.2V to 0.7V

CC CC

Input Rise and Fall Times

Input Reference Levels

10ns

0.5V

AC OPERATING CHARACTERISTICS:

V_CC= +2.5V to +6.0V, V_H= V_CC, V_L= 0V, unless otherwise specified

Symbol Parameter

Min

Typ⁽¹⁾

Max

Units

t_CI

CS to INC Setup

100

250

—

t_DI

U/D to INC Setup

t_ID

U/D to INC Hold

t_IL

INC LOW Period

t_IH

INC HIGH Period

t_IC

INC Inactive to CS Inactive

CS Deselect Time (NO STORE)

CS Deselect Time (STORE)

INC to V_OUTChange

INC Cycle Time

µs

t_CPH

t_IW

t_CYC

100

—

µs

—

500

µs

(2)

t_{R, F}

INC Input Rise and Fall Time

Power-up to Wiper Stable

Store Cycle

—

µs

(2)

t_PU

—

msec

t_WR

—

A. C. TIMING

(store)

t_CYC

t_IC

t_CPH

t_CI

t_IL

t_IH

90%

INC

10%

tID

tDI

t_R

t_F

U/D

(3)

t_IW

(1) Typical values are for T =25˚C and nominal supply voltage.

(2) This parameter is periodically sampled and not 100% tested.

(3) MI in the A.C. Timing diagram refers to the minimum incremental change in the W output due to a change in the wiper position.

Doc. No. 2008, Rev. O

CAT5111

ORDERING INFORMATION

Prefix

Device #

5111

Suffix

-10

CAT

TE13

Product Number

5111: Buffered

5113: Unbuffered

Resistance

Optional

Company ID

Tape & Reel

-10: 10kohms

SOIC: 2000/Reel

-50: 50kohms

-00: 100kohms

TSSOP: 2000/Reel

MSOP: 2500/Reel

Package

P: PDIP

S: SOIC

U: TSSOP

R: MSOP

L: PDIP (Lead free, Halogen free)

V: SOIC (Lead free, Halogen free)

Y: TSSOP (Lead free, Halogen free)

Z: MSOP (Lead free, Halogen free)

Notes:

(1) The device used in the above example is a CAT5111 SI-10TE13 (SOIC, 10K Ohms, Industrial Temperature, Tape & Reel)

Doc. No. 2008, Rev. O

CAT5111

REVISION HISTORY

Date

Rev.

Reason

3/10/2004

3/29/2004

4/12/2004

Updated Potentiometer Parameters

Changed Green Package marking for SOIC from W to V

Updated Reel Ordering Information

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™

AE ™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Phone: 408.542.1000

Publication #: 2002

Fax: 408.542.1200

Revison:

www.catalyst-semiconductor.com

Issue date:

4/12/04

Doc. No. 2008, Rev. O

CAT5111P-10TSSOP [CATALYST]

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