CAT512JTE13_技术文档

Advanced Information

CAT512

8-Bit Dual Digital POT with Independent Reference Inputs

FEATURES

APPLICATIONS

■ Output settings retained without power

■ Independent Reference Inputs

■ Automated product calibration.

■ Remote control adjustment of equipment

■ Output range includes both supply rails

■ Programming voltage generated on-chip

■ 2 independently addressable outputs

■ Serial µP interface

■ Offset, gain and zero adjustments in Self-

Calibrating and Adaptive Control systems.

■ Tamper-proof calibrations.

■ Single supply operation: 2.7V-5.5V

DESCRIPTION

Control of the CAT512 is accomplished with a simple 3

wire serial interface. A Chip Select pin allows several

CAT512's to share a common serial interface and com-

munications back to the host controller is via a single

serial data line thanks to the CAT512’s Tri-Stated Data

Output pin. A RDY/BSYoutput working in concert with

aninternallowvoltagedetectorsignalsproperoperation

of EEPROM Erase/Write cycle.

TheCAT512isadual8-BitMemoryDACdesignedasan

electronic replacement for mechanical potentiometers

and trim pots. Intended for final calibration of products

such as camcorders, fax machines and cellular tele-

phones on automated high volume production lines and

systems capable of self calibration, it is also well suited

for applications were equipment requiring periodic ad-

justment is either difficult to access or located in a

hazardous environment.

The CAT512 operates from a single 3–5 volt power

supply. The high voltage required for EEPROM Erase/

Write operations is generated on-chip.

TheCAT512offers2independentlyprogrammableDACs

each having its own reference inputs and each capable

of rail to rail output swing. Output settings, stored non-

volatile EEPROM memory, are not lost when the device

is powered down and are automatically reinstated when

power is returned. Each output can be dithered to test

new output values without effecting the stored settings

and stored settings can be read back without disturbing

the DAC’s output.

The CAT512 is available in the 0°C to 70°C Commercial

and –40°C to +85°C Industrial operating temperature

ranges and offered in 14-pin plastic DIP and Surface

mount packages.

FUNCTIONAL DIAGRAM

PIN CONFIGURATION

V

DD

1

DIP Package (P)

SOIC Package (J)

6

3

7

RDY/BSY

SERIAL DATA OUTPUT

DO

PROGRAM

CONTROL

PROG

H1

H2

1

2

3

4

5

14

13

12

11

10

9

H1

H2

V

1

2

3

4

5

14

13

12

11

V

DD

REF

DD

REF

14

V

H1

1

REF

EEPROM

CLK

REF

12

9

V

LATCH

DAC 1

OUT

1

OUT

RDY/BSY

V

L1

REF

2

4

CLK

CS

DI

V

2

V

2

CS

DI

CS

DI

DATA

CONTROLLER

OUT

CAT512

L2

10

V

REF

13

11

10

REF

V

H2

2

REF

5

EEPROM

LATCH

L1

9

DO

6

7

DO

6

7

V

DAC 2

OUT

V

L2

8

GND

PROG

8

GND

REF

PROG

H.V.

CHARGE

PUMP

CAT512

8

GND

Characteristics subject to change without notice

1

CAT512

Advanced Information

ABSOLUTE MAXIMUM RATINGS

Operating Ambient Temperature

Supply Voltage*

Commercial (‘C’ suffix) .................... 0°C to +70°C

Industrial (‘I’ suffix)...................... – 40°C to +85°C

Junction Temperature ..................................... +150°C

Storage Temperature ....................... –65°C to +150°C

Lead Soldering (10 sec max) .......................... +300°C

V_DDto GND ......................................–0.5V to +7V

Inputs

CLK to GND............................–0.5V to V_DD+0.5V

CS to GND..............................–0.5V to V_DD+0.5V

DI to GND ...............................–0.5V to V_DD+0.5V

RDY/BSY to GND ...................–0.5V to V_DD+0.5V

PROG to GND ........................–0.5V to V_DD+0.5V

V_REFH to GND ........................–0.5V to V_DD+0.5V

V_REFL to GND .........................–0.5V to V_DD+0.5V

Outputs

*StressesabovethoselistedunderAbsoluteMaximumRatings

may cause permanent damage to the device. Absolute

Maximum Ratings are limited values applied individually while

other parameters are within specified operating conditions,

and functional operation at any of these conditions is NOT

implied.Deviceperformanceandreliabilitymaybeimpairedby

exposure to absolute rating conditions for extended periods of

time.

D₀to GND...............................–0.5V to V_DD+0.5V

V_OUT1– 2 to GND...................–0.5V to V_DD+0.5V

RELIABILITY CHARACTERISTICS

Symbol

Parameter

Min

Max

Units

Test Method

(1)

V_ZAP

ESD Susceptibility

Latch-Up

2000

100

Volts

mA

MIL-STD-883, Test Method 3015

JEDEC Standard 17

(1)(2)

I_LTH

Notes:

1. This parameter is tested initially and after a design or process change that affects the parameter.

2. Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to V + 1V.

CC

DC ELECTRICAL CHARACTERISTICS: V_DD= +2.7V to +5.5V, V_REFH = V_DD, V_REFL = 0V, unless otherwise specified

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Resolution

8

—

Bits

Accuracy

INL

Integral Linearity Error

I_LOAD= 250 nA, T_R= C

T_R= I

—

0.6

± 1

—

LSB

I_LOAD= 1 µA,

T_R= C

T_R= I

1.2

—

DNL

Differential Linearity Error

I_LOAD= 250 nA, T_R= C

T_R= I

0.25

0.5

± 0.5

—

I_LOAD= 1 µA,

T_R= C

T_R= I

0.5

—

Logic Inputs

I_IH

Input Leakage Current

High Level Input Voltage

Low Level Input Voltage

V_IN= V_DD

V_IN= 0V

—

2

—

10

–10

V_DD

0.8

µA

V

I_IL

V_IH

V_IL

0

V

References

V_RH

V_REFH Input Voltage Range

V_REFL Input Voltage Range

V_REFH–V_REFL Resistance

Input Resistance Match

2.7

GND

—

V_DD

V_DD-2.7

—

V

V_RL

V

Z_IN

28K

± 0.5

Ω

%

∆V_IN/ R_IN

—

± 1

Logic Outputs

V_OH

V_OL

High Level Output Voltage

Low Level Output Voltage

I_OH= – 40 µA

V_DD–0.3

—

V

I_OL= 1 mA, V_DD= +5V

I_OL= 0.4 mA, V_DD= +3V

—

0.4

8/00

2

CAT512

Units

Advanced Information

DC ELECTRICAL CHARACTERISTICS (Cont.):

V_DD= +2.7V to +5.5V, V_REFH = V_DD, V_REFL = 0V, unless otherwise specified

Symbol Parameter

Analog Output

Conditions

Min

Typ

Max

FSO

ZSO

I_L

Full-Scale Output Voltage

V_R= V_REFH – V_REF

L

0.99 V_R

—

0.995 V_R

—

V

Zero-Scale Output Voltage

DAC Output Load Current

DAC Output Impedance

V_R= V_REFH – V_REF

0.005 V_R0.01 V_R

V

µA

—

1

R_OUT

V_DD= V_REFH = +5V

V_DD= V_REFH = +3V

I_LOAD= 1 µA

—

100K

150K

1

Ω

—

Ω

PSSR

Power Supply Rejection

—

LSB / V

Temperature

TC_O

V_OUTTemperature Coefficient

V_DD= +5V, I_LOAD= 250nA

V_REFH= +5V, V_REFL = 0V

—

200

—

µV/ °C

TC_REF

Temperature Coefficient of

V_REFResistance

V_REFH to V_REF

L

700

ppm / °C

Power Supply

I_DD1

I_DD2

Supply Current (Read)

Normal Operating

V_DD= 5V

—

40

1.2

.6

50

2.0

1.2

5.5

µA

mA

V

Supply Current (Write)

V_DD= 3V

—

V_DD

Operating Voltage Range

2.7

—

AC ELECTRICAL CHARACTERISTICS:

V_DD= +2.7V to +5.5V, V_REFH = V_DD, V_REFL = 0V, unless otherwise specified

Symbol Parameter

Digital

Conditions

Min

Typ

Max

Units

t_CSMIN

t_CSS

t_CSH

t_DIS

Minimum CS Low Time

150

100

0

—

400

4

—

150

—

5

ns

CS Setup Time

CS Hold Time

ns

DI Setup Time

C_L= 100 pF,

50

ns

see note 1

t_DIH

DI Hold Time

50

ns

t_DO1

t_DO0

t_HZ

Output Delay to 1

Output Delay to 0

Output Delay to High-Z

Output Delay to Low-Z

Erase/Write Cycle Time

PROG Setup Time

Minimum Pulse Width

Minimum CLK High Time

Minimum CLK Low Time

Clock Frequency

—

ns

—

ns

—

ns

t_LZ

—

ns

t_BUSY

t_PS

—

ms

ns

150

700

500

300

DC

—

1

t_PROG

ns

t_CLK

f_C

H

ns

L

ns

MHz

Analog

t_DS

DAC Settling Time to 1 LSB

C_LOAD= 10 pF, V_DD= +5V

C_LOAD= 10 pF, V_DD= +3V

—

3

6

10

µs

Pin Capacitance

C_IN

Input Capacitance

Output Capacitance

V_IN= 0V, f = 1 MHz⁽²⁾

V_OUT= 0V, f = 1 MHz²⁾

—

8

6

—

pF

C_OUT

Notes: 1. All timing measurements are defined at the point of signal crossing V / 2.

DD

2. These parameters are periodically sampled and are not 100% tested.

8/00

3

CAT512

Advanced Information

A. C. TIMING DIAGRAM

t

1

2

3

4

5

o

t

H

CLK

t

L

t

CSH

CSS

CLK

CS

t

CSMIN

t

DIS

DI

t

DIH

t

DO0

t

LZ

DO

t

HZ

t

DO1

PROG

t

PS

t

PROG

RDY/BSY

t

BUSY

t

1

2

3

4

5

o

8/00

4

CAT512

Advanced Information

PIN DESCRIPTION

DAC addressing is as follows:

Name

Function

DAC OUTPUT

A0

0

A1

1

2

3

4

5

6

7

V_DD

Power supply positive

Clock input pin

V

1

2

OUT

CLK

RDY/BSY

CS

V

1

Ready/Busy output

Chip select

DI

Serial data input pin

Serial data output pin

DO

PROG

EEPROM Programming Enable

Input

8

GND

Power supply ground

9

V_REFL1

V_REFL2

Minimum DAC 1 output voltage

Minimum DAC 2 output voltage

DAC 2 output

10

11

12

13

14

V_OUT

2

1

DAC 1 output

V_REFH2

V_REFH1

Maximum DAC 2 output voltage

Maximum DAC 1 output voltage

DEVICE OPERATION

CHIP SELECT

The CAT512 is a dual 8-bit Digital to Analog Converter

(DAC) whose outputs can be programmed to any one of

256 individual voltage steps. Once programmed, these

output settings are retained in non-volatile EEPROM

memoryandwillnotbelostwhenpowerisremovedfrom

the chip. Upon power up the DACs return to the settings

stored in EEPROM memory. Each DAC can be written

to and read from independently without effecting the

output voltage during the read or write cycle. Each

output can also be adjusted without altering the stored

output setting, which is useful for testing new output

settings before storing them in memory.

Chip Select (CS) enables and disables the CAT512’s

readandwriteoperations. WhenCSishighdatamaybe

read to or from the chip, and the Data Output (DO) pin is

active. Data loaded into the DAC control registers will

remain in effect until CS goes low. Bringing CS to a logic

low returns all DAC outputs to the settings stored in

EEPROM memory and switches DO to its high imped-

ance Tri-State mode.

Because CS functions like a reset the CS pin has been

desensitized with a 30 ns to 90 ns filter circuit to prevent

noise spikes from causing unwanted resets and the loss

of volatile data.

DIGITAL INTERFACE

CLOCK

The CAT512 employs a standard 3 wire serial control

interface consisting of Clock (CLK), Chip Select (CS)

and Data In (DI) inputs. For all operations, address and

data are shifted in LSB first. In addition, all digital data

must be preceded by a logic “1” as a start bit. The DAC

address and data are clocked into the DI pin on the

clock’s rising edge. When sending multiple blocks of

information a minimum of two clock cycles is required

between the last block sent and the next start bit.

The CAT512’s clock controls both data flow in and out of

the IC and EEPROM memory cell programming. Serial

data is shifted into the DI pin and out of the DO pin on the

clock’srisingedge. Whileitisnotnecessaryfortheclock

to be running between data transfers, the clock must be

operating in order to write to EEPROM memory, even

though the data being saved may already be resident in

the DAC control register.

No clock is necessary upon system power-up. The

CAT512’s internal power-on reset circuitry loads data

from EEPROM to the DACs without using the external

clock.

Multiple devices may share a common input data line by

selectively activating the CS control of the desired IC.

Data Outputs (DO) can also share a common line

because the DO pin is Tri-Stated and returns to a high

impedance when not in use.

8/00

5

CAT512

Advanced Information

As data transfers are edge triggered clean clock transi-

tionsarenecessarytoavoidfalselyclockingdataintothe

control registers. Standard CMOS and TTL logic fami-

lies work well in this regard and it is recommended that

any mechanical switches used for breadboarding or

device evaluation purposes be debounced by a flip-flop

or other suitable debouncing circuit.

itshighimpedanceTri-StatemodewhenCSreturnslow.

Tri-Stating the DO pin allows several 512s to share a

single serial data line and simplifies interfacing multiple

512s to a microprocessor.

WRITING TO MEMORY

Programming the CAT512’s EEPROM memory is ac-

complished through the control signals: Chip Select

(CS) and Program (PROG). With CS high, a start bit

followedbyatwobitDACaddressandeightdatabitsare

clockedintotheDACcontrolregisterviatheDIpin. Data

enters on the clock’s rising edge. The DAC output

changes to its new setting on the clock cycle following

D7, the last data bit.

V

REF

V_REF, the voltage applied between pins V_REFH&V_REFL,

sets the DAC’s Zero to Full Scale output range where

V_REFL=ZeroandV_REFH=FullScale. V_REFcanspanthe

full power supply range or just a fraction of it. In typical

applications V_REFH &V_REFL are connected across the

power supply rails. When using less than the full supply

voltage be mindfull of the limits placed on V_REFH and

V_REFL as specified in the "References" section of DC

"Electrical Characteristics".

Programming is accomplished by bringing PROG high

sometimeafterthestartbitandatleast150nspriortothe

rising edge of the clock cycle immediately following the

D7 bit. Two clock cycles after the D7 bit the DAC control

register will be ready to receive the next set of address

and data bits. The clock must be kept running through-

out the programming cycle. Internal control circuitry

takes care of generating and ramping up the program-

mingvoltagefordatatransfertotheEEPROMcells. The

CAT512’s EEPROM memory cells will endure over

1,000,000writecyclesandwillretaindataforaminimum

of 100 years without being refreshed.

READY/BUSY

Whensavingdatatonon-volatileEEPROMmemory,the

Ready/Busy ouput (RDY/BSY) signals the start and

durationoftheEEPROMerase/writecycle.Uponreceiv-

ing a command to store data (PROG goes high) RDY/

BSY goes low and remains low until the programming

cycle is complete. During this time the CAT512 will

ignore any data appearing at DI and no data will be

output on DO.

READING DATA

RDY/BSY is internally ANDed with a low voltage detec-

tor circuit monitoring V_DD.If V_DDis below the minimum

value required for EEPROM programming, RDY/BSY

willremainhighfollowingtheprogramcommandindicat-

ing a failure to record the desired data in non-volatile

memory.

Each time data is transferred into a DAC control register

currently held data is shifted out via the D0 pin, thus in

every data transaction a read cycle occurs. Note,

however, that the reading process is destructive. Data

must be removed from the register in order to be read.

Figure 2 depicts a Read Only cycle in which no change

occurs in the DAC’s output. This feature allows µPs to

poll DACs for their current setting without disturbing the

output voltage but it assumes that the setting being read

isalsostoredinEEPROMsothatitcanberestoredatthe

end of the read cycle. In Figure 2 CS returns low before

the13^thclockcyclecompletes. IndoingsotheEEPROM’s

DATA OUTPUT

Data is output serially by the CAT512, LSB first, via the

Data Out (DO) pin following the reception of a start bit

and two address bits by the Data Input (DI). DO

becomes active whenever CS goes high and resumes

Figure 1. Writing to Memory

Figure 2. Reading from Memory

t

1

2

3

4

5

6

7

8

9

10 11 12

N

N+1 N+2

t

1

2

3

4

5

6

7

8

9

10 11 12

o

CS

DI

CS

DI

NEW DAC DATA

1

A0 A1 D0 D1 D2 D3 D4 D5 D6 D7

CURRENT DAC DATA

1

A0 A1

CURRENT DAC DATA

DO

PROG

D0 D1 D2 D3 D4 D5 D6 D7

PROG

RDY/BSY

CURRENT

DAC VALUE

DAC

OUTPUT

CURRENT

DAC VALUE

NEW

DAC VALUE

NEW

DAC VALUE

DAC

OUTPUT

NON-VOLATILE

VOLATILE

NON-VOLATILE

8/00

6

CAT512

Advanced Information

Figure 3. Temporary Change in Output

setting is reloaded into the DAC control register. Since

this value is the same as that which had been there

previously no change in the DAC’s output is noticed.

Had the value held in the control register been different

from that stored in EEPROM then a change would occur

at the read cycle’s conclusion.

t

1

2

3

4

5

6

7

8

9

10 11 12

N

N+1 N+2

o

CS

DI

NEW DAC DATA

1

A0 A1 D0 D1 D2 D3 D4 D5 D6 D7

TEMPORARILY CHANGE OUTPUT

CURRENT DAC DATA

TheCAT512allowstemporarychangesinDAC’soutput

to be made without disturbing the settings retained in

EEPROM memory. This feature is particularly useful

when testing for a new output setting and allows for user

adjustment of preset or default values without losing the

original factory settings.

D0 D1 D2 D3 D4 D5 D6 D7

DO

PROG

RDY/BSY

DAC

OUTPUT

CURRENT

DAC VALUE

NEW

DAC VALUE

CURRENT

DAC VALUE

Figure 3 shows the control and data signals needed to

effect a temporary output change. DAC settings may be

changed as many times as required and can be made to

any of the two DACs in any order or sequence. The

temporarysetting(s)remainineffectlongasCSremains

high. WhenCSreturnslowalltwoDACswillreturntothe

output values stored in EEPROM memory.

NON-VOLATILE

VOLATILE

NON-VOLATILE

When it is desired to save a new setting acquired using

this feature, the new value must be reloaded into the

DAC control register prior to programming. This is be-

cause the CAT512’s internal control circuitry discards

from the programming register the new data two clock

cycles after receiving it if no PROG signal is received.

APPLICATION CIRCUITS

+5V

R

I

R

F

+15V

V

H

V

H

L

DD

REF

DD

REF

–

V

–

OUT

CONTROL

& DATA

CONTROL

& DATA

+

OPT 505

CAT512

OP 07

+

OPT 505

CAT512

OP 07

DAC

-15V

GND

V

REF

L

GND

V

REF

R

F

V

= V

DAC

OUT

V

= (1 + –––) V

OUT

R

I

Buffered DAC Output

Amplified DAC Output

+5V

DAC INPUT

DAC OUTPUT

ANALOG

OUTPUT

V

R

F

i

I

CODE

V

= ——— (V - V

) + V

ZERO

DAC

FS

ZERO

255

+15V

V

= 0.99 V

V

= 5V

F

FS

REF

= 0.01 V

REF

R = R

V

H

L

DD

REF

V

–

OUT

MSB LSB

1111 1111

V

I

ZERO

REF

) + .01 V

CONTROL

& DATA

255

—— (.98 V

= .990 V

REF

V

= +4.90V

+

OPT 505

CAT512

REF

OUT

OP 07

255

-15V

128

GND

V

REF

1000 0000

0111 1111

0000 0001

—— (.98 V

) + .01 V

REF

= .502 V

REF

V

= +0.02V

= -0.02V

= -4.86V

REF

OUT

255

127

—— (.98 V

) + .01 V

REF

= .498 V

REF

V

R

V

=

(

R ) -V

F

R +

255

REF

OUT

DAC

F

I

F

I

1

R

—— (.98 V

) + .01 V

REF

= .014 V

REF

V

I

255

REF

OUT

For R =R

I

0

0000 0000 —— (.98 V

) + .01 V

REF

= .010 V

REF

V

= -4.90V

V

= 2V -V

REF

OUT

DAC I

255

Bipolar DAC Output

8/00

7

CAT512

Advanced Information

APPLICATION CIRCUITS (Cont.)

+5V

V

+V

REF

V

REF

R

= —————

C

256 1 µA

*

V

H

DD

REF

+5V

V

REF

Fine adjust gives ± 1 LSB change in V

OFFSET

V

REF

2

127R

V

H

V

C

when V =

OFFSET

———

DD

REF

FINE ADJUST

DAC

+

(+V

) - (V

)

REF

OFFSET

127R

C

R

= ———————————

C

FINE ADJUST

DAC

1 µA

+

(-V

) + (V

)

REF

OFFSET

R

= ———————————

o

1 µA

R

C

COARSE ADJUST

DAC

+V

R

C

V

OFFSET

COARSE ADJUST

DAC

+

GND

V

L

REF

+V

-V

R

o

V

OFFSET

–

+

-V

REF

GND

V

L

REF

–

Coarse-Fine Offset Control by Averaging DAC Outputs

for Single Power Supply Systems

Coarse-Fine Offset Control by Averaging DAC Outputs

for Dual Power Supply Systems

28 - 32V

V+

I > 2 mA

15K

10 µF

1N5231B

5.1V

V

= 5.000V

REF

V

H

L

DD

REF

V

H

DD

REF

10K

CONTROL

& DATA

LT 1029

O

CA

P

T

5

1

0

2

5

CONTROL

& DATA

+

MPT3055EL

OPT 505

CAT512

–

LM 324

4.02 K

GND

V

REF

L

GND

V

REF

OUTPUT

10 µF

35V

0 - 25V

@ 1A

1.00K

Digitally Trimmed Voltage Reference

Digitally Controlled Voltage Reference

8/00

8

CAT512

Advanced Information

APPLICATION CIRCUITS (Cont.)

+5V

2.2K

V

REF

4.7 µA

DD

LM385-2.5

+15V

I

= 2 - 255 mA

1 mA steps

SINK

DAC

+

2N7000

+5V

–

10K

39Ω1W

39Ω 1W

CONTROL

& DATA

CAT512

OPT 505

DAC

+

5 µA steps

2N7000

3.9K

–

GND

V

L

5 meg

10K

5 meg

REF

10K

–

TIP 30

+

-15V

Current Sink with 4 Decades of Resolution

+15V

51K

+

TIP 29

–

10K

+5V

V

H

DD

REF

5 meg

39Ω 1W

DAC

–

CONTROL

& DATA

C

O

A

PTT5

5

1

0

2

5

BS170P

3.9K

1 mA steps

+

5 meg

DAC

–

GND

V

L

REF

BS170P

5 µA steps

+

LM385-2.5

-15V

I

= 2 - 255 mA

SOURCE

Current Source with 4 Decades of Resolution

8/00

9

CAT512

Advanced Information

ORDERING INFORMATION

Prefix

Device #

Suffix

-TE13

CAT

512

J

I

Optional

Company ID

Product

Number

Package

P: PDIP

J: SOIC

Tape & Reel

TE13:

2000/Reel

Temperature Range

Blank = Commercial (0˚C to +70˚C)

I = Industrial (-40˚C to +85˚C)

Notes:

(1) The device used in the above example is a CAT512JI-TE13 (SOIC, Industrial Temperature, Tape & Reel)

8/00

10


型号：	CAT512JTE13
厂家：	CATALYST SEMICONDUCTOR
描述：	8-Bit Dual Digital POT with Independent Reference Inputs 8位双通道数字电位器具有独立的基准输入电位器
文件：	总10页 (文件大小：74K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

CAT512JTE13 [CATALYST]

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CAT5132R-100TE13

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CAT5132RI-10