CAT521WI [CATALYST]
Configured Digitally Programmable Potentiometer (DPP⑩): Programmable Voltage Applications; 配置数字可编程电位计( DPP ™ ) :可编程电压应用型号: | CAT521WI |
厂家: | CATALYST SEMICONDUCTOR |
描述: | Configured Digitally Programmable Potentiometer (DPP⑩): Programmable Voltage Applications |
文件: | 总13页 (文件大小:208K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
CAT521
Configured Digitally Programmable Potentiometer (DPP™):
Programmable Voltage Applications
FEATURES
DESCRIPTION
8-bit DPP configured as a programmable
The CAT521 is a 8-bit digitally-programmable poten-
tiometer (DPP™) configured for programmable voltage
and DAC-like applications. Intended for final calibration
of products such as camcorders, fax machines and
cellular telephones on automated high volume
production lines, it is also well suited for self-calibrating
systems and for applications where equipment which
requires periodic adjustment is either difficult to access
or in a hazardous environment.
voltage source in DAC-like applications
Buffered wiper output
Non-volatile NVRAM memory wiper storage
Output voltage range includes both supply rails
1 LSB accuracy, high resolution
Serial Microwire-like interface
Single supply operation: 2.7V – 5.5V
Setting read-back without effecting outputs
The programmable DPP has an output voltage range
which includes both supply rails. The wiper is buffered
by a rail to rail op amp. The wiper setting, stored in
non-volatile NVRAM memory, is not lost when the
device is powered down and is automatically
reinstated when power is returned. The wiper can be
dithered to test new output values without effecting
the stored settings and stored settings can be read
back without disturbing the DPP’s output.
For Ordering Information details, see page 12.
APPLICATIONS
Automated product calibration
The CAT521 is controlled with a simple 3-wire,
Microwire like serial interface. A Chip Select pin
allows several devices to share a common serial
interface. Communication back to the host controller is
via a single serial data line thanks to the CAT521 Tri-
Remote control adjustment of equipment
Offset, gain and zero adjustments in self-
calibrating and adaptive control systems
Tamper-proof calibrations
¯¯¯¯
Stated Data Output pin. A RDY/BSY output working in
DAC (with memory) substitute
concert with an internal low voltage detector signals
proper operation of the non-volatile NVRAM memory
Erase/Write cycle.
PIN CONFIGURATION
PDIP 14-Lead (L)
SOIC 14-Lead (W)
The CAT521 is available in 0°C to 70°C commercial
and -40°C to 85°C industrial operating temperature
ranges. Both 14-pin plastic DIP and surface mount
packages are available.
VDD
1
2
3
4
5
6
7
14 VREFH
13 NC
12 VOUT
11 NC
10 NC
CLK
¯¯¯¯
RDY/BSY
CAT521
CS
DI
DO
8
8
VREFL
GND
PROG
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. MD-2003 Rev. G
CAT521
FUNCTIONAL DIAGRAM
V
V
DD
REFH
14
1
3
RDY/BSY
PROGRAM
CONTROL
7
PROG
24kΩ
24kΩ
5
2
4
DI
24kΩ
24kΩ
+
–
SERIAL
CONTROL
12
CLK
V
OUT
CS
SERIAL
DATA
OUTPUT
REGISTER
6
DO
CAT521
8
9
GND
V
REFL
Doc. No. MD-2003 Rev. G
2
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT521
ABSOLUTE MAXIMUM RATINGS
Parameters
Supply Voltage*
VDD to GND
Inputs
Ratings
Parameters
Outputs
Ratings
Units
Units
V
-0.5 to VDD +0.5
-0.5 to VDD +0.5
V
V
-0.5 to +7
D0 to GND
VOUT 1– 4 to GND
CLK to GND
CS to GND
DI to GND
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
-0.5 to VDD +0.5
V
V
V
V
V
V
V
Operating Ambient Temperature
Commercial
0 to +70
°C
(‘C’ or Blank suffix)
Industrial (‘I’ suffix)
Junction Temperature
Storage Temperature
Lead Soldering (10 sec max)
-40 to +85
+150
°C
°C
°C
°C
¯¯¯¯
RDY/BSY to GND
PROG to GND
VREFH to GND
VREFL to GND
-65 to +150
+300
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Test Method
Min Max Units
(2)
VZAP
ESD Susceptibility
Latch-Up
MIL-STD-883, Test Method 3015
JEDEC Standard 17
2000
100
V
(2)(3)
ILTH
mA
POWER SUPPLY
Symbol
IDD1
Parameter
Conditions
Min
—
Typ
Max Units
Supply Current (Read)
Supply Current (Write)
Normal Operating
Programming, VDD = 5V
VDD = 3V
400
600
µA
µA
µA
V
IDD2
—
1600 2500
1000 1600
—
VDD
Operating Voltage Range
2.7
—
5.5
LOGIC INPUTS
Symbol
Parameter
Conditions
VIN = VDD
VIN = 0V
Min
—
—
2
Typ
—
Max Units
IIH
IIL
Input Leakage Current
Input Leakage Current
High Level Input Voltage
Low Level Input Voltage
10
-10
VDD
0.8
µA
µA
V
—
VIH
VIL
—
0
—
V
LOGIC OUTPUTS
Symbol
VOH
Parameter
High Level Output Voltage
Low Level Output Voltage
Conditions
Min
Typ
—
Max Units
IOH = -40µA
VDD -0.3
—
V
V
V
VIL
IOL = 1 mA, VDD = +5V
IOL = 0.4 mA, VDD = +3V
—
—
—
0.4
0.4
—
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) This parameter is tested initially and after a design or process change that affects the parameter.
(3) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC + 1V.
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
3
Doc. No. MD-2003 Rev. G
CAT521
POTENTIOMETER CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Conditions
Min
Typ
24
Max
Units
kΩ
Potentiometer Resistance
See note 3
RPOT
RPOT to RPOT Match
Pot Resistance Tolerance
Voltage on VREFH pin
Voltage on VREFL pin
Resolution
—
±0.5
±1
±20
%
%
2.7
0
VDD
V
VDD - 2.7
V
0.4
0.5
%
INL
DNL
Integral Linearity Error
Differential Linearity Error
Buffer Output Resistance
Buffer Output Current
TC of Pot Resistance
Potentiometer Capacitances
1
0.5
10
3
LSB
LSB
Ω
0.25
ROUT
IOUT
mA
ppm/ºC
pF
TCRPOT
CH/CL
300
8/8
AC ELECTRICAL CHARACTERISTICS
VDD = +2.7V to +5.5V, VREFH = VDD, VREFL = 0V, unless otherwise specified
Symbol Parameter
Digital
Conditions
Min
Typ
Max
Units
tCSMIN
tCSS
tCSH
tDIS
Minimum CS Low Time
150
100
0
—
—
—
—
—
—
—
400
400
4
—
—
—
—
—
150
150
—
—
5
ns
ns
CS Setup Time
CS Hold Time
ns
DI Setup Time
50
ns
CL = 100pF (1)
tDIH
DI Hold Time
50
ns
tDO1
tDO0
tHZ
Output Delay to 1
Output Delay to 0
Output Delay to High-Z
Output Delay to Low-Z
Erase/Write Cycle Time
PROG Setup Time
Minimum Pulse Width
Minimum CLK High Time
Minimum CLK Low Time
Clock Frequency
—
ns
—
ns
—
ns
tLZ
—
ns
tBUSY
tPS
—
ms
ns
150
700
500
300
DC
—
—
—
—
—
—
—
—
—
1
tPROG
ns
tCLK
tCLK
fC
H
L
ns
ns
MHz
Analog
tDS
DPP Settling Time to 1 LSB
CLOAD = 10pF, VDD = +5V
CLOAD = 10pF, VDD = +3V
—
—
3
6
10
10
µs
µs
Notes:
(1) All timing measurements are defined at the point of signal crossing VDD / 2.
(2) These parameters are periodically sampled and are not 100% tested.
(3) The 24kΩ +20% resistors are configured as 4 resistors in parallel which would provide a measured value between VREFH and VREFL of 6kΩ
+20%. The individual 24kΩ resistors are not measurable but guaranteed by design and verification of the 6kΩ +20% value.
Doc. No. MD-2003 Rev. G
4
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT521
A.C. TIMING DIAGRAM
t
1
2
3
4
5
o
t
H
CLK
CLK
CS
DI
t
t
L
t
CSH
CSS
CLK
t
CSMIN
t
DIS
t
DIH
t
DO0
t
LZ
DO
t
HZ
t
DO1
PROG
t
PS
t
PROG
RDY/BSY
t
BUSY
4
t
1
2
3
5
o
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5
Doc. No. MD-2003 Rev. G
CAT521
PIN DESCRIPTION
Pin
1
Name
VDD
Function
DPP addressing is as follows:
Power supply positive
Clock input pin
DPP OUTPUT
A0 A1
2
CLK
VOUT
1
0
¯¯¯¯
RDY/BSY
3
Ready/Busy output
Chip select
4
CS
DI
5
Serial data input pin
Serial data output pin
6
DO
EEPROM Programming Enable
Input
7
PROG
8
GND
VREFL
NC
Power supply ground
Minimum DAC output voltage
No Connect
9
10
11
12
13
14
NC
No Connect
VOUT
NC
DPP output
No Connect
VREFH
Maximum DPP 1 output voltage
because the DO pin is Tri-Stated and returns to a high
impedance when not in use.
DEVICE OPERATION
The CAT521 is a single 8-bit configured digitally
programmable potentiometer (DPP™) whose output
can be programmed to any one of 256 individual
voltage steps. Once programmed, the output setting is
retained in non-volatile memory and will not be lost
when power is removed from the chip. Upon power up
the DPP returns to the setting stored in non-volatile
memory. The DPP can be written to and read from
without effecting the output voltage during the read or
write cycle. The output can also be adjusted without
altering the stored output setting, which is useful for
testing new output settings before storing them in
memory.
CHIP SELECT
Chip Select (CS) enables and disables the CAT521’s
read and write operations. When CS is high data may
be read to or from the chip, and the Data Output (DO)
pin is active. Data loaded into the DPP control register
will remain in effect until CS goes low. Bringing CS to
a logic low returns all DPP outputs to the settings
stored in nonvolatile memory and switches DO to its
high impedance Tri-State mode.
Because CS functions like a reset the CS pin has
been desensitized with a 30ns to 90ns filter circuit to
prevent noise spikes from causing unwanted resets
and the loss of volatile data.
DIGITAL INTERFACE
The CAT521 employs a 3 wire, Microwire-like serial
control interface consisting of Clock (CLK), Chip
Select (CS) and Data In (DI) inputs. For all operations,
address and data are shifted in LSB first. In addition,
all digital data must be preceded by a logic “1” as a
start bit. The DPP address and data are clocked into
the DI pin on the clock’s rising edge. When sending
multiple blocks of information a minimum of two clock
cycles is required between the last block sent and the
next start bit.
CLOCK
The CAT521 clock controls both data flow in and out
of the device and non-volatile memory cell program-
ming. Serial data is shifted into the DI pin and out of
the DO pin on the clock’s rising edge. While it is not
necessary for the clock to be running between data
transfers, the clock must be operating in order to write
to non-volatile memory, even though the data being
saved may already be resident in the DPP wiper
control register.
Multiple devices may share a common input data line
by selectively activating the CS control of the desired
IC. Data Outputs (DO) can also share a common line
No clock is necessary upon system power-up. The
CAT521 internal power-on reset circuitry loads data
Doc. No. MD-2003 Rev. G
6
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT521
from non-volatile memory to the DPP without using
the external clock.
command indicating a failure to record the desired
data in non-volatile memory.
As data transfers are edge triggered clean clock
transitions are necessary to avoid falsely clocking
data into the control register. Standard CMOS and
TTL logic families work well in this regard and it is
recommended that any mechanical switches used for
breadboarding or device evaluation purposes be
debounced by a flip-flop or other suitable debouncing
circuit.
DATA OUTPUT
Data is output serially by the CAT521, LSB first, via
the Data Out (DO) pin following the reception of a
start bit and two address bits by the Data Input (DI).
DO becomes active whenever CS goes high and
resumes its high impedance Tri-State mode when CS
returns low. Tri-Stating the DO pin allows several
521s to share a single serial data line and simplifies
interfacing multiple 521s to a microprocessor.
VREF
VREF, the voltage applied between pins VREFH & VREFL,
WRITING TO MEMORY
sets the DPP’s Zero to Full Scale output range where
VREFL = Zero and VREFH = Full Scale. VREF can span
the full power supply range or just a fraction of it. In
typical applications VREFH & VREFL are connected
across the power supply rails. When using less than
the full supply voltage be mindfull of the limits placed
on VREFH and VREFL as specified in the References
section of DC Electrical Characteristics.
Programming the CAT521’s non-volatile memory is
accomplished through the control signals: Chip Select
(CS) and Program (PROG). With CS high, a start bit
followed by a two bit DPP address and eight data bits
are clocked into the DPP wiper control register via the
DI pin. Data enters on the clock’s rising edge. The
DPP output changes to its new setting on the clock
cycle following D7, the last data bit.
¯¯¯¯¯
READY/BUSY
Programming is accomplished by bringing PROG high
sometime after the start bit and at least 150ns prior to
the rising edge of the clock cycle immediately
following the D7 bit. Two clock cycles after the D7 bit
the DPP wiper control register will be ready to receive
the next set of address and data bits. The clock must
be kept running throughout the programming cycle.
Internal control circuitry takes care of generating and
ramping up the programming voltage for data transfer
to the non-volatile memory cells. The CAT521 non-
volatile memory cells will endure over 1,000,000 write
cycles and will retain data for a minimum of 100 years
without being refreshed.
When saving data to non-volatile memory, the
Ready/Busy ouput (RDY/BSY) signals the start and
duration of the erase/write cycle. Upon receiving a
command to store data (PROG goes high) RDY/BSY
goes low and remains low until the programming cycle is
complete. During this time the CAT521 will ignore any
data appearing at DI and no data will be output on DO.
¯¯¯¯
¯¯¯¯
¯¯¯¯
RDY/BSY is internally ANDed with a low voltage
detector circuit monitoring VDD. If VDD is below the
minimum value required for EEPROM programming,
¯¯¯¯
RDY/BSY will remain high following the program
Figure 1. Writing to Memory
t
1
2
3
4
5
6
7
8
9
10
11 12
N
N+1 N+2
o
CS
DI
NEW DPP DATA
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
CURRENT DPP DATA
DO
PROG
D0 D1 D2 D3 D4 D5 D6 D7
RDY/BSY
DPP
OUTPUT
CURRENT
DPP VALUE
NEW
DPP VALUE
NEW
DPP VALUE
NON-VOLATILE
VOLATILE
NON-VOLATILE
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
7
Doc. No. MD-2003 Rev. G
CAT521
READING DATA
TEMPORARILY CHANGE OUTPUT
Each time data is transferred into the DPP wiper
control register currently held data is shifted out via
the D0 pin, thus in every data transaction a read cycle
occurs. Note, however, that the reading process is
destructive. Data must be removed from the register
in order to be read. Figure 2 depicts a Read Only
cycle in which no change occurs in the DPP’s output.
This feature allows µPs to poll DPPs for their current
setting without disturbing the output voltage but it
assumes that the setting being read is also stored in
non-volatile memory so that it can be restored at the
end of the read cycle. In Figure 2 CS returns low
before the 13th clock cycle completes. In doing so the
non-volatile memory's setting is reloaded into the DPP
wiper control register. Since this value is the same as
that which had been there previously no change in the
DPP’s output is noticed. Had the value held in the
control register been different from that stored in non-
volatile memory then a change would occur at the
read cycle’s conclusion.
The CAT521 allows temporary changes in the DPP’s
output to be made without disturbing the settings
retained in non-volatile memory. This feature is
particularly useful when testing for a new output
setting and allows for user adjustment of preset or
default values without losing the original factory
settings.
Figure 3 shows the control and data signals needed to
effect a temporary output change. DPP settings may
be changed as many times as required. The
temporary setting remains in effect long as CS
remains high. When CS returns low the DPP will
return to the output value stored in non-volatile
memory.
When it is desired to save a new setting acquired
using this feature, the new value must be reloaded
into the DPP wiper control register prior to program-
ming. This is because the CAT521’s internal control
circuitry discards from the programming register the
new data two clock cycles after receiving it if no
PROG signal is received.
Figure 2. Reading from Memory
Figure 3. Temporary Change in Output
t
1
2
3
4
5
6
7
8
9
10
11 12
N
N+1 N+2
o
t
1
2
3
4
5
6
7
8
9
10
11 12
o
CS
DI
CS
DI
NEW DPP DATA
1
A0 A1 D0 D1 D2 D3 D4 D5 D6 D7
1
A0 A1
CURRENT DPP DATA
CURRENT DPP DATA
D0 D1 D2 D3 D4 D5 D6 D7
DO
PROG
DO
D0 D1 D2 D3 D4 D5 D6 D7
PROG
RDY/BSY
RDY/BSY
DPP
OUTPUT
CURRENT
NEW
CURRENT
CURRENT
DPP
OUTPUT
DPP VALUE
DPP VALUE
DPP VALUE
DPP VALUE
NON-VOLATILE
VOLATILE
NON-VOLATILE
NON-VOLATILE
Doc. No. MD-2003 Rev. G
8
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT521
APPLICATION CIRCUITS
+5V
DPP INPUT DPP OUTPUT
ANALOG OUTPUT
V
R
I
R
F
I
CODE
VDPP
=
VFS - VZERO +VZERO
255
VFS = 0.99VREF
=0.01V
+15V
VREF =5V
RI =RF
MSB LSB
–
V
V
DD
REFH
V
V
OUT
ZERO
REF
255
+
VOUT = +4.90V
VOUT =+0.02V
CONTROL
& DATA
×0.98V
REF
+0.01V
REF
=0.990V
REF
1111 1111
1000 0000
0111 1111
0000 0001
0000 0000
CAT521
255
128
OP 07
×0.98V
REF
+0.01V
REF
= 0.502V
REF
255
127
255
1
-15V
V
GND
REFL
×0.98V
REF
+0.01V
REF
= 0.498V
REF
VOUT = -0.02V
V
R
F
(
R ) - V
F I
R +
DPP
I
V
=
OUT
×0.98V
REF
+0.01V
REF
= 0.014V
REF
VOUT = -4.86V
VOUT = -4.90V
R
I
255
0
For R = R
I
F
×0.98V
REF
+0.01V
REF
= 0.010V
REF
255
V
= 2V - V
DPP I
OUT
Bipolar DPP Output
V+
+5V
V
I > 2mA
R
I
R
F
+15V
V
REF
= 5.00V
–
V
DD
REFH
V
OUT
V
V
REFH
DD
+
CONTROL
& DATA
CAT521
OP 07
CONTROL
& DATA
LT 1029
CAT521
-15V
V
GND
REFL
V
REFL
GND
R
F
R
I
V
OUT
= (1 +
) V
DPP
Amplified DPP Output
Digitally Trimmed Voltage Reference
28 - 32V
15kΩ
10µF
10kΩ
1N5231B
5.1V
V
DD
V
REFH
CONTROL
& DATA
CAT521
+
–
MPT3055EL
LM 324
V
GND
REFL
OUTPUT
4.02kΩ
0 - 25V
@ 1A
10µF
35V
1.00kΩ
Digitally Controlled Voltage Reference
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
9
Doc. No. MD-2003 Rev. G
CAT521
PACKAGE OUTLINE DRAWING
PDIP 14-Lead (L)(1)(2)
SYMBOL
MIN
3.56
0.38
2.92
0.36
1.15
0.21
18.67
7.62
6.10
NOM
MAX
A
A1
A2
b
5.33
3.30
0.45
4.95
0.55
1.77
0.35
19.68
8.25
7.11
E1
b1
c
1.52
0.26
D
19.05
7.87
E
E1
e
6.35
D
2.54 BSC
eB
L
7.88
2.99
10.92
3.81
TOP VIEW
3.30
E
A2
A1
A
L
c
e
b
b1
eB
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-001.
Doc. No. MD-2003 Rev. G
10
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
CAT521
SOIC 14-Lead (W)(1)(2)
SYMBOL
MIN
NOM
MAX
1.75
0.25
0.51
0.25
8.75
6.20
4.00
A
A1
b
1.35
0.10
0.33
0.19
8.55
5.80
3.80
c
D
E
E1
e
8.65
6.00
E1
E
3.90
1.27 BSC
h
0.25
0.40
0º
0.50
1.27
8º
L
θ
PIN#1 IDENTIFICATION
TOP VIEW
h
D
θ
A
c
e
b
L
A1
SIDE VIEW
END VIEW
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
© 2006 Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
11
Doc. No. MD-2003 Rev. G
CAT521
EXAMPLE OF ORDERING INFORMATION
Prefix
Device # Suffix
CAT
521
W
I
-
T2
Optional
Company ID
Temperature Range
I = Industrial (-40ºC to 85ºC)
Tape & Reel
T2: 2000/Reel
Product
Number
521
Package
L: PDIP
W: SOIC
Notes:
(1) All packages are RoHS compliant (Lead-free, Halogen-free).
(2) Standard lead finish is Matte-Tin.
(3) The device used in the above example is a CAT521WI-T2 (SOIC, Industrial Temperature, Tape & Reel).
ORDERING INFORMATION
CAT521WI
CAT521LI
Doc. No. MD-2003 Rev. G
12
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
REVISION HISTORY
Date
Rev. Reason
3/16/2004
E
Updated Potentiometer Characteristics
Updated Functional Diagram
07/12/2004
07/26/2007
F
Updated Potentiometer Characteristics
Added Note 3 under Potentiometer/AC Characteristics tables
Updated Ordering Information
Added MD- to document number
Add Package Outline Drawings
G
Copyrights, Trademarks and Patents
© Catalyst Semiconductor, Inc.
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
Beyond Memory™, DPP™, EZDim™, LDD™, MiniPot™, and Quad-Mode™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR
THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY
ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where
personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled
"Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical
semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Document No: MD-2003
Revision:
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Issue date:
07/26/07
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