CAT5251UI-50TE13 [CATALYST]
Quad Digitally Programmable Potentiometer (DPP) with 256 Taps and SPI Interface; 四路数字可编程电位计( DPP)与256丝锥和SPI接口![CAT5251UI-50TE13](http://pdffile.icpdf.com/pdf1/p00081/img/icpdf/CAT5251_424634_icpdf.jpg)
型号: | CAT5251UI-50TE13 |
厂家: | ![]() |
描述: | Quad Digitally Programmable Potentiometer (DPP) with 256 Taps and SPI Interface |
文件: | 总15页 (文件大小:97K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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E
CAT5251
QuadDigitallyProgrammablePotentiometer(DPP™)with
256 Taps and SPI Interface
TM
FEATURES
■ Automatic recall of saved wiper settings at
■ Four linear-taper digitally programmable
power up
potentiometers
■ 2.5 to 6.0 volt operation
■ 256 resistor taps per potentiometer
■ End to end resistance 50kΩ or 100kΩ
■ Standby current less than 1µA
■ 1,000,000 nonvolatile WRITE cycles
■ 100 year nonvolatile memory data retention
■ 24-lead SOIC and 24-lead TSSOP
■ Industrial temperature range
■ Potentiometer control and memory access via
SPI interface
■ Low wiper resistance, typically 100Ω
■ Nonvolatile memory storage for up to four wiper
settings for each potentiometer
DESCRIPTION
registers is via a SPI serial bus. On power-up, the
contents of the first data register (DR0) for each of the
four potentiometers is automatically loaded into its
respective wiper control register.
The CAT5251 is four Digitally Programmable
Potentiometers (DPPs™) integrated with control logic
and 16 bytes of NVRAM memory. Each DPP consists of
a series of resistive elements connected between two
externallyaccessibleendpoints.Thetappointsbetween
eachresistiveelementareconnectedtothewiperoutputs
with CMOS switches. A separate 8-bit control register
(WCR)independentlycontrolsthewipertapswitchesfor
each DPP. Associated with each wiper control register
are four 8-bit non-volatile memory data registers (DR)
used for storing up to four wiper settings. Writing to the
wiper control register or any of the non-volatile data
The CAT5251 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. Itisavailableinthe-40°Cto85°Cindustrial
operating temperature range and offered in a 24-lead
SOIC and TSSOP package.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC/TSSOP Package (J, W/U, Y)
R
R
H3
R
R
H2
H1
H0
24
23
22
21
20
19
18
17
16
15
14
13
HOLD
SO
A0
1
SCK
2
R
R
3
L2
W3
R
R
R
CS
SCK
SI
W0
W1
W2
W3
WIPER
CONTROL
REGISTERS
R
R
4
H2
SPI BUS
INTERFACE
H3
R
R
5
W2
L3
S
O
NC
NC
6
CAT
5251
V
7
GND
CC
R
R
8
W1
L0
WP
A0
A1
R
R
R
9
H1
H0
NONVOLATILE
DATA
REGISTERS
CONTROL
LOGIC
R
10
11
12
L1
W0
R
HOLD
A1
SI
CS
WP
R
R
L3
R
R
L2
L1
L0
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Document No. 2017, Rev. D
1
CAT5251
PIN DESCRIPTION
PIN DESCRIPTIONS
Pin
SI:
Serial Input
(SOIC/TSSOP)
Name
SO
Function
SI is the serial data input pin. This pin is used to
input all opcodes, byte addresses and data to be
written to the CAT5251. Input data is latched on the
rising edge of the serial clock.
1
2
3
4
Serial Data Output
A0
Device Address, LSB
Wiper Terminal for Potentiometer 3
RW3
RH3
SO:
Serial Output
High Reference Terminal
for Potentiometer 3
SO is the serial data output pin. This pin is used to
transfer data out of the CAT5251. During a read
cycle, data is shifted out on the falling edge of the
serial clock.
5
RL3
Low Reference Terminal
for Potentiometer 3
6
7
8
NC
VCC
RL0
No Connect
SCK:
Serial Clock
Supply Voltage
SCK is the serial clock pin. This pin is used to
synchronize the communication between the
microcontroller and the CAT5251. Opcodes, byte
addresses or data present on the SI pin are latched
on the rising edge of the SCK. Data on the SO pin is
updated on the falling edge of the SCK.
Low Reference Terminal
for Potentiometer 0
9
RH0
High Reference Terminal
for Potentiometer 0
10
11
12
13
14
15
RW0
CS
WP
SI
Wiper Terminal for Potentiometer 0
Chip Select
A0, A1: Device Address Inputs
Write Protection
These inputs set the device address when address-
ing multiple devices. A total of four devices can be
addressed on a single bus. A match in the slave
address must be made with the address input in
order to initiate communication with the CAT5251.
Serial Input
A1
Device Address
RL1
Low Reference Terminal
for Potentiometer 1
RH, RL: Resistor End Points
The four sets of RH and RL pins are equivalent to the
terminal connections on a mechanical potentiometer.
16
RH1
High Reference Terminal
for Potentiometer 1
17
18
19
20
RW1
GND
NC
Wiper Terminal for Potentiometer 1
Ground
RW:
Wiper
The four RW pins are equivalent to the wiper terminal
of a mechanical potentiometer.
No Connect
RW2
Wiper Terminal for
Potentiometer 2
CS:
Chip Select
CS is the Chip select pin. CS low enables the
21
22
RH2
RL2
High Reference Terminal
for Potentiometer 2
CAT5251 and CS high disables the CAT5251. CS
high takes the SO output pin to high impedance and
forces the devices into a Standby mode (unless an
internal write operation is underway). The CAT5251
draws ZERO current in the Standby mode. A high to
low transition on CS is required prior to any sequence
Low Reference Terminal
for Potentiometer 2
23
24
SCK
Bus Serial Clock
Hold
HOLD
being initiated. A low to high transition on CS after a valid write sequence is what initiates an internal write cycle.
WP: Write Protect
WP is the Write Protect pin. The Write Protect pin will allow normal read/write operations when held high. When WP is tied low, all
non-volatile write operations to the Data registers are inhibited (change of wiper control register is allowed). WP going low while
CS is still low will interrupt a write to the registers. If the internal write cycle has already been initiated, WP going low will have no
effect on any write operation.
HOLD: Hold
The HOLD pin is used to pause transmission to the CAT5251 while in the middle of a serial sequence without having to re-
transmit entire sequence at a later time. To pause, HOLD must be brought low while SCK is low. The SO pin is in a high imped-
ance state during the time the part is paused, and transitions on the SI pins will be ignored. To resume communication, HOLD is
brought high, while SCK is low. (HOLD should be held high any time this function is not being used.) HOLD may be tied high
directly to VCC or tied to VCC through a resistor.
Document No. 2017, Rev. D
2
CAT5251
SERIAL BUS PROTOCOL
The CAT5251 supports the SPI bus data transmission
protocol. The synchronous Serial Peripheral Interface
(SPI) helps the CAT5251 to interface directly with many
of today's popular microcontrollers. The CAT5251
containsan8-bitinstructionregister.Theinstruction set
and the operation codes are detailed in the instruction
set table 3 on page 9.
After the device is selected with CS going low the first
byte will be received. The part is accessed via the SI pin,
withdatabeingclockedinontherisingedgeofSCK.The
first byte contains one of the six op-codes that define the
operation to be performed.
DEVICE OPERATION
The CAT5251 is four resistor arrays integrated with an
SPIserialinterfacelogic,four8-bitwipercontrolregisters
and sixteen 8-bit, non-volatile memory data registers.
Each resistor array contains 255 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (RH and RL). RH and RL are
symmetricalandmaybeinterchanged.Thetappositions
between and at the ends of the series resistors are
connected to the output wiper terminals (RW) by a
CMOS transistor switch. Only one tap point for each
potentiometerisconnectedtoitswiperterminalatatime
and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the SPI bus. Additional instructions allow data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
Document No. 2017, Rev. D
3
CAT5251
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. These are stress ratings only, and functional operation of the
device at these or any other conditions outside of those listed in the operational sections
of this specification is not implied. Exposure to any absolute maximum rating for extended
periods may affect device performance and reliability.
Temperature Under Bias .................. -55°C to +125°C
Storage Temperature........................ -65°C to +150°C
Voltage on any Pin with
Respect to VSS(1)(2) ................ -2.0V to +VCC +2.0V
Recommended Operating Conditions:
V
CC with Respect to Ground ................ -2.0V to +7.0V
V
CC
= +2.5V to +6.0V
Package Power Dissipation
Temperature
Min
Max
Capability (TA = 25°C) ................................... 1.0W
Industrial
-40°C
85°C
Lead Soldering Temperature (10 secs) ............ 300°C
Wiper Current.................................................... +6mA
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC voltage on output
pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.
(2) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
POTENTIOMETER CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
RPOT
Parameter
Test Conditions
Min
Typ
100
50
Max
Units
kΩ
Potentiometer Resistance (-00)
Potentiometer Resistance (-50)
RPOT
kΩ
Potentiometer Resistance
Tolerance
+20
%
RPOT Matching
Power Rating
1
%
mW
25°C, each pot
50
IW
RW
Wiper Current
+3
mA
Wiper Resistance
IW = +3mA @ VCC =3V
IW = +3mA @ VCC = 5V
VSS = 0V
200
100
300
150
VCC
Ω
RW
Wiper Resistance
Ω
VTERM
VN
Voltage on any RH or RL Pin
Noise
GND
V
(1)
nV/ Hz
%
Resolution
0.4
Absolute Linearity (2)
Relative Linearity (3)
Temperature Coefficient of RPOT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Rw(n)(actual)-R(n)(expected)
+1
LSB (4)
LSB (4)
ppm/°C
ppm/°C
pF
(5)
(5)
Rw(n+1)-[Rw(n)+LSB
]
+0.5
TCRPOT
TCRATIO
CH/CL/CW
fc
(1)
(1)
(1)
+300
20
10/10/25
0.4
RPOT = 50kΩ(1)
MHz
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(3) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a
potentiometer. It is a measure of the error in step size.
(4) LSB = RTOT / 255 or (RH - RL) / 255, single pot
(5) n = 0, 1, 2, ..., 255
Document No. 2017, Rev. D
4
CAT5251
D.C. OPERATING CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
ICC1
Power Supply Current
fSCK = 2.5 MHz, SO Open
VCC = 6 V Inputs = GND
1
mA
ICC2
Power Supply Current
Non-volatile Write
fsck = 2.5 MHz, SO = Open
VCC = 6 V Inputs = GND
5
mA
ISB
ILI
Standby Current (VCC = 5.0V)
Input Leakage Current
VIN = GND or VCC; SO Open
VIN = GND to VCC
1
µA
µA
µA
10
10
ILO
Output Leakage Current
Input Low Voltage
VOUT = GND to VCC
VIL
-1
VCC x 0.3
VCC + 1.0
0.4
V
V
V
V
VIH
Input High Voltage
VCC x 0.7
VOL1
VOH1
Output Low Voltage (VCC = 3 V)
Output High Voltage (VCC = 6 V)
IOL = 3 mA
IOH = -1.6mA
VCC-0.8
(1)
PIN CAPACITANCE
Applicable over recommended operating range from TA=25˚C, f=1.0 MHz, VCC=+5.0V (unless otherwise noted).
Symbol
COUT
CIN
Test Conditions
Min
Typ
Max
8
Units
pF
Conditions
VOUT=0V
VIN=0V
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD,
6
pF
A0, A1)
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Document No. 2017, Rev. D
5
CAT5251
A.C. CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Test
SYMBOL
tSU
PARAMETER
Min
50
Typ
Max UNITS
Conditions
Data Setup Time
Data Hold Time
ns
ns
ns
ns
tH
50
tWH
SCK High Time
125
125
DC
tWL
SCK Low Time
fSCK
tLZ
Clock Frequency
HOLD to Output Low Z
Input Rise Time
3
50
2
MHz
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
(1)
tRI
(1)
tFI
Input Fall Time
2
CL = 50pF
tHD
tCD
tV
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
100
100
200
tHO
tDIS
tHZ
tCS
tCSS
0
250
100
250
250
250
CS Setup Time
tCSH
CS Hold Time
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(1)(2)
POWER UP TIMING
Over recommended operating conditions unless otherwise stated.
Symbol
tPUR
Parameter
Min
Typ
Max Units
Power-up to Read Operation
Power-up to Write Operation
1
1
ms
ms
tPUW
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) and t are the delays required from the time V is stable until the specified operation can be initiated.
t
PUR
PUW
CC
XDCP TIMING
Symbol
tWRPO
tWRL
Parameter
Min
5
Max Units
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
10
10
µs
µs
5
Document No. 2017, Rev. D
6
CAT5251
WRITE CYCLE LIMITS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Min
Typ
Typ
Max
Units
tWR
Write Cycle Time
5
ms
RELIABILITY CHARACTERISTICS
Over recommended operating conditions unless otherwise stated.
Symbol
Parameter
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
Max
Units
Cycles/Byte
Years
(1)
NEND
Endurance
(1)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(1)
VZAP
2000
Volts
(1)
ILTH
100
mA
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
Figure 1. Sychronous Data Timing
t
CS
VIH
CS
VIL
t
t
CSH
CSS
VIH
t
t
WL
SCK
SI
WH
t
VIL
VIH
t
H
SU
VALID IN
V
IL
t
RI
FI
t
t
V
t
t
HO
DIS
VOH
VOL
HI-Z
HI-Z
SO
Note: Dashed Line= mode (1, 1)
Figure 2. HOLD Timing
CS
t
t
CD
CD
SCK
t
HD
t
HD
HOLD
SO
t
HZ
HIGH IMPEDANCE
t
LZ
Document No. 2017, Rev. D
7
CAT5251
INSTRUCTION BYTE
INSTRUCTION AND REGISTER
DESCRIPTION
ThenextbytesenttotheCAT5251containstheinstruction
andregisterpointerinformation.Thefourmostsignificant
bits used provide the instruction opcode I3-I0. The R1
and R0 bits point to one of the four data registers of each
associated potentiometer. The least two significant bits
point to one of four Wiper Control Registers. The format
is shown in Table 2.
DEVICE TYPE / ADDRESS BYTE
The first byte sent to the CAT5251 from the master/
processor is called the Device Address Byte. The most
significant four bits of the Device Type address are a
device type identifier. These bits for the CAT5251 are
fixed at 0101[B] (refer to Table 1).
The two least significant bits in the slave address byte,
A1 - A0, are the internal slave address and must match
thephysicaldeviceaddresswhichisdefinedbythestate
of the A1 - A0 input pins for the CAT5251 to successfully
continuethecommandsequence.Onlythedevicewhich
slave address matches the incoming device address
sent by the master executes the instruction. The A1 - A0
inputs can be actively driven by CMOS input signals or
tied to VCC or VSS. The remaining two bits in the device
address byte must be set to 0.
Data Register Selection
Data Register Selected
R1
0
R0
0
DR0
DR1
DR2
DR3
0
1
1
0
1
1
Table 1. Identification Byte Format
Device Type
Identifier
Slave Address
ID3
0
ID2
1
ID1
0
ID0
1
0
0
A1
A0
(MSB)
(LSB)
Table 2. Instruction Byte Format
Instruction
Opcode
Data Register
Selection
WCR/Pot Selection
I3
I2
I1
I0
R1
R0
P1
P0
(MSB)
(LSB)
Document No. 2017, Rev. D
8
CAT5251
four Data Registers and the associated Wiper Control
Register. Any data changes in one of the Data Registers
is a non-volatile operation and will take a maximum of
5ms.
WIPER CONTROL AND DATA REGISTERS
Wiper Control Register (WCR)
The CAT5251 contains four 8-bit Wiper Control
Registers, one for each potentiometer. The Wiper
Control Register output is decoded to select one of
256 switches along its resistor array. The contents of
the WCR can be altered in four ways: it may be written
bythehostviaWriteWiperControlRegisterinstruction;
it may be written by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction; it can be modified one step at a
time by the Increment/decrement instruction (see
Instruction section for more details). Finally, it is
loaded with the content of its data register zero (DR0)
upon power-up.
If the application does not require storage of multiple
settingsforthepotentiometer;theDataRegisterscanbe
used as standard memory locations for system
parameters or user preference data.
Write in Process
The contents of the Data Registers are saved to
nonvolatile memory when the CS input goes HIGH after
a write sequence is received. The status of the internal
write cycle can be monitored by issuing a Read Status
command to read the Write in Process (WIP) bit.
INSTRUCTIONS
The Wiper Control Register is a volatile register that
loses its contents when the CAT5251 is powered-down.
Although the register is automatically loaded with the
value in DR0 upon power-up, this may be different from
the value present at power-down.
Five of the ten instructions are three bytes in length.
These instructions are:
— Read Wiper Control Register - read the current
wiperpositionoftheselectedpotentiometerintheWCR
Data Registers (DR)
— Write Wiper Control Register - change current
wiperpositionintheWCRoftheselectedpotentiometer
Each potentiometer has four 8-bit non-volatile Data
Registers. These can be read or written directly by the
host. Data can also be transferred between any of the
— Read Data Register - read the contents of the
selected Data Register
Table 3. Instruction Set
Instruction Set
WCR1/ WCR0/
Instruction
I3
I2
I1
I0
R1
R0
Operation
P1
P0
Read Wiper Control
Register
1
0
0
1
0
0
1/0
1/0
Read the contents of the Wiper Control
Register pointed to by P1-P0
Write Wiper Control Register
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
Write new value to the Wiper Control
Register pointed to by P1-P0
Read Data Register
1/0 1/0
1/0 1/0
1/0 1/0
Read the contents of the Data Register
pointed to by P1-P0 and R1-R0
Write Data Register
Write new value to the Data Register
pointed to by P1-P0 and R1-R0
XFR Data Register to Wiper
Control Register
Transfer the contents of the Data Register
pointed to by P1-P0 and R1-R0 to its
associated Wiper Control Register
XFR Wiper Control Register
to Data Register
1
0
1
1
0
0
1
0
0
0
1
0
1/0 1/0
1/0 1/0
1/0 1/0
1/0
0
1/0
0
Transfer the contents of the Wiper Control
Register pointed to by P1-P0 to the Data
Register pointed to by R1-R0
GlobalXFR DataRegisters
to Wiper Control Registers
Transfer the contents of the Data Registers
pointed to by R1-R0 of all four pots to their
respective Wiper Control Register
Global XFR Wiper Control
Registers to Data Register
0
0
Transfer the contents of both Wiper Control
Registers to their respective data Registers
pointed to by R1-R0 of all four pots
Increment/Decrement Wiper
Control Register
0
0
0
1
1
0
0
1
0
0
0
0
1/0
0
1/0
1
Enable Increment/decrement of the Control
Latch pointed to by P1-P0
Read WIP bit to check internal
write cycle status
Read Status (WIP bit)
Note: 1/0 = data is one or zero
Document No. 2017, Rev. D
9
CAT5251
— Write Data Register - write a new value to the
Control Register to the specified associated
Data Register.
selected Data Register
— Read Status - Read the status of the WIP bit which
when set to "1" signifies a write cycle is in progress.
— Global XFR Data Register to Wiper
Control Register
This transfers the contents of all specified Data
Registers to the associated Wiper Control
Registers.
The basic sequence of the three byte instructions is
illustrated in Figure 8. These three-byte instructions
exchange data between the WCR and one of the Data
Registers. The WCR controls the position of the wiper.
The response of the wiper to this action will be delayed
bytWRL.AtransferfromtheWCR(currentwiperposition),
to a Data Register is a write to non-volatile memory and
takes a minimum of tWR to complete. The transfer can
occur between one of the four potentiometers and one
of its associated registers; or the transfer can occur
betweenallpotentiometersandoneassociatedregister.
— Global XFR Wiper Counter Register to
Data Register
This transfers the contents of all Wiper Control
Registers to the specified associated Data
Registers.
INCREMENT/DECREMENT COMMAND
The final command is Increment/Decrement (Figure 9
and 10). The Increment/Decrement command is differ-
ent from the other commands. Once the command is
issued the master can clock the selected wiper up and/
or down in one segment steps; thereby providing a fine
tuning capability to the host. For each SCK clock pulse
(tHIGH)whileSIisHIGH,theselectedwiperwillmoveone
resistor segment towards the RH terminal. Similarly, for
each SCK clock pulse while SI is LOW, the selected
wiper will move one resistor segment towards the RL
terminal.
Four instructions require a two-byte sequence to
complete, as illustrated in Figure 7. These instructions
transfer data between the host/processor and the
CAT5251; either between the host and one of the data
registers or directly between the host and the Wiper
Control Register. These instructions are:
— XFR Data Register to Wiper Control Register
This transfers the contents of one specified Data
Register to the associated Wiper Control Register.
See Instructions format for more detail.
— XFR Wiper Control Register to Data Register
This transfers the contents of the specified Wiper
Figure 7. Two-Byte Instruction Sequence
SI
0
1
0
1
0
0
ID3 ID2 ID1 ID0
A2 A1 A0
A3
I3 I2 I1
Instruction
I0
R1 R0 P1 P0
Internal
Address
Register
Address
Pot/WCR
Address
Device ID
Opcode
Figure 8. Three-Byte Instruction Sequence
0
1
0
1
0
0
SI
I3
ID0 A3 A2 A1 A0
I1
P1 P0 D7 D6 D5 D4 D3 D2 D1 D0
I2
I0 R1 R0
ID3 ID2
ID1
Internal
Address
Device ID
Instruction
Opcode
Data
Register Address
Address
Pot/WCR
WCR[7:0]
or
Data Register D[7:0]
Figure 9. Increment/Decrement Instruction Sequence
0
1
0
1
0
0
SI
ID3 ID2 ID1 ID0
Device ID
I1
A3 A2 A1 A0 I3
I2
I0
R1 R0 P1 P0
I
I
D
E
C
1
I
D
E
C
n
N
N
C
2
N
C
n
Instruction
Opcode
Pot/WCR
Address 1
Data
C
Internal
Address
Register
Address
Document No. 2017, Rev. D
10
CAT5251
Figure 10. Increment/Decrement Timing Limits
INC/DEC
Command
Issued
t
WRL
SCK
SI
Voltage Out
R
W
INSTRUCTION FORMAT
Read Wiper Control Register (WCR)
DEVICE ADDRESSES
0 1 0 1 0 0 A A 1 0 0 1 0 0 P P 7 6 5 4 3
1 0 1 0
INSTRUCTION
DATA
2
2
1 0
CS
CS
Write Wiper Control Register (WCR)
DEVICE ADDRESSES INSTRUCTION
0 1 0 1 0 0 A A 1 0 1 0 0 0 P P 7 6 5 4 3
1 0 1 0
DATA
1 0
CS
CS
CS
Read Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
High Voltage
Write Cycle
0 1 0 1 0 0 A A 1 0 1 1 R R P P 7 6 5 4 3
1 0 1 0 1 0
2
2
1 0
CS
Write Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
DATA
0 1 0 1 0 0 A A 1 1 0 0 R R P P 7 6 5 4 3
1 0 1 0 1 0
1 0
CS
CS
CS
Read (WIP) Status
DEVICE ADDRESSES
INSTRUCTION
DATA
W
0 1 0 1 0 0 A A 0 1 0 1 0 0 0 1 7 6 5 4 3
2
1
0
CS
I
1 0
0 0 0 0
0
0
P
Document No. 2017, Rev. D
11
CAT5251
INSTRUCTION FORMAT (continued)
Global Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
0 1 0 1 0 0 A A 0 0 0 1 R R 0 0
CS
CS
1 0
1 0
Global Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
High Voltage
Write Cycle
0 1 0 1 0 0 A A 1 0 0 0 R R 0 0
CS
CS
1 0
1 0
Transfer Wiper Control Register (WCR) to Data Register (DR)
DEVICE ADDRESSES
INSTRUCTION
High Voltage
Write Cycle
0 1 0 1 0 0 A A 1 1 1 0 R R P P
CS
CS
1 0
1 0 1 0
Transfer Data Register (DR) to Wiper Control Register (WCR)
DEVICE ADDRESSES
INSTRUCTION
0 1 0 1 0 0 A A 1 1 0 1 R R P P
CS
CS
1 0
1 0 1 0
Increment (I)/Decrement (D) Wiper Control Register (WCR)
DEVICE ADDRESSES
0 1 0 1 0 A A 0 0 1 0 0 0 P P I/D I/D
1 0 1 0
INSTRUCTION
DATA
0
I/D I/D
CS
CS
• • •
Notes:
(1) Any write or transfer to the Non-volatile Data Registers is followed by a high voltage cycle after a STOP has been issued.
Document No. 2017, Rev. D
12
CAT5251
ORDERING INFORMATION
Prefix
Device #
Suffix
-TE13
CAT
5251
J
I
-50
Optional
Company ID
Product
Number
Tape & Reel
TE13: 2000/Reel
Package
J: SOIC
U: TSSOP
W: SOIC (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
Resistance
-50: 50kohm
-00: 100kohm
Notes:
(1) The device used in the above example is a CAT5251JI-50-TE13 (SOIC, Industrial Temperature, 50kohm, Tape & Reel)
PACKAGING INFORMATION
24-LEAD 300 MIL WIDE SOIC (J)
0.2914 (7.40) 0.394 (10.00)
0.2992 (7.60) 0.419 (10.65)
0.5985 (15.20)
0.6141 (15.60)
0.0926 (2.35)
0.1043 (2.65)
0.050 (1.27) BSC
0.0040 (0.10)
0.0118 (0.30)
0.013 (0.33)
0.020 (0.51)
0.010 (0.25)
X 45
0.029 (0.75)
0.0091 (0.23)
0.0125 (0.32)
0 —8
All Dimensions in inches (mm).
0.016 (0.40)
0.050 (1.27)
Document No. 2017, Rev. D
13
CAT5251
PACKAGING INFORMATION CON'T
24 Lead TSSOP (U)
7.8 + 0.1
-A-
7.72 TYP
6.4
4.16 TYP
4.4 + 0.1
-B-
(1.78 TYP)
3.2
0.42 TYP
0.65 TYP
0.2 C B A
ALL LEAD TIPS
LAND PATTERN RECOMMENDATION
PIN #1 INDENT.
1.1 MAX TYP
0.1 C
ALL LEAD TIPS
(0.9)
-C-
0.10 + 0.05 TYP
0.65 TYP
0.19 - 0.30 TYP
0.3 M A B S C S
SEE DETAIL A
GAGE PLANE
0.25
0.09 - 0.20 TYP
0o- 8o
0.6+0.1
SEATING PLANE
DETAIL A
All Dimensions in mm.
Document No. 2017, Rev. D
14
REVISION HISTORY
Date
Rev.
Reason
11/11/2003
C
Eliminated BGA package in all areas
Eliminated Commercial temperature range
Updated Functional Diagram
5/6/2004
D
Updated wiper resistance from 50Ω to 100Ω
Updated notes in Absolute Max Ratings
Eliminated Commercial temp range in all areas
Updated Potentiometer Characteristics table
Updated DC Characteristics table
Updated AC Characteristics table
Added XDCP Timing Table on page 6
Corrected Sychronous Data Timing (Figure 1) drawing
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
2
DPP ™
AE ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Publication #: 2017
Sunnyvale, CA 94089
Phone: 408.542.1000
Fax: 408.542.1200
Revison:
Issue date:
Type:
D
5/6/04
Advance
www.catalyst-semiconductor.com
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