CAT64LC10JA [CATALYST]
EEPROM, 64X16, Serial, CMOS, PDSO8, SOIC-8;
| 型号： | CAT64LC10JA |
| 厂家： | 
CATALYST SEMICONDUCTOR |
| 描述： | EEPROM, 64X16, Serial, CMOS, PDSO8, SOIC-8 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
E
CAT64LC10/20/40
1K/2K/4K-Bit SPI Serial EEPROM
TM
FEATURES
■ SPI bus compatible
■ Commercial, industrial and automotive
temperature ranges
■ Low power CMOS technology
■ 2.5V to 6.0V operation
■ Power-up inadvertant write protection
■ RDY/BSY pin for end-of-write indication
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Self-timed write cycle with auto-clear
■ Hardware reset pin
■ Hardware and software write protection
DESCRIPTION
TheCAT64LC10/20/40isa1K/2K/4K-bitSerialEEPROM
which is configured as 64/128/256 registers by 16 bits.
Each register can be written (or read) serially by using
the DI (or DO) pin. The CAT64LC10/20/40 is
manufactured using Catalyst’s advanced CMOS
EEPROM floating gate technology. It is designed to
endure 1,000,000 program/erase cycles and has a data
retention of 100 years. The device is available in 8-pin
DIP, SOIC and TSSOP packages.
PIN CONFIGURATION
SOIC Package (J, W)
TSSOP Package (U, Y)
DIP Package (P, L)
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
CS
SK
DI
V
RDY/BUSY
RESET
GND
DO
1
2
3
4
8
7
6
5
CS
SK
DI
V
CC
CC
RDY/BUSY
RESET
GND
RDY/BUSY
RESET
GND
V
CC
CS
DO
DO
SK
DI
SOIC Package (S, V)
TSSOP Package (UR, YR)
1
2
3
4
8
7
6
5
CS
SK
DI
V
1
2
3
4
8
7
6
5
RDY/BUSY
RESET
GND
DO
CC
V
RDY/BUSY
RESET
GND
CC
CS
SK
DI
DO
PIN FUNCTIONS
BLOCK DIAGRAM
V
GND
CC
Pin Name
CS
Function
Chip Select
ADDRESS
DECODER
MEMORY ARRAY
64/128/256 x 16
SK
Clock Input
DI
Serial Data Input
Serial Data Output
DATA
REGISTER
DO
OUTPUT
BUFFER
DI
VCC
+2.5V to +6.0V Power Supply
Ground
MODE DECODE
LOGIC
RESET
CS
GND
CLOCK
GENERATOR
DO RDY/BUSY
RESET
RDY/BUSY
Reset
SK
Ready/BUSY Status
64LC10/20/40 F02
Doc. No. 1021, Rev. C
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
CAT64LC10/20/40
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature....................... –65°C to +150°C
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Voltage on any Pin with
Respect to Ground(1) ............ –2.0V to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C)................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
Parameter
Endurance
Min.
1,000,000
100
Max.
UnitsReference
t
Tes Method
(3)
NEND
Cycles/Byte
Years
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
(3)
TDR
Data Retention
ESD Susceptibility
Latch-Up
(3)
VZAP
2000
Volts
(3)(4)
ILTH
100
mA
CAPACITANCE (T = 25°C, f= 1.0 MHz, V
=6.0V)
CC
A
Symbol
Test
Max.
Units
pF
Conditions
VI/O = 0V
VIN = 0V
(3)
CI/O
Input/Output Capacitance (DO, RDY/BSY)
Input Capacitance (CS, SK, DI, RESET)
8
6
(3)
CIN
pF
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V +0.5V, which may overshoot to V +2.0V for periods of less than 20 ns.
CC
CC
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.
CC
Doc. No. 1021, Rev. C
2
CAT64LC10/20/40
D.C. OPERATING CHARACTERISTICS
= +2.5V to +6.0V, unless otherwise specified.
V
CC
Limits
Typ.
Sym.
Parameter
Operating Current
EWEN, EWDS, READ 6.0V
Min.
Max.
UnittsTes Conditions
ICC
2.5V
0.4
1
mA
mA
mA
mA
µA
fSK = 250 kHz
fSK = 1 MHz
ICCP Program Current
2.5V
6.0V
2
3
(1)
ISB
Standby Current
3
VIN = GND or VCC
CS = VCC
ILI
Input Leakage Current
2
µA
µA
V
VIN = GND to VCC
VOUT = GND to VCC
ILO
VIL
VIH
VIL
Output Leakage Current
Low Level Input Voltage, DI
High Level Input Voltage, DI
10
–0.1
VCC x 0.7
–0.1
VCC x 0.3
VCC + 0.5
VCC x 0.2
V
Low Level Input Voltage,
V
CS, SK, RESET
VIH
High Level Input Voltage,
VCC x 0.8
VCC + 0.5
V
CS, SK, RESET
(1)
VOH
High Level Output Voltage 2.5V VCC – 0.3
V
V
V
V
V
IOH = –10µA
IOH = –10µA
IOH = –400µA
IOL = 10µA
6.0V VCC – 0.3
2.4
(1)
VOL
Low Level Output Voltage
2.5V
6.0V
0.4
0.4
IOL = 2.1mA
Note:
(1)
V and V spec applies to READY/BUSY pin also
OH OL
Doc. No. 1021, Rev. C
3
CAT64LC10/20/40
A.C. OPERATING CHARACTERISTICS
V
CC
= +2.5V to +6.0V, unless otherwise specified.
Limits
Typ.
Symbol
tCSS
tCSH
tDIS
Parameter
CS Setup Time
Min.
100
100
200
200
Max.
Units
ns
CS Hold Time
ns
DI Setup Time
ns
tDIH
DI Hold Time
ns
tPD1
Output Delay to 1
300
300
500
ns
tPD0
Output Delay to 0
ns
(2)
tHZ
Output Delay to High Impendance
Minimum CS High Time
Minimum SK High Time
ns
tCSMIN
tSKHI
250
1000
400
ns
2.5V
ns
4.5V–6.0V
2.5V
tSKLOW
Minimum SK Low Time
1000
400
ns
4.5V–6.0V
tSV
fSK
Output Delay to Status Valid
Maximum Clock Frequency
500
ns
2.5V
250
1000
0
kHz
4.5V–6.0V
tRESS
tRESMIN
tRESH
tRC
Reset to CS Setup Time
Minimum RESET High Time
RESET to READY Hold Time
Write Recovery
ns
ns
ns
ns
250
0
100
(1)(3)
POWER-UP TIMING
Symbol
tPUR
Parameter
Min.
Min.
Max.
Units
Power-Up to Read Operation
Power-Up to Program Operation
10
1
µs
tPUW
ms
WRITE CYCLE LIMIITS
Symbol
Parameter
Max.
10
Units
tWR
Program Cycle Time
2.5V
ms
4.5V–6.0V
5
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) This parameter is sampled but not 100% tested.
(3) t
and t
are the delays required from the time V is stable until the specified operation can be initiated.
PUR
PUW
CC
Doc. No. 1021, Rev. C
4
CAT64LC10/20/40
INSTRUCTION SET
Instruction
Opcode
Address
Data
Read
64LC10
10101000
10101000
10101000
10100100
10100100
10100100
10100011
10100000
10100001
A5 A4 A3 A2 A1 A0 0
A6 A5 A4 A3 A2 A1 A0
0
0
D15 - D0
D15 - D0
D15 - D0
D15 - D0
D15 - D0
D15 - D0
64LC20
64LC40
64LC10
64LC20
64LC40
A7 A6 A5 A4 A3 A2 A1 A0
Write
A5 A4 A3 A2 A1 A0 0
A6 A5 A4 A3 A2 A1 A0
0
0
A7 A6 A5 A4 A3 A2 A1 A0
X X X X X X X X
Write Enable
Write Disable
X X X X X X X X
[Write All Locations](1)
X X X X X X X X
D15–D0
(2)(3(4)
Figure 1. A.C. Testing Input/Output Waveform
(C = 100 pF)
L
V
x 0.8
CC
V
V
x 0.7
x 0.3
CC
INPUT PULSE LEVELS
REFERENCE POINTS
CC
V
x 0.2
CC
Note:
(1) (Write All Locations) is a test mode operation and is therefore not included in the A.C./D.C. Operations specifications.
(2) Input Rise and Fall Times (10% to 90%) < 10 ns.
(3) Input Pulse Levels = V x 0.2 and V x 0.8.
CC
CC
(4) Input and Output Timing Reference = V x 0.3 and V x 0.7.
CC
CC
Doc. No. 1021, Rev. C
5
CAT64LC10/20/40
DEVICE OPERATION
and data to be written are clocked into the DI pin on the
rising edge of the SK clock. The DO pin is normally in a
high impedance state except when outputting data in a
READ operation or outputting RDY/BSY status when
polled during a WRITE operation.
The CAT64LC10/20/40 is a 1K/2K/4K-bit nonvolatile
memory intended for use with all standard controllers.
The CAT64LC10/20/40 is organized in a 64/128/256 x
16 format. All instructions are based on an 8-bit format.
Therearefour16-bitinstructions:READ,WRITE,EWEN,
andEWDS.TheCAT64LC10/20/40operatesonasingle
powersupplyrangingfrom2.5Vto6.0Vandithasanon-
chipvoltagegeneratortoprovidethehighvoltageneeded
duringaprogrammingoperation.Instructions,addresses
Theformatforallinstructionssenttothisdeviceincludes
a 4-bit start sequence, 1010, a 4-bit op code and an 8-
bit address field or dummy bits. For a WRITE operation,
Figure 2. Sychronous Data Timing
RESET
t
t
t
SKLOW
SKHI
RESS
SK
t
t
DIH
DIS
DI
t
t
t
CSMIN
CSS
CSH
CS
t
t
t
t
SV
PD0, PD1
HZ
DO
t
t
SV
t
RESH
RC
RDY/BUSY
Figure 3. Read Instruction Timing
RESET
SK
CS
DI
1
0
1
0
1
0
0
0
ADDRESS*
DO
D15 D14
D1 D0
HIGH
RDY/BUSY
* Please check the instruction set table for address
Doc. No. 1021, Rev. C
6
CAT64LC10/20/40
a 16-bit data field is also required following the 8-bit
address field.
Read
UponreceivingaREADcommandandaddress(clocked
into the DI pin), the DO pin will output data one tPD after
the falling edge of the 16th clock (the last bit of the
address field). The READ operation is not affected by
the RESET input.
The CAT64LC10/20/40 requires an active LOW CS in
order to be selected. Each instruction must be preceded
by a HIGH-to-LOW transition of CS before the input of
the 4-bit start sequence. Prior to the 4-bit start sequence
(1010), the device will ignore inputs of all other logical
sequence.
Write
After receiving a WRITE op code, address and data, the
device goes into the AUTO-Clear cycle and then the
Figure 4. Write Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO
RDY/BUSY
* Please check instruction set table for address
Figure 5. Ready/BUSY Status Instruction Timing
RESET
LOW
SK
CS
WRITE INSTRUCTION
NEXT INSTRUCTION
DI
DO
HIGH
RDY/BUSY
Doc. No. 1021, Rev. C
7
CAT64LC10/20/40
WRITE cycle. The RDY/BSY pin will output the BUSY
status (LOW) one tSV after the rising edge of the 32nd
clock (the last data bit) and will stay LOW until the write
cycle is complete. Then it will output a logical “1” until the
next WRITE cycle. The RDY/BSY output is not affected
by the input of CS.
the device is deselected. The rising edge of the first “1”
input on the DI pin will reset DO back to the high
impedance state again.
The WRITE operation can be halted anywhere in the
operation by the RESET input. If a RESET pulse occurs
during a WRITE operation, the device will abort the
operation and output a READY status.
AnalternativetogetRDY/BSY statusisfromtheDOpin.
Duringawritecycle, assertingaLOWinputtotheCS pin
will cause the DO pin to output the RDY/BSY status.
Bringing CS HIGH will bring the DO pin back to a high
impedance state again. After the device has completed
a WRITE cycle, the DO pin will output a logical “1” when
NOTE: Data may be corrupted if a RESET occurs while
the device is BUSY. If the reset occurs before the BUSY
period, no writing will be initiated. However, if RESET
occurs after the BUSY period, new data will have been
written over the old data.
Figure 6. RESET During BUSY Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
1
0
0
ADDRESS*
D15
D0
DO
t
WR
RDY/BUSY
* Please check instruction set table for address
Figure 7. EWEN Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
0
1
1
HIGH-Z
HIGH
DO
RDY/BUSY
5064 FHD F09
Doc. No. 1021, Rev. C
8
CAT64LC10/20/40
RESET
ERASE/WRITE ENABLE and DISABLE
The RESET pin, when set to HIGH, will reset or abort a
WRITEoperation.WhenRESETissettoHIGHwhilethe
WRITE instruction is being entered, the device will not
executetheWRITEinstructionandwillkeepDOinHigh-
Z condition.
The CAT64LC10/20/40 powers up in the erase/write
disabledstate.Afterpower-uporwhilethedeviceisinan
erase/write disabled state, any write operation must be
preceded by an execution of the EWEN instruction.
Once enabled, the device will stay enabled until an
EWDShasbeenexecutedorapower-downhasoccured.
The EWDS is used to prevent any inadvertent over-
writing of the data. The EWEN and EWDS instructions
have no affect on the READ operation and are not
affected by the RESET input.
When RESET is set to HIGH, while the device is in a
clear/write cycle, the device will abort the operation and
will display READY status on the RDY/BSY pin and on
the DO pin if CS is low.
The RESET input affects only the WRITE and WRITE
ALL operations. It does not reset any other operations
such as READ, EWEN and EWDS.
Figure 8. EWDS Instruction Timing
RESET
SK
CS
DI
1
0
1
0
0
0
0
0
HIGH-Z
HIGH
DO
RDY/BUSY
Doc. No. 1021, Rev. C
9
CAT64LC10/20/40
ORDERING INFORMATION
P: PDIP
S: SOIC (JEDEC)
J: SOIC (JEDEC)
U: TSSOP
UR: TSSOP (Rotated)
L: PDIP (Lead free, Halogen free)
V: SOIC (JEDEC) (Lead free, Halogen free)
W: SOIC (JEDEC) (Lead free, Halogen free)
Y: TSSOP (Lead free, Halogen free)
YR: TSSOP (Rotated) (Lead free, Halogen free)
Notes:
(1) The device used in the above example is a 64LC10SI-TE13 (SOIC, Industrial Temperature, Tape & Reel)
Doc. No. 1021, Rev. C
10
CAT64LC10/20/40
PACKAGING INFORMATION
8-LEAD TSSOP (U)
+
3.0 0.1
-A-
5
8
7.72 TYP
4.16 TYP
6.4
+
4.4 0.1
-B-
(1.78 TYP)
3.2
0.42 TYP
0.65 TYP
LAND PATTERN RECOMMENDATION
0.2 C B A
ALL LEAD TIPS
1
4
PIN #1 IDENT.
SEE DETAIL A
1.1 MAX TYP
0.1
C
ALL LEAD TIPS
0.09 - 0.20 TYP
(0.9)
-C-
+
0.10 0.05 TYP
0.65 TYP
GAGE PLANE
0.25
0.19 - 0.30 TYP
0.3 M
A B S C S
0o- 8o
0.6+0.1
SEATING PLANE
DETAIL A
Doc. No. 1021, Rev. C
11
REVISION HISTORY
Date
Rev.
Reason
9/3/2004
B
Added Green packages in all areas
Updated DC Operating Characteristics table & notes
11/17/2004
C
Changed ISB from 1µA, Max to 3µA, Max in DC Operating
Characteristics table
Copyrights, Trademarks and Patents
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
2
DPP ™
AE ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
Catalyst Semiconductor, Inc.
Corporate Headquarters
1250 Borregas Avenue
Sunnyvale, CA 94089
Phone: 408.542.1000
Publication #: 1021
Fax: 408.542.1200
Revison:
C
www.catalyst-semiconductor.com
Issue date:
11/3/04
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